Programmable Logic Devices

Tutorial 1
Michal Kubíček
Department of Radio Electronics, FEEC BUT Brno
Vytvořeno za podpory projektu OP VVV Moderní a otevřené studium techniky CZ.02.2.69/0.0/0.0/16_015/0002430.
Agenda

❑ MPx-PLD course notes

❑ Basics of digital circuits
❑ Origin of FPGAs
❑ Implementation of FPGA designs

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Contact

Michal Kubíček
[email protected]

 Consulting hours:
Try any day from 7 to 14, but write me an email in advance!
Department of Radio Electronics, Technická 12
office: SD6.94,  5 4114 6578

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MPx-PLD Course

Tutorials

❑ MPA-PLD: Wednesday 13:00 – 14:40, SE 6.134

❑ MPC-PLD: Tuesday 10:00 – 11:40, SD 1.49
❑ NOT mandatory, but strongly recommended
❑ Presentations on E-learning (usualy after each tutorial)

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MPx-PLD Course

Tutorials by external staff

advanced topics, real-life examples

❑ S3 Group Praha (ASIC design)

??.??. Team work, Specifics of ASIC design (+ possible tour to company)

❑ ON Semiconductor Brno (ASIC design)

??.??. Mixed-Signal Design (ASIC)

❑ Tescan Brno, Thermo Fisher Scientific Brno (FPGA)

??.??. FPGA in electron microscopes
❑ PSI Drásov (FPGA)
??.??. FPGA + ARM = SoC

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MPx-PLD Course

PC labs
❑ MPC-PLD: 13 labs, 39 points (19 minimum)
❑ MPA-PLD: 9 labs, 36 points (18 minimum)
❑ MANDATORY!
Missing? ➔ email ➔ individual task
❑ All materials on the E-learning

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MPx-PLD Course

Points
❑ PC lab: MPC-PLD 39p / MPA-PLD 36p
minimum 50 % (19p / 18p)
❑ Final exam MPC-PLD 61p / MPA-PLD 64p
minimum 50 % from each part (30p / 32p)
▪ Written part (theory from tutorials) max. 16p / 15p, min. 8p / 7p
▪ Practical part (PC) max. 30p / 34p, min. 15p / 17p
▪ Oral part (theory from tutorials) max. 15p / 15p, min. 7b / 7p

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MPx-PLD Course

Final Exam
❑ „Must-go“ questions ("Don't know? Come next time!")
• Set of basic questions from MPx-PLD
Examples:
What is a sensitivity list of process in VHDL?
What is a LATCH?
What is a LUT in FPGA?
What is an RTL schematic?
...

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MPx-PLD Course

Study materials
❑ E-learning
❑ Online materials
▪ YouTube, Google

❑ Books:
▪ Clive Maxfield: The Design Warrior‘s Guide to FPGAs
▪ Bob Zeidman: Introduction to CPLD and FPGA Design
▪ Johnson, Graham: High-Speed Digital Design – A Handbook of Black Magic
▪ ...

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MPx-PLD Course

What will you learn?

❑ Brief introduction into FPGA world. Quick, efficient, challenging.
❑ FPGA
• Digital design in FPGA
• What are internal features of FPGA
• How to choose a suitable FPGA technology, where to use FPGA
❑ VHDL
• Syntax, coding rules
• Simulation, verification
• How to avoid common mistakes
❑ Xilinx Vivado environment

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MPx-PLD Course

Why such content?

❑ We are not going to go much deep into details (not enough time). You should
have an overview: what is possible, what are abilities and limitations of FPGAs.
The idea is, that you must know that certain features and topics exist - you can
find details on your own later (once you need it).
❑ No Verilog, only VHDL – that's life (how to use tools, scripting...)
❑ Only VHDL, not Verilog, becasue:
❑ VHDL is still dominant in FPGA segment
❑ VHDL is less prone to design error
❑ Once you know VHDL it is easy to switch to Verilog.
The other way around is much, much harder.

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MPx-PLD: what (not) to expect?

Focused on practical knowledge and skills

You should be able to work with FPGAs on your own.

• Where to use FPGA?

Performance, power consumption, price, development time...
• What kinds FPGAs are available on market?
FPGA technology, features, manufactures...

• How to configure FPGA

VHDL (Verilog), synthesis, Place and Route, Xilinx Vivado / Vitis...
• How to design a system with FPGA?
Power supply, configuration, clocking, PCB...

I'll ask such questions at final exam!

strana 12 [email protected]
MPx-PLD: what (not) to expect?

However, the theory is essential!

• Digital logic basics
Elementary combinatorial and sequential logic cells, boolean algebra...
• Digital components timing parameters
Static timing analysis, metastability, pipelining, register retiming...
• Power consumption
Static and dynamic loses, power saving principles...
• Chip manufacturing technology
(non)volatility, ionizing radiation hardness...

I'll ask also such questions at final exam!

strana 13 [email protected]
My offer

Diploma thesis, cooperation on commercial projects

❑ ERA (Brno/Pardubice): radar systems

❑ VF (Černá Hora): radiation detectors
❑ RACOM (Nové Město na Moravě): digital radio links
❑ OZM (Blížňovice/Hrochův Týnec): energetic material characterization
❑ ONsemi (Brno, Rožnov pod Radhoštěm): ASIC/FPGA design
❑ TESCAN, Thermo-Fisher, Delong Instruments (Brno): electron microscopy
❑ Photon Systems Instruments (Drásov): biotechnology instruments
❑ ...

strana 14 [email protected]
My offer

OZM Blížňovice/Hrochův Týnec

Energetic material characterization
High speed measurement of current and voltage over electric spark
• DDR3 memory interface to Xilinx Artix-7 FPGA

strana 15 [email protected]
My offer

VF Černá Hora / MU FI
❑ Proportional counters digital interface
❑ Gama / Neutron particle detection and separation

strana 16 [email protected]
My offer

Summer camp at ON Design Czech (ON Semiconductor)

❑ Introduction to analog/digital ASIC design

❑ 4 weeks during summer holidays, paid
❑ Students are selected based on interview
❑ The core of the camp is an individual project related to ASIC
design and verification
❑ During the camp there also several tutorials focused on
selected ASIC design topics

strana 17 [email protected]
MPx-PLD Course

International FPGA contest

❑ http://www.openhw.eu/
❑ Registration until 28.2.2022
❑ Participants may apply to the Xilinx University Program for a
donation of a hardware platform.
The donation request must be made by the project supervisor.

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How to start with FPGAs?

Design kits

$149 / $79 $495 / $319

$189 / $125

$1499 / $399

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How to start with FPGAs?

Design kits

€59
$144

$29

$149
€39

$45 / $75

page 20 $6 - $29 $25

How to start with FPGAs?

Design kits

$?? ???

$15 995

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How to start with FPGAs?

Programming tools

$150.00 / $99.00 $59.00 € 20

€ 24 / € 34 € 240

€ 50
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How to start with FPGAs?

Bare FPGA devices

xc3s50a xc3s500e xc6slx4 xc6slx150

€8 € 40 € 10 € 155

xc7z010 xc7a15t agln010v5

€ 55 € 25 €4 XCVU47P
> € 126 000
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How to start with FPGAs?

RedPitaya
ARM 9 dual core + Artix-7 = SoC
Integrated fast AD and DA
converters => SDR, DAQ, radar...

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 Programmable Logic Devices

Introduction
Basics of digital logic
(... that you should already know)

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Programmable Logic Devices

PLD = Programmable Logic Devices

Programmable = their function can be changed

Logic = digital ( 0 / 1 )
Device = solely integrated circuits (devices) are considered

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Basics of digital logic circuits

"Building blocks" of digital circuits

❑ Combinatorial
AND, OR, XOR, NOT gates and their derivatives

❑ Sequential
registers, the most important one is the edge triggered D type (flip-flop)

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Basics of digital logic circuits

BUFFER

A Y Y=A

INVERTOR

A Y Y = !A

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Basics of digital logic circuits

AND
A B Y=A·B Y=!(A·B)
A Y Y=A·B
B
0 0 0 1
0 1 0 1
1 0 0 1
NAND 1 1 1 0
A Y Y = ! (A · B)
B

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Basics of digital logic circuits

AND

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Basics of digital logic circuits

OR
A B Y=A+B Y=!(A+B)
A Y=A+B
Y
B
0 0 0 1
0 1 1 0
1 0 1 0
NOR 1 1 1 0
A Y Y = ! (A + B)
B

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Basics of digital logic circuits

OR

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Basics of digital logic circuits

XOR
A B Y=A + B Y=!(A + B)
A Y=A+B
Y
B
0 0 0 1
0 1 1 0
1 0 1 0
XNOR 1 1 0 1

A Y Y = ! (A + B)
B

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Basics of digital logic circuits

To remember them all...

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Basics of digital logic circuits

D-type register, level sensitive (D latch); LATCH

When CLK is active (H level), value from D input is transferred to Q output. When
CLK is inactive (L level), output stays in the last known value (memory function).

CLK D Q Q
D Q
1 0 0 1
1 1 1 0
CLK Q
0 X QPREV QPREV

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Basics of digital logic circuits

LATCH
❑ LATCH = statically driven (level sensitive) register
❑ When triggered (CLK is at H level), signal from its input is forwarded to
its output - including any glitches!!!
❑ Before CLK inactivation (HIGH to LOW transition) D must be stable for
a certain time.

CLK D Q

D CLK

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Basics of digital logic circuits

D-type register, edge sensitive (D flip-flop); Flip-flop

When there is an active (rising) edge on CLK input, value from D input is
transferred to Q output. Otherwise output stays in the last known value (memory
function).
CLK D Q Q
D Q
 0 0 1
 1 1 0
CLK Q ostatní
X QPREV QPREV

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Basics of digital logic circuits

Flip-flop
❑ Dynamically (edge) driven register (edge sensitive FlipFlop)
❑ Signal from input is transferred to the output at each active edge of CLK signal
❑ The input signal must be stable certain time before and after the active clock
edge (setup/hold time violation) => Much easier to control and verify
using CAD tools, enables unified design methodology

CLK D Q

D CLK

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Basics of digital logic circuits

Binary Hexadecimal Decimal BCD BCD

(binary) (hexadecimal)
0000 0000 0x00 0 0000 0000 0000 0x000
0000 0001 01 1 0000 0000 0001 001
0000 0010 02 2 0000 0000 0010 002
... ... ... ... ...
0001 0000 10 16 0000 0001 0110 016
0001 0001 11 17 0000 0001 0111 017
0001 0010 12 18 0000 0001 1000 018
... ... ... ... ...
1111 1101 FD 253 0010 0101 0011 253
1111 1110 FE 254 0010 0101 0100 254
1111 1111 FF 255 0010 0101 0101 255

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 Integrated Circuits

...101110110111...
...010010100010...
...100101001001...

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What is an integrated circuit?

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What is a DIGITAL integrated circuit?

Analog

Digital

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What is a DIGITAL integrated circuit?

Combinatorial logic A Y
B
IF A = 1 AND B = 1 THEN Y = 1
ELSE Y = 0

Y <= A AND B; -- VHDL

A B Y=A·B
0 0 0
0 1 0
1 0 0
1 1 1

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What is a DIGITAL integrated circuit?

Combinatorial logic

A Y
B

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What is a DIGITAL integrated circuit?

Digital circuit on a chip

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 ASIC and ASSP

ASIC
Application Specific Integrated Circuit
❑ Very simple as well as the most complex devices, both analog
and digital (mixed signal)
❑ The best solution regarding power consumption, overal
performance and chip area
❑ Very long and expensive development (high NRE costs) ➔
suitable only for large series
❑ Very difficult to modify (debugging, innovation)
❑ Not generally available

• Chipsets, control chips of HDD, SSD...

• Dedicated chips for multimedia players
• Chips for car industry (ABS controller, wiper controller,...)

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ASIC and ASSP

ASSP
Application Specific Standard Part

❑ The same design procedure and production as for ASIC

❑ Both simple and complex function
❑ Often very flexible (configurable)
❑ Often redundant (user do not need all the functionality)
❑ Commercially available
• Standard interface chipsets (USB, Serial, Ethernet...)
• A/D D/A converters
• Memories, microprocessors

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Integrated circuits

Semiconductor fabrication plant (FAB)

Dedicated factories for chip fabrication; starting from crude silicon ending with
a complete chip. Packaging is sometimes performed in a different factory
(cheaper, simpler technology).
❑ The largest chip makers: TSMC, UMC, GlobalFoundries, Intel, Samsung
❑ For each new technology node it is necessary to build a new FAB = huge expenses
(billions USD)

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Integrated circuits

Chip manufacturing
Masks, Chips, Testing, Packaging

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Integrated circuits

Basic terms (self study)

❑ Chip
❑ Semiconductor fabrication plant (FAB), Foundry
❑ Silicon Wafer
❑ (Photo)Lithographic mask
❑ Technology node
❑ Non-Recurring Engineering (NRE) Cost
http://www.youtube.com/watch?v=qm67wbB5GmI
www.youtube.com/watch?v=Q5paWn7bFg4
www.youtube.com/watch?v=d9SWNLZvA8g
www.youtube.com/watch?v=5xxEKPLlFw8
www.youtube.com/watch?v=i8kxymmjdoM
http://www.youtube.com/watch?v=gBAKXvsaEiw
http://www.youtube.com/watch?v=vK-geBYygXo

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 Implementation of digital
circuits
(in case no suitable ASSP is
available)

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Integrated Circuits
Integrated Circuits 74xx, CMOS 4000, ASSP Microcontrollers,
(low density integration) Microcomputers

Programmable Logic Devices (PLD and FPGA) Custom Chips (ASIC)

 Integrated Circuits

• "Jelly-Bean Logic" (74xx, CMOS 4000)

+ For simple and standard functions ready-to-use

– Only standard functions, low density of integration

• Microcontrollers, Microcomputers

+ Very complex functions, easy to modify, cheap

– Slow reaction on inputs, modest performance

• Programmable logic devices (PLD / FPGA)

+ Complex functions, fast response, easy to modify

– More complex development (=expensive), power consumption

• Custom Chips

+ Arbitrary function, highest performance

– Very expensive and long development, fixed function
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 Integrated Circuits
Performance Power Price Development Flexibility
Consumption Time

• 74xx
CMOS 4000

• Microcontroller

• FPGA, CPLD

• ASIC 10 ks
106 ks

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 Origin of SPLD/CPLD

...101110110111...
...010010100010...
...100101001001...

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Origin of SPLD/CPLD

❑ Advent of integrated circuits (70‘):

Only simple ASSPs available (74xx; Jelly-Bean Logic) the other alternative being
ASICs. Low level of integration, very difficult to change functionality of the design
(need to change chips and interconnect)

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Origin of SPLD/CPLD

Standard Integrated Circuits series 74xx and CMOS 4000

„Jelly Bean Logic"

74xx174 / CMOS40174
74xx00 / CMOS4000 6 x D Flip-Flop
4 x 2-input NAND

❑ xx157 2-input MUX

74xx04 / CMOS4004 ❑ xx141 Decoder BCD -> Decimal
6 x NOT (inverter) ❑ xx283 4-bit Adder
❑ xx181 4-bit ALU

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Origin of SPLD/CPLD

Early 70': First PLD (PROM):

• Generally available PROM memory ➔ logic generator
• Memory 8 kb (1024 x 8b): up to 8 arbitrary combinatorial functions of up to 10 inputs and
one output variable (signal).
• Technology: PROM, EPROM, EEPROM

inputs AND minterms OR outputs

stage stage
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FIXED PROGRAMMABLE
Origin of SPLD/CPLD

PROM structure
AND stage OR stage

decoder
Full

OR array
(summation)

OR array inputs

amplifier
(minterms)

Output

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Origin of SPLD/CPLD

Memory array 16x1b

PROM structure:
d c b a y minterm
0 0 0 0 0 /a·/b·/c·/d ❑ By adding minterms it is possible to compose
0 0 0 1 0 a·/b·/c·/d any combinatorial logic function
0 0 1 0 0 /a·b·/c·/d
0 0 1 1 0 a·b·/c·/d ❑ One minterm = one memory cell (one bit)
0 1 0 0 0 /a·/b·c·/d
0 1 0 1 0 a·/b·c·/d ❑ Function with 4 inputs and one output ➔ 16b
0 1 1 0 1 /a·b·c·/d memory (4-bit address, 1-bit data)
0 1 1 1 0 a·b·c·/d
1 0 0 0 1 /a·/b·/c·d
1 0 0 1 1 a·/b·/c·d
1 0 1 0 0 /a·b·/c·d 16x1b
RAM/ROM
1 0 1 1 0 a·b·/c·d
1 1 0 0 1 /a·/b·c·d
1 1 0 1 1 a·/b·c·d
1 1 1 0 0 /a·b·c·d
1 1 1 1 0 a·b·c·d

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Origin of SPLD/CPLD

Memory 16x1b SPLD = Simple Programmable Logic Device

a b d
Address Data
c y
d c b a y minterm 0 0 0 0
0 0 0 0 0 /a·/b·/c·/d b
c
0 0 0 1 0 a·/b·/c·/d 0 0 0 1 a
0 0 1 0 0 /a·b·/c·/d
0 0 1 1 0 a·b·/c·/d d 1 1 0 0
0 1 0 0 0 /a·/b·c·/d
0 1 0 1 0 a·/b·c·/d 1 1 0 0
0 1 1 0 1 /a·b·c·/d
0 1 1 1 0 a·b·c·/d
1 0 0 0 1 /a·/b·/c·d y = /a·/b·c·d + /a·/b·/c·d + a·/b·/c·d + a·/b·c·d + /a·b·c·/d =
1 0 0 1 1 a·/b·/c·d = /b·d + /a·b·c·/d
1 0 1 0 0 /a·b·/c·d
1 0 1 1 0 a·b·/c·d

Term Minterms
1 1 0 0 1 /a·/b·c·d
1 1 0 1 1 a·/b·c·d
1 1 1 0 0 /a·b·c·d
1 1 1 1 0 a·b·c·d Sum Of Products
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Origin of SPLD/CPLD

a b
d c b a y
0 0 0 0 0 0 1 0 1
0 0 0 1 1 c
1 0 1 0 Function XOR (XNOR)
0 0 1 0 0
0 0 1 1 1 d 0 1 0 1 4 inputs = 8 terms
0 1 0 0 0
0 1 0 1 1 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0 XOR cannot be minimized ➔
1 0 0 1 1
1 0 1 0 0 high implementation demands ➔
1 0 1 1 1 ideally suitable for PROM structure
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
For simple functions the PROM structure is
1 1 1 1 1 not so efficient

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Origin of SPLD/CPLD

Complete decoder (AND stage)

❑ Complex combinatorial digital circuitry
• 4 inputs => 24 = 16 outputs
• 6 inputs => 26 = 64 outputs
• 10 inputs => 210 = 1024 outputs (!!!)
❑ Large number of inputs = large delay = low operating frequency of
the design = problem

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Origin of SPLD/CPLD

❑ SPLD = Simple Programmable Logic Device

❑ Mid 70': PLDs (PLA, PAL, GAL)
• Faster than PROM
• Better silicon utilization
• Cannot implement arbitrary function of input signals, because of limited number of
OR stage inputs (terms) for each output (function), but it is sufficient for most
real-world applications

SPLD structure
inputs AND product terms OR outputs
stage stage

PROGRAMMABLE FIXED
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Origin of SPLD/CPLD

❑ PAL
• Programmable AND stage, fixed OR stage
• First commercially successful PLDs (GAL16V8, 20V8, 22V10)
❑ PLA
• Both AND and OR stages are programmable
• Slower, more expensive
• Not successful, but later the structure was reused in some CPLDs

inputs AND product terms OR outputs

stage stage

PROGRAMMABLE FIXED
(PROGRAMMABLE)
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Origin of SPLD/CPLD

PAL structure
PAL structure with 5 inputs and two macrocells featuring 4 terms each.

Macrocell

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Origin of SPLD/CPLD

PAL structure
Example of combinatorial function implemented in PAL structure
d

c y
b
a

a b

0 0 0 0
c
0 0 0 1
d 1 1 0 0
1 1 0 0

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Origin of SPLD/CPLD

PAL structure
XOR (XNOR) function: number of required terms = 2(n-1), where n is number of inputs.
3 inputs => 4 terms

a b

0 1 0 1
c
1 0 1 0

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Origin of SPLD/CPLD

PAL – first SPLDs

❑ Many types, different features of device outputs

Problem: one had to keep stock of many different PALs

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SPLD – PAL 16L8

OutputMacrocell

Logic Macrocell
SPLD – PAL 16R4
Origin of SPLD/CPLD

GAL – "modern" SPLDs

❑ Unified output macrocell
❑ Different programmable array sizes
❑ GAL16V8, GAL20V8 (all outputs have same mode)
❑ GAL22V10 (independent outputs)
❑ Reduced number of different PLDs in stock
❑ Still available (3 - 6 EUR)
❑ Different speed versions (3,5-15 ns) and power consumption

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22V10 SPLD
Origin of SPLD/CPLD

SPLD in 80‘:
❑ Lower number of parts on board
❑ Can be used for non-standard functions
❑ Easier to change function (system modifications, debug)

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Origin of SPLD/CPLD

Typical devices with SPLDs

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Origin of SPLD/CPLD

80`s of 20th century: about 150 digital circuits on a single PCB

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 Origin of SPLD/CPLD

SPLD today
❑ Low density of integration
❑ High power consumption
❑ Only for special application (vintage...)

http://dangerousprototypes.com/2012/10/19/7400-competition-entry-rf74xxid-a-passive-rfid-
tag-from-7400-discrete-logic/

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Origin of SPLD/CPLD

More complex PLDs needed!

❑ First the basic structure was simply enlarged ➔ MII: MegaPAL 64R32,
unsuccessful (slow, power hungry)
❑ Solution: more SPLDs on a single chip + programmable interconnect
❑ Result: 1984 – Altera CPLD

CPLD = Complex Programmable Logic Device

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Origin of SPLD/CPLD

CPLD structure
Interconnection is not complete (cannot connect anything-to-anything,
all-to-all) ➔ not so flexible, but higher performance

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Origin of SPLD/CPLD

CPLD – XC9500XL (1998)

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Origin of SPLD/CPLD

XC9500XL
❑ 36, 72, 144 or 288 macrocells
❑ 5-6 ns macrocell delay
❑ 34 to 192 user IO
❑ Non-volatile, ISP programming
❑ Core power supply 3.3V, IOs 3.3V or 2.5V
❑ IO 5V tolerant
❑ Still available (stocked), price from 1 EUR

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Origin of SPLD/CPLD

XC9500XL
❑ IO 5V tolerant

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Origin of SPLD/CPLD

CPLD – CoolRunner II

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Origin of SPLD/CPLD

CoolRunner II – macrocell

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Origin of SPLD/CPLD

CoolRunner II
❑ 32 až 512 macrocells
❑ Macrocell delay 3.8 to 7.6 ns (frequency 323 až 179 MHz)
❑ 33 to 270 user IO
❑ Current consumption at 50 MHz 2.5 to 55 mA (depends on size)
❑ VCCIO 1.5V, 1.8V, 2.5V and 3.3V
❑ VCC 1.8V (180 nm CMOS)

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Origin of SPLD/CPLD

Modern CPLD – properties

❑ Price from 1 EUR (32 Macrocell) to 50 EUR (512 Macrocell)
❑ Very low power consumption (static only few tens of μW)
❑ Simple to use, non-volatile
❑ Integrated blocks for clock generation, clock control (PLL, DLL), standard
interfaces (SPI, I2C), memories (RAM, FLASH)
❑ Smaller and better predictable signal propagation delay than in FPGA

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Origin of SPLD/CPLD

Modern CPLD – usage

❑ IO expansion (processors...)

❑ Voltage level translation (multi-chip systems)

❑ Power control and monitoring (power sequencers)

❑ FPGA configuration control

❑ Initialization control (DSP, processors)

❑ Multi-channel PWM drivers

page 87 [email protected]
Origin of SPLD/CPLD

page 88 [email protected]
Origin of SPLD/CPLD

CPLD today
Traditional CPLDs are no longer developed
(the last "new" Xilinx CoolRunner2 @ 2002).

Still well available, including 5V versions.

Replaced by FLASH-based FPGAs (Intel MAX 10, Lattice MachXO3, Microsemi

IGLOO2)

❑ Non-volatile => instant ON, no need for external FLASH memory

❑ Unified design flow with other (SRAM-based) FPGAs

❑ Smaller granularity is more efficient for current digital systems

page 89 [email protected]
 Origin of FPGAs

...101110110111...
...010010100010...
...100101001001...

page 90 [email protected]
Origin of FPGA

Full-custom ASIC drawbacks

Full custom ASIC design is very expensive and takes a long time (1-3 years)
Non-Recurring Engineering (NRE) costs: price of chip development, including
prototype samples, several iterations of redesing, testing, certification... These costs
create important part of the ASIC final price.
First ASICs were designed at transistor level – each transistor could had been (and often
was) just as large as required, so that chip area is utilized as efficiently as possible.
Today this is case only for analog portion of the ASICs.

page 91 [email protected]
Origin of FPGA

Problem #1: Design Productivity Gap

Chip manufacturing technology improves much faster (~2x) than ability of designers to
utilize it efficiently (development of CAD tools)

Result:
Careful design is much more
expensive than
manufacturing ➔ it is better
to design faster and slightly
less efficiently

page 92 [email protected]
Origin of FPGA

Problem #2: Verification Gap

Another problem:
It is not possible to verify, that a new design is
free of bugs
➔ only limited amount of testing (simulations),
try to cover only the "real-life" or most critical
aspects
➔ there are often many bugs in manufactured
chips (sometimes fixed in next revisions of the
chip)

page 93
Origin of FPGA

A new idea appeared:

Manufacture large number (=cheap) of a basic chip that could be shared among several different
project. Customer can define the chip function by definition of few customizable layers.

Advantages
❑ The basic chip is manufactured in large series for many different customers ➔ it is cheap
❑ Only small part of the design is unique ➔ faster and cheaper development
❑ Only small part of the design is unique ➔ faster and cheaper verification

page 94 [email protected]
Origin of FPGA

The idea
Basic chip with customizable layer

page 95 [email protected]
Origin of FPGA

Basic chip Základní čip

Transistor array (mid 70's)

Array of unconnected transistors (100-500), user can
define two metal layers as a custom interconnect
Micromatrix – interconnection defined by hand-drawing,
then manufactured at FAB.
Micromosaic – text-defined interconnection; one of the Naprogramovaný čip
first usage of CAD systems. Metallization is done in FAB.
The chip can be "programmed", but not reprogrammed.
Unsuccessful.

Metalizace definovaná
uživatelem
page 96 [email protected]
Origin of FPGA

Basic chip
Transistor array

Configured chip

User Defined Metal Layers

page 97
Origin of FPGA

Basic chip
Gate Arrays (end of 70‘s, commercially available from mid 80‘s):
Basic chip is composed of cells, which contain several transistors and resistors. The function
of the cell as well as cell interconnection is defined by user and implemented using metal
layers (in FAB). One time programmable, unsuccessful.

page 98 [email protected]
Origin of FPGA

Basic chip
Structured ASIC (beginning of 90‘, than again after 2001)
Array of prefabricated configurable cells, that are programmed using user- defined metal
layers ➔ "programming" in FAB, one time programmable.
Today used in some cases when FPGA design is mature and ready for production: there is no
need for FPGA reprogrammability, so the design (configuration) is "frozen" to metal layers.

page 99 [email protected]
Origin of FPGA

FPGA: Electronically programmable interconnect and

cell function
1984: firs commercially available FPGA (Field Programmable Gate Array; Xilinx)

page 100 [email protected]

Origin of FPGA

Basic cell: LUT (Function Generator) and Flip-Flop

Data
Address
b
Inputs

Function Flip- a d c b a y minterm

generator Flop 0 0 0 0 0 /a·/b·/c·/d
0 0 0 0 0 0 0 1 0 a·/b·/c·/d
c 0 0 1 0 0 /a·b·/c·/d
0 0 0 1 0 0 1 1 0 a·b·/c·/d
d 0 1 0 0 0 /a·/b·c·/d
d 1 1 0 0 0 1 0 1 0 a·/b·c·/d
c y 0 1 1 0 1 /a·b·c·/d
b
1 1 0 0 0 1 1 1 0 a·b·c·/d
a 1 0 0 0 1 /a·/b·/c·d
1 0 0 1 1 a·/b·/c·d
1 0 1 0 0 /a·b·/c·d
y = /a·/b·c·d + /a·/b·/c·d + a·/b·/c·d + a·/b·c·d + /a·b·c·/d = 1 0 1 1 0 a·b·/c·d
= /b·d + /a·b·c·/d 1 1 0 0 1 /a·/b·c·d
1 1 0 1 1 a·/b·c·d
1 1 1 0 0 /a·b·c·d
page 101 1 1 1 1 0 a·b·c·d
[email protected]
 Origin of FPGA

Programmable interconnect and cell function

Similar to structured ASIC, but configuration is done using electronic switches, which can be
reprogramed (user needs only a PC and programmer, no need to go to FAB)

Xilinx XC3000 Family FPGA (1998)

page 102 [email protected]

Origin of FPGA

FPGA versus CPLD?

❑ The same basic structure, so why CPLDs are no longer around?

FPGA CPLD

page 103 [email protected]

Origin of FPGA

FPGA versus CPLD

So what is the main difference??? Granularity!
CPLD cell
FPGA cell coarse grain
fine grain architecture
architecture
Flip-
Flop

Inputs
Function
generator
Inputs

Function Flip-
generator Flop

page 104 [email protected]

Digital design for ASIC and FPGA

page 105 [email protected]

Digital design

Digital design: WHY?

When to bother with ASIC/FPGA design?
Well, I need a digital system but...
❑ there is no suitable ASSP available
❑ microprocessor is too slow for the required function
❑ combination of COTS components would result in too expensive / unreliable /
slow / power-hungry solution
❑ I want to improve some older device (integration, improvement)
❑ ...

page 106 [email protected]

Digital design

Digital design: HOW?

❑ First digital systems were drawn as
schematics using basic logic gates
❑ Slow process of optimization (by hand)
❑ Time consuming, prone to error
❑ Very difficult to verify the design

page 107 [email protected]

Digital design

Digital design: HOW?

❑ Today only CAD tools
❑ Different methods of system description
• Text based – Hardware Description Languages (HDL)
ABEL, VHDL, Verilog, SystemVerilog, System C...
• Schematic, State Diagrams
• IP cores
• Matlab / Simulink
• ...
ENTITY prepinac IS PORT(
a,b,c: IN STD_LOGIC;
volba: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
y: OUT STD_LOGIC);
END prepinac;
ARCHITECTURE Behavioral OF prepinac IS BEGIN
y <= a WHEN volba = "00" ELSE
b WHEN volba = "01" OR volba = "10" ELSE
c;
END Behavioral;

page 108 [email protected]

Digital design

Digital design synthesis

❑ Conversion of design description (textual, schematic...) to a circuit composed of generic
digital components (gates) including optimization (logic minimization...).
❑ Synthesis tools are integrated in modern FPGA CAD systems
❑ Output of the synthesis tool is an RTL schematic (Register Transfer Logic)

ENTITY prepinac IS PORT(

a,b,c: IN STD_LOGIC;

Synthesis
volba: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
y: OUT STD_LOGIC);
END prepinac;
ARCHITECTURE Behavioral OF prepinac IS BEGIN
y <= a WHEN volba = "00" ELSE
b WHEN volba = "01" OR volba = "10" ELSE
c;
END Behavioral;

page 109 [email protected]

Digital design

What to do with RTL schematic?

In theory, it can be used for both FPGA and ASIC. User must consider target
number of devices, required performance, power consumption, time of
development (time to market), need for update (modify/change its function)...

$$
$
$ $$
$ $
$
$

page 110 [email protected]

Digital design

FPGA versus ASIC

Chip area 30-40X 1X

Power consumption 12-14X 1X
Performance (speed) 1X 3-5X
FPGA ASIC

page 111 [email protected]

 Implementation of a digital
system in an FPGA

page 112 [email protected]

Implementation (FPGA)

Digital design synthesis

❑ Conversion of design description (textual, schematic...) to a circuit composed of generic
digital components (gates) including optimization (logic minimization...).
❑ Synthesis tools are integrated in modern FPGA CAD systems
❑ Output of the synthesis tool is an RTL schematic (Register Transfer Logic)

ENTITY prepinac IS PORT(

a,b,c: IN STD_LOGIC;

Synthesis
volba: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
y: OUT STD_LOGIC);
END prepinac;
ARCHITECTURE Behavioral OF prepinac IS BEGIN
y <= a WHEN volba = "00" ELSE
b WHEN volba = "01" OR volba = "10" ELSE
c;
END Behavioral;

page 113 [email protected]

Implementation (FPGA)

Output of a synthesis tool: RTL schematic

More or less independent on the target FPGA, in theory could be used even for ASIC.

page 114
Implementation (FPGA)

Output of a synthesis tool: RTL schematic

Implementation (FPGA)

Translate and Map (part of synthesis)

Constraints
FREQ "clk" = 80 MHz
LOC "clk" = 193
LOC "Tx_data" = 87
...

page 116 [email protected]

Implementation (FPGA)

MAP result each LUT has already its own function

O = ((I0 * I1 * !I2 * !I3) + (!I0 * !I1 * I2 * I3) + (I0 * I1 * I2 * I3) + (!I0 * !I1 *
!I2 * !I3));

page 117
Implementation (FPGA)

MAP result: technology schematic

Implementation (FPGA)

Cell placement: PLACE

(PAR = P&R = Place and Route)
Partially random process with random initial conditions
Can give different results for each run (difference in maximum design
frequency, up to several tens of %)
PAR result (Virtex-5 70FXT, 60%)

Cell interconnection: ROUTE

(PAR = P&R = Place and Route)

page 120
PAR result (Virtex-5 70FXT, 60%)

LUT + flip-flops

Global (long)
interconnection

Local (short)
interconnection

Switching matrix

Dedicated arithmetic
interconnection

page 121 [email protected]

 Where can you find FPGAs?

page 122 [email protected]

What is FPGA good for?

FPGA - applications
• Digital signal processing (DSP)
• Software Defined Radio (SDR)
• Radar, military, aerospace
• Security, ciphering

page 123 [email protected]

What is FPGA good for?

FPGA - applications
• Data transmission – Ethernet Switches (CISCO…), SONET
• Video processing, machine vision, encoders, decoders (DVB-x…)
• Embedded applications, SoC, handheld devices

page 124 [email protected]

What is FPGA good for?

Data Centers

page 125 [email protected]

What is FPGA good for?

Data Centers

Introduction to Parallel Computing with

OpenCL™ on FPGAs

page 126 [email protected]

What is FPGA good for?
What is FPGA good for?

GPS satellites, Mars Reconnaissance Orbiter,

Mars Explorer Rover 1 a 2 (Spirit, Opportunity)

page 128 [email protected]

Thank You For Your Attention