ASSIGNMENT 3

ON TOPICS:
1. CONTACT AND VIA
2. ADVANTAGES OF USING MULTIPLE VIAS
3. PINCH-OFF
4. P-CELL
5. LATCH-UP
6. MOS CAPACITOR
7. BODY EFFECT

Submitted By:
Arnon Pukhrambam
Trainee, KNK Technologies
CONTACT AND VIA:
Contact is the connection between the diffusion layers (Source and Drain) and metal 1 layer.
It is generally made up of aluminium. Via is used to make connections between two metal
layers. A hole is made through the insulating medium and tungsten is generally used to
connect the metal layers.

ADVANTAGES OF USING MULTIPLE VIAS:

More number of vias means lesser resistivity. Let us consider two 5 ohm resistors connected
in parallel. When we calculate the equivalent resistance, it becomes 2.5 ohms. If we increase
the number of resistors connecting in a parallel manner, the resistance keeps reducing.
Similarly, via also has some resistance and if we increase the number of vias which are
connected in a parallel way, the equivalent resistance reduces.
The sizes of vias are really small generally having the size of about 0.2x0.2 um. So, when
some large amount of current passes through it (maybe because of some voltage or current
spikes), this area gets heated up and there is some chance that the via breaks. So, in case one
via breaks, there are other vias to keep the metal lines connected.

PINCH-OFF:

Fig. N-channel MOSFET during pinch-off

When we apply some gate voltage on a MOSFET and when the gate voltage becomes equal
to or more than the threshold voltage, an inversion layer or a channel is formed. When we
keep the gate voltage constant and apply some drain voltage, current starts flowing from
Drain to Source or from Source to Drain. The MOSFET is said to be working in linear
region when VGS> Vth and the overdrive voltage (VGS-Vth) is greater than VDS. But if
keep the gate voltage constant and further increase the Drain voltage, there will be a time
when Gate voltage is equal to the Drain voltage. So the above equation becomes,
VGS-Vth >= VDS
 Vth >= VGS-Vth
 Vth >= 0 (Gate voltage=Drain voltage)
The threshold voltage represents how large the channel will become when gate voltage is
applied. In this case, the inversion layer becomes zero or in practical very near to zero. When
this inversion layer or channel width becomes zero is the pinch-off. When pinch-off occurs,
the Drain current becomes constant even if Drain voltage is increased.

P-CELL:
P-Cell stands for parameterized cell, a concept used widely in the automated design of
analog integrated circuits. It represents a part or a component of the circuit whose structure is
dependent on one or more parameters. It is a cell which is automatically generated by EDA
software based on the values on these parameters.

LATCH UP:
A latch-up is a type of short circuit which can occur in an integrated circuit (IC). More
specifically it is the inadvertent creation of a low-impedance path between the power supply
rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning
of the part, possibly even leading to its destruction due to overcurrent. A power cycle is
required to correct this situation.
A single event latch-up is a latch-up caused by a single event upset, typically heavy ions or
protons from cosmic rays or solar flares.
The parasitic structure is usually equivalent to a thyristor (or SCR), a PNPN structure which
acts as a PNP and an NPN transistor stacked next to each other. During a latch-up when one
of the transistors is conducting, the other one begins conducting too. They both keep each
other in saturation for as long as the structure is forward-biased and some current flows
through it - which usually means until a power-down. The SCR parasitic structure is formed
as a part of the totem-pole PMOS and NMOS transistor pair on the output drivers of the
gates.
The latch-up does not have to happen between the power rails - it can happen at any place
where the required parasitic structure exists. A common cause of latch-up is a positive or
negative voltage spike on an input or output pin of a digital chip that exceeds the rail voltage
by more than a diode drop. Another cause is the supply voltage exceeding the absolute
maximum rating, often from a transient spike in the power supply. It leads to a breakdown of
an internal junction. This frequently happens in circuits which use multiple supply voltages
that do not come up in the required sequence on power-up, leading to voltages on data lines
exceeding the input rating of parts that have not yet reached a nominal supply voltage.
Latch-ups can also be caused by an electrostatic discharge event.

Fig. SCR formation in CMOS

MOS CAPACITOR:
MOS (Metal Oxide Silicon) capacitor is a semiconductor device and it is part of MOSFET
(Metal Oxide Silicon Field Effect Transistor). It is used to explain the basic concept of how
MOSFET works and some basic physical characteristics of the FET device.
MOS cap itself doesn’t do much but it provides an important function for the FET; the
ability to trap charges at the oxide-silicon surface (which is later used in FETs). We know
that conductors (metals), insulator, and semiconductors all have distinct band structure.
When these materials come in contact with one another in equilibrium, they all must share
the same Fermi energy
Important Terms
Couple terms that need to be defined first.
Flat-band voltage Vfb: At equilibrium the valence and conduction band of silicon is curved
at the oxide-silicon interface. Flat-band voltage is the voltage required to make these energy
bands flat.
For p-type silicon body the flat-band voltage would be negative while for n-type body the
voltage would be positive.
One equation that we would use is Vg (voltage bias at metal, or gate bias) = Vfb + Φs (work
function of silicon) + Vox (voltage across oxide)
Vg=Vfb+ϕs+Vox
MODES OF OPERATION
Accumulation
If we apply a negative voltage at the polysilicon, an electric field will form pointing from the
silicon to the metal. This will cause electrons to move towards ground end or technically
move from silicon to metal. This forces the oxide-silicon contact region to be further filled
with holes. From band diagram perspective, we see that energy band at the oxide-silicon
region is more p-type and we call this accumulation. In accumulation the device behaves like
a capacitor. In this case, the equation mentioned before can be written as Vox = Vg – Vfb.
Φs is ignored in case because it is much smaller than the gate bias and the flat-band voltage.
The amount of charge inside the capacitor is related by Vox = Vg – Vfb = Qacc/Cox, where
Cox is defined as εoxAox/tox.

Fig. Accumulation of charges in MOSCAP

Depletion & Inversion

If we apply a positive voltage at the gate to a p-type MOS device, the electric field will point
from the gate to the semiconductor body. Depending on the magnitude of voltage applied,
we will end up in two cases, surface depletion and inversion. The minimum gate voltage that
will transition the MOS device from Depletion to Inversion is called the Threshold Voltage
(VTH). For a p-type body: VTH=VFB+(4qϵNaϕ)1/2 / Ci+2ϕF
Depletion

Since we are applying a positive gate voltage to a p-type body, we will be attracting the
minority carrier (electrons) to the oxide-semiconductor interface. As these electrons arrive at
the interface, they will form a depletion region. As far as MOS capacitance is concerned, this
looks like two series capacitors: a capacitor across the oxide (C ox) and a capacitor across the
new depletion region (Cw = εSiWdepletion/tdepletion).

Inversion
Inversion occurs once we have built up so many minority carriers at the Oxide-
Semiconductor interface that this region begins to act as though it has the opposite doping
type. For example, for a p-type body, inversion occurs when there are so many electrons at
the interface that the region very close to the oxide begins to act as though it was n-type. In
the inversion region, the capacitance depends on the frequency of the gate voltage.
High Frequency (HF): At high frequencies, the minority carriers do not have enough time
to diffuse through the depletion region. Instead, they change the width of the depletion
region.
Cmin=Cox / 1+ (ϵoxWmax / ϵSitox)
Low Frequency(LF): At low frequencies, the minority carriers have enough time to diffuse
through the depletion region and join the inverted region at the oxide-semiconductor
interface.

BODY EFFECT:
In n-channel enhancement-mode devices, a conductive channel does not exist naturally
within the transistor, and a positive gate-to-source voltage is necessary to create one such.
The positive voltage attracts free-floating electrons within the body towards the gate,
forming a conductive channel. But first, enough electrons must be attracted near the gate to
counter the dopant ions added to the body of the MOSFET; this forms a region with no
mobile carriers called a depletion region, and the voltage at which this occurs is the threshold
voltage of the FET. Further gate-to-source voltage increase will attract even more electrons
towards the gate which are able to create a conductive channel from source to drain; this
process is called inversion. The reverse is true for the p-channel "enhancement-mode" MOS
transistor. When VGS = 0 the device is “OFF” and the channel is open / non-conducting.
The application of a negative (-ve) gate voltage to the p-type "enhancement-mode"
MOSFET enhances the channels conductivity turning it “ON”.
In contrast, n-channel depletion-mode devices have a conductive channel naturally existing
within the transistor. Accordingly, the term threshold voltage does not readily apply to
turning such devices on, but is used instead to denote the voltage level at which the channel
is wide enough to allow electrons to flow easily. This ease-of-flow threshold also applies to
p-channel depletion-mode devices, in which a negative voltage from gate to body/source
creates a depletion layer by forcing the positively charged holes away from the gate-
insulator/semiconductor interface, leaving exposed a carrier-free region of immobile,
negatively charged acceptor ions.
For the n-channel depletion MOS transistor, a negative gate-source voltage, -VGS will
deplete (hence its name) the conductive channel of its free electrons switching the transistor
“OFF”. Likewise for a p-channel "depletion-mode" MOS transistor a positive gate-source
voltage, +VGS will deplete the channel of its free holes turning it “OFF”.
The body effect is the change in the threshold voltage by an amount approximately equal to
the change in the source-bulk voltage, VSB, because the body influences the threshold
voltage (when it is not tied to the source). To understand this effect suppose VS = 0 and VD
= 0 and VG is somewhat less than VTH so that depletion region is formed under the gate but
inversion channel does not exist. As VB becomes more negative (i.e. VB < V S where VS =
0) more holes are attracted to the substrate connection leaving a larger negatively charged
ions behind i.e. the depletion region becomes wider. It can be thought of as a second gate,
and is sometimes referred to as the back gate, and accordingly the body effect is sometimes
called the back-gate effect.
For an enhancement-mode nMOS MOSFET, the body effect upon threshold voltage is
computed according to the Shichman–Hodges model, which is accurate for older process
nodes, using the following equation:
VTN = VTO + γ (√|VSB+2ϕF - √|2Φf|)
Where VTN is the is the threshold voltage when substrate bias is present, VSB is the source-
to-body substrate bias, 2Φf is the surface potential, and VTO is threshold voltage for zero
substrate bias, γ = (tox/ϵox) √2qϵsiNA is the body effect parameter, tox is oxide thickness,
ϵox is oxide permittivity, ϵsi is permittivity of silicon, NA is doping concentration, q is
elementary charge.