Chapter 6: Synchronous Sequential

Circuits
Trương Ngọc Sơn, Ph.D
 Synchronous sequential circuit
• Combinational logic circuits: The outputs are determined
fully by the present values of inputs
• Flip-flop: The output depends on the state of the flip-flop
rather than the value of its inputs at any given time; the
inputs cause changes in the state
• Sequential circuit: The outputs depend on the past behavior
of the circuit, as well as on the present values of inputs
• Synchronous sequential circuit: clock signal is used to
control the operation of a sequential circuit
• The alternative, in which no clock signal is used, is called
an asynchronous sequential circuit

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 Synchronous sequential circuit
• A sequential circuit is a circuit with memory, which
forms the internal state of the circuit.
• Unlike a combinational circuit, in which the output is a
function of input only, the output of a sequential circuit
is a function of the input and the internal state. The
synchronous design methodology is the most commonly
used practice in designing a sequential circuit. In this
methodology, all storage elements are controlled (i.e.,
synchronized) by a global clock signal and the data is
sampled and stored at the rising or falling edge of the
clock signal

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 Review of Verilog assignment and
procedure

Thanasis Oikonomou 4 Verilog HDL Basics

 Continuous Assignments
review

• Continuously assigns right side of expression to left

side.
• Limited to basic Boolean and ? operators. For
example a 2:1 mux:
– ? operator
assign D = (A= =1) ? B : C; // if A then D = B else D = C;

– Boolean operators
assign D = (B & A) | (C & ~A); // if A then D = B else D = C;
 Procedural Assignments

• Executes a procedure allowing for more powerful

constructs such as if-then-else and case statement.
• For example 2:1 mux:
– if-else
if (A) D = B else D = C;
– case This is obviously much easier
case(A) to implement and read then
1'b1 : D = B; Boolean expressions!!
1'b0 : D = C;
endcase
 Always Block

• An always block is an example of a procedure.

• The procedure executes a set of assignments when
a defined set of inputs change.
 2:1 mux Always Block
Module mux_2_1(a, b, out, sel); Declare Module and IO as before.
input a, b, sel;
output out; All data types in always blocks must be
declared as a ‘reg’ type.
reg out; This is required even if the data type is for
always @ (a or b or sel) combinational logic.
begin
if (sel) out = a; The always block ‘executes’ whenever
else out = b;
signals named in the sensitivity list
change.
end
endmodule Literally: always execute at a or b or
sel.
Sensitivity list should include
wire out; conditional (sel) and right side (a, b)
assign out =(sel==1)?a:b; assignment variables.
 As Easier Way to Implement the
Sensitivity List
• Recent versions of Verilog provides a means to
implement the sensitivity list without explicitly
listing each potential variable.
• Instead of listing variables as in the previous
example
always @ (a or b or sel)
Simply use The * operator will automatically
identify all sensitive variables.
always @*
 Blocking vs Non-Blocking Assignments
• Blocking (=) and non-blocking (<=) assignments are provided to
control the execution order within an always block.

• Blocking assignments literally block the execution of the next

statement until the current statement is executed.
– Consequently, blocking assignments result in ordered
statement execution.
For example:

assume a = b = 0 initially;
a = 1; //executed first
b = a; //executed second
then a = 1, b = 1 after ordered execution
 Blocking vs Non-Blocking Cont

• Non-blocking assignments literally do not block the execution of the next

statements. The right side of all statements are determined first, then the left
sides are assigned together.
– Consequently, non-blocking assignments result in simultaneous or
parallel statement execution.

For example:

assume a = b = 0 initially;
a <= 1;
Execute together (in parallel)
b <= a;
then a = 1, b = 0 after parallel execution
Result is different from ordered exec!!! Does not preserve logic flow
 To Block or Not to Block ?

• Ordered execution mimics the inherent logic flow of

combinational logic.
• Hence blocking assignments generally work better for
combinational logic.
• For example:

x=a&b y=x|b

logic flow
 To Block or Not to Block ? cont
Module blocking(a,b,c,x,y);
input a,b,c; Blocking behavior a b c x y
output x,y;
reg x,y;
Initial values 1 1 0 1 1
always @* a changesàalways block execs 0 1 0 1 1
begin
x = a & b; x = a & b; //make assignment 0 1 0 0 1
y = x | c; y = x | c; //make assignment 0 1 0 0 0
end
endmodule
Non-blocking behavior a b c x y
Module nonblocking(a,b,c,x,y); Initial values 1 1 0 1 1
input a,b,c;
output x,y; a changesàalways block execs 0 1 0 1 1
reg x,y;
x = a & b; 0 1 0 1 1
always @*
begin y = x | c; //x not passed from here 0 1 0 1 1
x <= a & b;
make x, y assignments 0 1 0 0 1
y <= x | c;
end
endmodule non-blocking behavior does not preserve
logic flow!!
 Synchronous sequential circuit

State register: a collection of D FFs controlled by the same clock

signal
Next-state logic: combinational logic that uses the external input and
internal state (i.e., the output of register) to determine the new value
of the register
Output logic: combinational logic that generates the output signal

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Design of synchronous counter

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 Design of synchronous counter
• Sample code
module Counter
#(parameter N= 8)
( input wire clk, reset,
output wire [N-1:0] q );
// signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
// body, register
always @(posedge clk, posedge reset)
if (reset)
r_reg <= 0;
else
r_reg<=r_next; // <= is non-blocking statement
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg;
endmodule
Thanasis Oikonomou 16 Verilog HDL Basics
 Up/ down counter
• Design 8-bit synchronous up/down counter

17 Verilog HDL Basics

 8-bit up/down counter
module CounterUD
( input wire clk,reset,ud,
output wire [7:0] q );
// signal declaration
reg [7:0] r_reg;
wire [7:0] r_next;
// body, register
always @(posedge clk, posedge reset)
if (reset)
r_reg<=0;
else
r_reg<=r_next;
// next state logic
assign r_next = (ud==1)?r_reg + 1:r_reg - 1;
// output logic
assign q=r_reg;
endmodule

18 Verilog HDL Basics

 Register
• A register is a collection of D FFs that are controlled
by the same clock and reset signals
• Serial In – Serial Out (SISO) shift register. The block
diagram of 4-bit SISO shift register is shown in the
following figure.

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 Register
• Sample code
module Shift_SISO

#(parameter N= 4) // 500,000,000 for 0.1Hz

( input wire clk,reset,s_in,
output wire s_out
);
// signal declaration

reg [N-1:0] r_reg;

wire [N-1:0] r_next;
// body, register
always @(posedge clk, posedge reset)
r_reg<=r_next;
// next state logic
assign r_next = {s_in,r_reg[N-1: 1]};
// output logic
assign s_out= r_reg[0];
endmodule
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Serial input – parallel output shift register

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 Register
• Sample code
module Shift_SIPO
(
input wire clk,s_in,
output wire [7:0] q_out );
// signal declaration
reg [7:0] r_reg;
wire [7:0] r_next;
// body, register
always@(negedge clk)
r_reg<=r_next;
// next state logic
assign r_next = {s_in,r_reg[7:1]};
// output logic
assign q_out= r_reg;

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Serial input – parallel output shift register

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24 Verilog HDL Basics
 Synchronous sequential circuit
Finite state machine (FSM)

• Synchronous sequential circuits are realized using combinational logic and

one or more flip-flops.
• The circuit has a set of primary inputs, W , and produces a set of outputs, Z.
The stored values in the flip-flops are referred to as the state, Q, of the circuit
• Under control of the clock signal, the flip-flops change their state as
determined by the combinational logic that feeds the inputs of these flip-
flops. the circuit moves from one state to another
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 Moore and Mealy type of FSM

• Mealy type: The outputs are a function of the present state of the
flip-flops and of the primary inputs
• Moore type: The outputs always depend on the present state,
they do not necessarily have to depend directly on the primary
inputs
• that sequential circuits whose outputs depend only on the state of
the circuit are of Moore type, while those whose outputs depend
on both the state and the primary inputs are of Mealy type
• Sequential circuits are also called
26 finite state machines (FSMs)
 State Machine
• The first step in designing a finite state machine is
to determine how many states are needed and
which transitions are possible from one state to
another

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 State Machine
module simple (Clock, Resetn, w, z);
input Clock, Resetn, w; output z;
reg [2:1] y, Y;
parameter [2:1] A = 2’b00, B = 2’b01, C = 2’b10;
// Define the next state combinational circuit
always @(w, y)
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2’bxx;
endcase
// Define the sequential block
always @(negedge Resetn, posedge Clock)
if (Resetn == 0) y < = A;
else y < = Y;
// Define output
assign z = (y == C); 28
Endmodule
FSM

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 FSM
module fsm-eg-mult-seg SO: if(a)
( if(b)
input wire clk , reset , state_next=S2;
input wire a , b , else
output wire yo, y l ); state_next=Sl;
//symbolic state declaration else
localparam [1:0] S0 = 2’b00; S1 = 2'b01 , state_next=S0;
S2=2'b10; Sl: if(a)
// signal declaration state_next=S0;
reg [1 : 0] state_reg,state_next ; else
// state register state_next=S1;
always @ (posedge clk ,posedge reset) S2: state_next=S0;
i f (reset) default: state_next=S0;
state_reg<=S0; endcase
else //Moore outputlogic
state_reg<=state_next; assign yl=(state_reg==S0)||(state_reg==Sl);
//next_state logic //Mealy outputlogic
always @* assign y0=(state_reg==SO)&a&b;
case (state_reg) endmodule

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Design of Counter Using Sequential Circuit

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Design of Counter Using Sequential Circuit

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Design of Counter Using Sequential Circuit
• Sample code

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 Homework #1
• Design the up/down counter. The input clock is
50Mhz. The circuit count up or down, with the
frequency is selected by two switches (f,2*f,4*f,8*f,
where f is less than fclk). The block diagram is shown
as follows
CLR

CK_50M f<0> q<0>

CK_50M
f<1>

f<2>
q<7>
f<3>

S0

S1

U_D
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