Chapter 4: Design Proposal of 16-bit Pipelined ADC with

Novel Background Calibration Technique

Proposed Architecture of Pipelined ADC

Here a 16-bit Pipelined ADC is proposed based on SHA-less and multi-bit front-end as

shown in Figure 4.1. Total number of stages used here are 8. Initial two stages are 3.5 bit

stages, next stages i.e stage 3 to stage 7 are 2.5 bit stages as flash ADC of 3 bit comes at

last stage. This proposed Pipelined ADC is capable to attain high speed and resolution,

less area with less consumption of power. To make this architecture error-free, a digital

circuit (little complex) was utilized. This architecture is capable to remove errors like

op-amp gain, offset error and capacitor mismatching error. The advantage of structures

like multi-bit first stage could be used sometimes without calibration for some

applications where accuracy is not a prime requirement because these structures are

themselves capable to remove some errors. To make the overall structure simple, only

initial stages are higher in resolution and other stages are of lower resolution which

means less complexity. The stages in pipeline are scaled down to remove the problem

of higher bias currents and somewhat of capacitor mismatching also. Overall area

utilization is less as maximum stages are of low resolution.

Different units of this Pipelined ADC are: pseudo random sequence generator, a

reference generator, bit truncation or correction block, bit alignment logic and digital

calibration block and another important unit as clock generator. Because two different

voltages are used for the whole circuit and to avoid interference between stages with high

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power supply rejection ratio (PSRR) and low temperature coefficient voltage reference

generator is used here. At high input sampling frequencies, a clock generator is used for

low jitter clocks [61-63]. To make ADC free from the residue amplifier’s linear gain

errors and capacitor mismatching errors, novel digital background calibration technique

is applied for the ADC. In this technique, the advantage of signal dependent dithering

technique is taken with the butterfly shuffler DAC.

Figure 4.1: Proposed 16-bit pipelined ADC

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For Signal Dependent Dithering calibration technique two control signals of pseudo

random noise sequences, which are PN1 [1:5] & PN2 [1:5] are taken here. After digital

bit alignment and truncation method, the final 16-bit digital output could be achieved.

Front-End Concerns

Here, the main idea was to design this Pipelined ADC error-free and to achieve high

dynamic performance with less power consumption and less area utilization. The large

sampling capacitor is always required to achieve high performance with high resolution

at high sampling frequency but that is a cause of capacitor mismatching errors and op-

amp offset and gain errors which make hard drivability of ADC. One option is to use

input buffer to improve drivability by using BiCMOS process technology but that is not

feasible always. In CMOS technology, by removing on-chip input buffer from the

switched-capacitor, the problem could be solved which has created by a large Cs. Efforts

has been put to minimize Cs in this design also.

Instead of increasing the sampling capacitor value, reducing the noise-contributing

stages and blocks is the best way to achieve a high SNDR and SFDR. In a conventional

Pipelined ADCs, the prime source of noise and distortion is the front-end SHA [64-65].

Apart from the noise problem, the SHA is a power consumption device as well. So, if

possible in the design, removes SHA and save the total power and minimize the noise

contribution. In addition to above said advantages of removal of SHA, all stages are

taking the benefit of smaller sampling capacitor, those could save the power further and

make the ADC easily drivable. Because a small value of Cs allows smaller switches to

use for its operation within a particular bandwidth; that’s another advantage of SHA

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removal. Smaller switches can also help to improve the linearity of the front-end by

minimizing the total non-linear parasitic in the input sampling network. In this design,

apart from the SHA-less frontend, the multi-bit stages are used which saves a significant

power additionally. This kind of design is good for the noise-limited Pipelined ADCs

where high-SNR is required [66-67].

In multi-bit stage, after adding each new bit in each stage, the gain (G) rises by a factor

of 2 and on the other side, the feedback factor reduces by factor of 2. The effective trans-

conductance is assumed ‘gm’ for a single stage amplifier and the same results could be

applicable to two stage amplifier also. The calculation of bandwidth (BW) of a single

stage amplifier could be

gm
BW=β 𝐶𝐿 4.1

The feedback factor β would be halved by adding each bit in stage-1 and to keep the

bandwidth constant and the load capacitor, CL must be halved without any change in

power dissipation. The effective value of CL would be the sum of all capacitors like

stage-1 feedback Cf, Cs2 the sampling capacitance at stage-2 and the parasitic

capacitances. In the case when the CL is dominated by Cs2, CL could be split fifty-fifty by

splitting Cs2 in two halves to keep the bandwidth constant.

Stage-2 generates the total noise sampled by two major noise contributing elements. The

one of the two sources of noise is: in the stage-2 the noise generated by the switches and

the passive sampling circuit and the second source of noise is the amplifier of stage-1

when comes in the hold phase. Now, in the ADC, the noise factor referred to the input

(RTI) is represented by

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 𝐾𝑇
σ2_SWT α√ 𝐶𝐿 /G. 4.2

From equation 4.2, by making CL as half, the value of σ2_SWT would reduce by √2.

But there would be no change in the value of the track mode noise sampled by stage-

1(σ1) and (σ2_AMP1) and these values would be same as first order when RTI specified

by (4.1) and (4.2) [68]. Equation 4.3 is the representation of the summing node parasitic

capacitance of stage-1.

KT(Cs+Cf+Cp) 𝐾𝑇
σ1 α √ =√𝛽𝐺𝐶𝐿 4.3
𝐶𝑠2

𝐾𝑇
σ2_AMP1 α√𝛽𝐶𝐿/G. 4.4

It can be concluded from equation 4.4, by adding each additional quantized bit in stage

1, without making any increase in total power, the noise generated from the switches of

passive sampling circuit at stage-2 would be decreased by √2. Within the specified noise

budget, noise reduction could be done with smaller capacitance and lower power to some

extend only due to the limitation of reduction of the value of CL limited by parasitic

capacitance. On the other side, by increasing the number of quantization bits, the area

usage and the power dissipation will also increase exponentially.

Keeping all these factors in mind and to minimize the power, to remove errors and to

maximize static and dynamic performance, stage 1 and stage 2 has been decided as 3.5

bit with SHA-less front-end. The designed ADC has substantial advantages with

complex design circuitry and hard to work well at high frequencies beyond 300 MHz.

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 Proposal of 16-bit ADC Architecture and
Implementation

Here a 16-bit Pipelined ADC architecture is proposed. Refer to Figure. 4.1, the initial

two stages are 3.5 bit stages, next five stages i.e stage third to seventh are used 2.5 bit

stages and the final stage of the 16-bit Pipelined ADC is 3-bit flash ADC. Due to the

absence of SHA, the MDAC and the flash in stage-1 should sample the input signal at

the same time. Because stage-1 quantizes 4-bits, the value of the gain amplifier of the

MDAC would be 8, and one extra redundant bit is used to avoid the comparator offset

[69]. This Analog to Digital Converter includes digital background calibration technique

to remove the capacitor mismatching error in stage-1 [70]. While working with high

sampling frequency signals, a differential low-jitter clock receiver makes sure to raise

the value of SNR. A stable differential voltage could be achieved by a fast-settling push-

pull reference buffer [71].

4.3.1 Stage-1 MDAC

Figure 4.2, 4.3, 4.4 shows different types of Multiplying Digital to Analog Converter

circuits for a 4-bit pipeline stage. Here all three MDACs will discuss and find out the

appropriate one for our design because the MDAC used in the first stage of a SHA-less

design Pipelined ADC is most important and is the most complicated part of ADC. With

reference to Figure 4.2 [68], for the duration of the hold phase φ2, Cs is used for DAC

operation and Cs samples the input signal Vin during the track phase φ1. Depending on

flash data, Cs is connected to either REFB or REFT during φ2. The flash data is nothing

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 but only the representation of the sample in a quantized form which is currently used,

and during φ2 Cs has charged to a quantized value of the sample. And after that Cs

connects back to the input in the next track phase φ1, and helps the circuit to drive the

ADC inputs with charge.

Figure 4.2 : 4-bit MDAC implementations for DAC operation with reusing of Cs during
hold phase

Figure 4.3 : 4-bit MDAC implementations for DAC operation with separate and Cs and
CDAC during hold phase

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 Figure 4.4 : Nonlinear charge removing MDAC

Figure 4.2 depicts the charge which is directly related to quantized value of the last

sample is denoted by QQ_prev. The linearity of the ADC would significantly degraded if

the circuit which drives the ADC inputs could not effectively settle down to the nonlinear

kickback, that’s because quantization is a non-linear process. Mathematically, the

representation of the sampled signal be in the form of the following equation

Vsampled(n)= VIN(nT)+αQ(Vsampled(n-1)) 4.5

Here Vsampled(n) represents the nth sample, Q(Vsampled(n-1)) represents the

quantization function and Vsampled(n-1) signifies the 4-bit quantized value of the

previous sample. Here T is the clock period, α denotes the presence of the nonlinear

charge kickback to the input while taking the nth sample and its value lies in between -1

and +1.

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 |Sampling mismatch + Flash offsets|< VREF/2 4 4.6

The value of α has been determined by the circuit driving capability to settle down the

nonlinear kick back and the circuit driving capabilities of ADC inputs further depends

on the sample rate, the value of Cs and the effective impedance which includes bond-

wire and board trace parasitic. Without using the on-chip circuit e.g SHA-less stage-1,

to achieve low noise and to prevent nonlinear kickback and to settle effectively within

the accessible track time, comparatively large value of Cs is needed here. So, this MDAC

implementation is not useful for stage-1 MDAC shown in Figure 4.2.

Another SHA-less for stage-1 MDAC circuit is represented in Figure 4.3 which is using

separate sampling and capacitors of DAC [69-71]. Here, during the interval of φ1, Cs

samples and during the interval of φ2, Cs goes to reset and CDAC completes the DAC

operation. So, during the interval when Cs samples, there will be no kick back to the

ADC inputs with nonlinear charge but with a degradation factor of 2 in β in comparison

to MDAC implementation shown in Figure 4.2. Also, from equation (4.1),(4.3)and(4.4)

the capacitances should be double which makes the ADC difficult to drive and so ‘gm’

should be quadruple which significantly increases power, for the given target noise and

band width. So, the implementation of MDAC shown in Figure 4.3 is not favourable for

MDAC stage-1.

Another MDAC implementation shown in Figure 4.4 is similar to Figure 4.2 in addition

to a clearing switch and a short pulse (φCLEAR) who is driving that switch, used to solve

the nonlinear charge kickback problem [72-74]. Here, in the interval of φ1, Cs samples

Vin and in the interval of φ2, CS is connecting to REFB or REFT depending on flash data.

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 A short clearing pulse φCLEAR is able to discharge the nonlinear charge QQ_PREV

completely before Cs is connected back to Vin. This MDAC implementation is able to

achieve high SNR, low power and small Cs in this design.

4.3.2 Stage-1 Design

Stage-1 consists of a MDAC and a flash as shown in Figure 4.5. Quantizing high

frequency inputs without a SHA circuit on front-end and to reduce the mismatch error of

the signal sampled by the flash and the MDAC a “sampling flash architecture” is

preferred here [69]. In the interval of track phase (φ1), the two capacitors, flash and

sampling CS_FL and Cs are concurrently sample Vin, and to sample the reference ladder

taps, a different capacitor set is used in the flash (CREF_FL). Switches of linear

bootstrapped are considered here to make sure the input signal and to reduce sampling

distortion [70-71]. In the starting of φ2, CREF_FL and CS_FL are connected together to give

an indication of the signal to be amplify and to generate a valid flash data after a short

interval at the input of the pre-amplifier and to latch after a short interval to generate a

valid flash data. The flash data is used to generate the residue amplifier’s output driven

by the MDAC reference switches. The availability of time for MDAC settling is the

challenge in this implementation, which is reduced during φ2 by the latch and the pre-

amplifier. So, the flash comparator and the residue amplifier should be fast enough for

SHA-less front-end at the cost of more power dissipation. SHA-less architecture is

playing a role of power saver by eliminating the SHA and SHA-less could be a power

consumer on the other side due to increased power in the flash comparator and the residue

amplifier. Up to medium sampling rates ADCs, the SHA-less architectures are good to

save power due to the feasibility of fast and low power comparators. For high sampling

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rate ADCs, MDAC settling time is too high, so flash comparators use a huge portion of

power compared to MDAC using a SHA where the comparators could be latched earlier

so useful to save power.

Figure 4.5: Switched-capacitor implementation

For this particular SHA less architecture, 125 MS/s, a significant power saving with some

design modifications. Because CS and CS_FL concurrently sample Vin, the available

correction range could be consumed by the value difference of flash sample value and

the MDAC sample value might be a major problem of SHA-less front–end. At higher

input frequencies, the difference would be high between the timing and bandwidth of the

flash and MDAC sampling networks. At very high input frequencies, ADC could have

missing codes due to sampling mismatch if stage-1 goes out of correction range. Here,

special attention is required to increase the tolerance of mismatch without going out of

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correction range and to minimize the sampling mismatch between the MDAC circuit and

the flash circuit while sampling inputs up to 300 MHz . In the flash comparators, offset

cancellation could be realized to minimize their offsets and to maximize the tolerance of

sampling mismatch because they are more susceptible to large offsets. Because separate

reference capacitors and sampling capacitors (i.e. CREF_FL and CS_FL) are used in this

“sampling flash architecture” so, before pre-amplification there is a capacitive reduction

of 2 on the sampled by doubling the flash offset RTI. The easiness can be increased

related to sampling mismatch by increasing the quantizing bits to 3 in stage-1, so the

available correction range would also be double to ± 125 mV RTI. The design would be

easy because the comparators are not needed for offset cancellation and matching

requirement is also relaxed between the flash and MDAC sampling networks. But there

is significantly raise in power consumption of ADC along with the high value of SNR

comparative to the 4-bit stage-1. For the matching of MDAC and flash sampling

networks and for the comparator offset cancellation the power increases less in

comparison to the increased layout effort and the cost of extra design. So, there is always

a compromise between power consumption and complex design circuit. The difference

between the sampled values appears due to bandwidth mismatching between the two

sampling networks and due to the difference in timing skew between the flash and

MDAC sampling clocks φ1P. The same buffered clock control can be used to drive both

sampling switches just to reduce the timing skew. The matching of the two networks

with their bandwidths is a hard problem due to (1) the flash network involves two

capacitors CS_FL and CREF_FL of equal values but the MDAC network has one large CS

and one small Cf (2) the value of Cs is much larger than CS_FL and (3) the input parasitic

80
 capacitance of RA is much higher than the input parasitic capacitance of the pre-

amplifier. By using post-layout extracted simulations, the bandwidths of the two

networks could be matched as closely as possible under the above said fundamental

differences.

4.3.3 Flash Comparator for Stage-1

The flash comparator given in [71] is comparable to satge-1 flash comparator described

here with some changes. The cross-coupled PMOS pairs has been removed in present

design to take the benefit of smaller regeneration time. In the comparator represented in

Figure 4.6, to make up a pre-amplifier, PMOS are used as loads. A diode is coupled to a

latch and to PMOS loads. In the starting of Ф2 phase, the preamplifier is ready to amplify

and to strengthen the input signal of different nodes to its highest to voltage levels.

Figure 4.6: Flash comparator for Stage 1.

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4.3.4 The Residue Amplifier

As shown in Figure 4.7, a Two-stage Miller-compensated design is used here as a residue

amplifier which is capable to give large swing, high gain and excellent linearity [72]. For

the first stage, along with the PMOS inputs telescopic structure is perfect and the second

stage is made up with PMOS loads of NMOS differential pair amplifier. NMOS inputs

are not used for residue amplifier stage-1 because a large gm per unit current is needed.

If NMOS devices would use instead of PMOS devices in CMOS integration technology,

a greater value of 1/f noise achieved. By growing the Miller capacitor, the issue of low

frequency behavior of 1/f noise could be solved because it is capable to filter the noise

directly. Hence a large Miller capacitor has been preferred here. To reduce 1/f noise

further, an auto-zeroing amplifier could be used by paying the cost of increased power

consumption and increased design circuitry. So for stage-1, to achieve the lowest power

solution and to get lower 1/f noise PMOS inputs are preferable than NMOS inputs.

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 Figure 4.7: Residue Amplifier circuit for Stage-1

4.3.5 Voltage references

The Voltage reference structure is used to provide stable and suitable voltage supply to

every stage of Pipelined ADC [73]. To make sure the final digital output received is

error-free, the kind of voltage referencing arrangement is used where digital calibration

has performed in first two stages. The calibrated output would be passed to backend

stages only. In the beginning of hold phase, the sampling capacitor changes its current

value by charging or discharging to the reference voltages of sub_DAC’s depending

upon outputs of sub_ADC. There may be a requirement of a large current by first stage

capacitors if just one reference voltage was used which allows the changed output of

other stages helps for slow settling. At the starting of hold phase, small current supplies

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 due to sampling capacitors. By using separate voltages, the final outputs could be

achieved properly and error-free. So by using different voltage references, the optimum

current consumption could be achieved and could save the power as well.

Dithering Calibration Technique

Here different types of dithering techniques are going to be discussed along with their

pros and cons.

4.4.1 Types of PN Dithering

There are two major constraints of the calibration using PN dithering or modelling. One

out of two is the dither magnitude and the other one is the measurement time. There must

be a compromise between the signal range and the dither magnitude [74-76]. With a large

value of PN-modulated dither is represented in Figure 4.8(a) where the full scale range

varies in between –1 to 1. The flexibility with the total signal plus dither signal is to fit

within the full-scale voltage range. But the effective number of bit (ENOB) could be

reduced after that. If the thermal noise is dominating on signal-noise ratio, then this kind

of reduction technique of signal range is not recommended. Just to suppress this noise

(kT/C) by 3 dB, SC circuits will require capacitors of double in size which results in

increased area and power consumption. Because even a small value dither can make a

huge change in signal range, so to achieve the same accuracy it requires much longer

time for that due to the large ratio of VIN/VCAL as shown in Figure 4.8(b). There is a

compromise between the averaging time and the measurement accuracy for the

measurement time limit. If both VIN/VCAL and VREF are set to 1, then after averaging

220 samples, the measurement error is shown in Figure 4.9(a). For a 2 Vpp sine wave

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 input, the simulation has been repeated 1000 times. In the output, histogram, the

percentage of the measurement error is 99%, means an accuracy of 10 b.

Figure 4.8: (a) PN dithering with Large Magnitude. (b) PN dithering with Small Dither
Magnitude.

Figure 4.9: (a) after taking average of samples the histogram of the measurement error (b)
Graph between the number of samples averaged and Measurement accuracy.

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 The relation of measurement accuracy w.r.t numbers of samples averaged demonstrated

in Figure 4.9(b). It should be noted that if someone wants to achieve an added bit of

accuracy then number of samples averaged should be increased by four times. The fact

is by treating the PN-modulated VIN/VCAL as a white noise due to doubling the number

of averaging samples, the SD of a white noise is decreased by a factor that is square root

of 2. The result depicted in Figure 4.9(b) indicates that for the 15-b accuracy and if the

ADC is working at sampling rate of 20 MS/s, 230 samples should be averaged for one

measurement by taking nearly one minute to complete. So, getting an answer that pleases

both conditions is really difficult. So, go for other solution as explained in next section.

4.4.2 Signal-Dependent Dithering

The problems discussed in the last section of PN dithering, the dither magnitude

limitation and the measurement time could be solved by signal-dependent dithering

scheme. To minimize signal-to-dither ratio, the signal-dependent dithering is used where

dithers of different magnitudes, technically selected by the strength of signal level. Dither

signal is injected by dividing the unit capacitor into two of each pipeline stage and by

adding two comparators. Using this background calibration method, finite op-amp gain,

capacitor mismatching error, gain errors could be removed just in one step without

changing the values of analog components and with removal of digital dividers or

multipliers. Depending upon the value of signal level, the dither magnitude has been

selected for that. As shown in Figure 4.10(a), three different sub-ranges are made and to

set PN value in the middle range, a dither of +2/3 or -2/3 is inserted. When PN = −1and

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 the signal is more than +1/3, a dither of −4/3 is inserted and no dither is inserted when

the value of PN is ’1’. The dithers of +4/3 is inserted when the value of PN is ‘1’ and

signal is below −1/3, and no dither is injected if PN =-1.

Figure 4.10: (a) SDD with three different subranges (b) PN dithering with no change in
magnitude

Overall, compare to a large value of 2/3 in fixed-magnitude dither technique, the signal

plus dither results into a smaller signal of between ±1/3 is represented in Figure 4.10(b)

which shows that with small ratio of VIN/VCAL, higher measurement accuracy could

be achieved as compared to fixed magnitude dither technique. The SDD, signal

dependent dithering scheme is efficient to achieve the higher level of measurement

accuracy and to reduce the measurement time. By allocating more sub-ranges to the

signal is another way to reduce signal-to-dither ratio VIN/VCAL further. In the signal

dependent dithering, on the output side, the PN associated component will not change its

value even though different magnitude dithers are added. To match with fixed-magnitude

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PN dithering and to generate the difference of the outputs for these cases of PN = 1 and

−1, same hardware is used here. Irrespective to comparator offsets and to maintain the

signal within full-scale range, the dither magnitudes and the comparator thresholds

should be set properly. The fixed-magnitude dithering is a compromise between large

magnitude and small magnitude dithering while the signal-dependent dithering is

advantageous as more apparent by Figure 4.10(a). Because the dither injection of ¼, can

reduce the signal range to ¾ and the ENOB could be better by about 0.5-b. Also, as the

ratio of VIN/VCAL decreases from 3 to 1/2 which could help to improve the accuracy

by 2.5 bits. So, by applying the signal dependent dithering scheme, 3 more bits of

accuracy can be achieved and the measurement time could be shortened by 1/43. In this

process, one measurement cycle could be reduced to one second. Now, to generate two

different residues the sub-ADC and the sub-DAC are capable enough. To calibrate an

ADC of high resolution, a low signal to dither ratio is beneficial to improve ENOB and

accuracy. Like calibrating a multi-bit first stage Pipelined ADC requires less accuracy

comparatively as required by the first stage of 1.5-bit. Multi-bit first stage ADCs are

more capable to relax the calibration accuracy requirement but at the cost of complex

calibration algorithm [77].

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4.4.3 Signal-Dependent Dithering for MDAC

Figure 4.11: Modified residue for SDD.

In Figure 4.11, the MDAC modified residue plot for signal-dependent dithering is shown

where the sub-ADC shifts thresholds of comparators is from ±1/4 VREF to ±3/8 VREF.

Because the Signal-dependent dithers are injected in the range of ±3/8 VREF, there is

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requirement of two more comparators with new threshold voltages of ±1/8 VREF. The

selection of dither magnitude depends on the signal levels and the PN values. One of

these values of dither magnitude has been selected − VREF, −1/2 VREF, 0, +1/2 VREF or +

VREF as shown in Figure 4.11. For a small signal of ±1/4 VREF range, a large dither of 1/2

VREF inserted in case of fixed magnitude and the signal plus dither comes in range of

±3/8 VREF as represented in Figure 4.12. VIN/VCAL, the ratio of signal to dither has

come down to 1/2. If the input stays within ±3/8 VREF and by doing the average of the

output samples, 99% of the measurement errors corrected. In Figure 4.12, the modified

standard MDAC is shown for signal dependent dithering where the capacitor has been

split into two and two more comparators are added [78].

Here, the dithers are injected by the values coming out from the switches which works

by the comparator outputs and PN values. if PN is 1 and the signal range in between −3/8

to −1/8 VREF , the capacitor C1 & C2 switches in between − VREF and 0 and if PN is -1

and the signal ranges from +1/8 to +3/8 , the capacitor C1 and C2 switches between 0

and +VREF. The capacitors C1 and C2 are in turn changed to +VREF when PN is logic’

−1’ and changed to − VREF when PN is logic ‘1’ and when the signal comes in the central

range insert a dither of 1/2 VREF. The two split capacitors could be mismatched which

will contribute to noise after randomized and later on it could spread over the Nyquist

band also. This noise is not required to subtract digitally in this design because its level

is lower than the system’s noise level.

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Figure 4.12: Equivalent fixed-magnitude PN dithering of modified MDAC stage.

The following are the features of MDAC shown in Figure 4.13:

(a) Because the low signal-to-dither ratio, VIN/VCAL, the signal de-correlation time will

get shorten.

(b) Number of comparators will increase in each stage of Pipelined ADC.

(c) Number of capacitors with dithering remains same as before and also the analog

performance.

(d) No change in op-amp settling with Switch control logic

(e) Without compromising with the signal range, large dithers could be used.

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 Figure 4.13: Signal-dependent dithering with MDAC residue amplifier.

When the signal is high, no dither is inserted and a problem of different calibration time

for different signal condition may arise in this dithering scheme. With added number of

comparators for the dithering with the full scale range is shown in Figure 4.14. Assume

PN = −1 and the signal is higher than +5/8 VREF, the residue voltage will be 2VIN −2

VREF due to an additional capacitor or a reference voltage of 2 VREF. Only initial stages

require dithering, most of the time the first stage only because that is more sensitive to

input noise and signal changes. All the other stages are dependent on the output generated

from the previous stages only. Although by applying signal-dependent dithering,

measurement time is shorter and the circuit complexity is also low but the problem comes

when the signal remains high for longer time. Because all output samples are averaged,

so the signal-to-dither ratio remains high. Another approach of Pipelined ADC

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 architecture with two channel could be used to remove the PN un-correlated i/p signal

which can create the problem of mismatching between the two channels.

Figure 4.14: Modifications in residue voltage of the MDAC stage restored to full dithering
range.

Sampling Clock Skew in SHA-less Pipelined ADC

By removing the dedicated front-end SHA reduces noise contribution and also helps to

reduce power in the Pipelined ADC. So the other stages of ADC can use smaller

capacitors within the specified noise budget to further save power. Elimination of SHA

helps ADC to drive easily because the first stage uses smaller sampling capacitor.

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Because the smaller switches are used with less non-linear parasitic in the input network,

linearity of the sampling circuit has been improved. In addition to that if initial stages

considered multi-bit, it would be capable to save power further for the high speed and

high resolution Pipelined ADCs, but be ready to handle the increased circuit complexity.

So, the finest balance between power dissipation, component matching and design

complexity could be done by the proposed SHA-less, multi-bit Pipelined ADC [79-80].

But in a SHA-less pipeline architecture the S/H and the sub-ADC in the first stage have

to sample dynamic input signal simultaneously without a held signal. So, there are more

chances for the same event, S/H and sub_ADC take different sampled values if there is

bandwidth mismatch between their input networks or/and if there is a sampling clock

skew, as is shown in Figure 4.15. For higher bit stage i.e first stage with digital error-

correction, this mismatch error could be corrected.

Figure 4.15: In the first stage, Sampling clock skew.

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4.5.1 Proposed Timing diagram for SHA-less:

Figure 4.16 shows the conventional schematic and timing diagram of single stage. All

through the sampling phase φ1, the i/p signal is connected to the bottom plates of

sampling capacitors when the first stage’s sampling switches are turned on. The switch

‘Sm’ has turned off at the falling edge of φ1e and then the input voltage will be sampled

on Cs. Comparators can start its function after a delay time of ∆tc and compare input

voltages and generate its output. The decoder comes in picture to play its role for the

reference switch ‘S’ and converts the digital outputs into control signals at the rising edge

of the amplifying phase φ2. All through the phase φ2, with the switch ‘Sr’, the reference

voltages are connected to the bottom plates of MDAC’s sampling capacitors while

turning on the feedback switch ‘Sf’. Once the control signals generated by the decoder

comes to stable, the residue voltage starts settling down.

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 Figure 4.16: A conventional schematic and timing diagram

Due to the decoder’s delay time of ∆t, the residue voltage would be unable to start settling

during this delay time because the bottom plates of MDAC’s sampling capacitors are not

in connection to any voltage. The decoder’s delay time uses residue voltage’s settling

time also. In the low speed Pipelined ADCs, only a small portion of the settling time

could be used whose effect is insignificant also.

For the low speed ADCs, like 50 MS/s, the half of a clock cycle required would be 10ns

and the available settling time is no longer than 9ns by considering ∆t as 200ps, which

is about 2% of the settling time. So no timing diagram consideration is required for low

speed Pipelined ADCs. But a relatively short clock cycle is in high speed ADCs. But for

96
a Pipelined ADC of sampling rate 400MS/s, the available settling time would be less

than 1.25ns and the time used for settling by a decoder cannot be neglected. So something

should be done to remove this problem. If the capacitor floats during interval ∆t, at the

output voltage, there would be an overshot. To pull the capacitor out from this overshot

would be worse when residue voltage starts settling. So, some changes are required in

the traditional timing diagrams to remove the disadvantages discussed above. Figure 4.17

presents the proposed circuit diagram and timing. Now triggering the decoder happens

at additional clock phase φ2d. It starts ∆t time early than that of φ2, and the switch S

with its control signals would be ready before the amplifying phase starts. In this way,

the residue voltage could start its settling instantly. It means, the delay time used by

decoder won’t come in the given settling time. Moreover, no overshot at the output will

appear and at the same time there is no scope for the sampling capacitor floating time.

The point to be noted down here is φ2d stays high before the falling edge of φ2, so during

the whole ranging sampling phase of the next stage, the residue voltage signal remains

stable. The first and third stages of the decoders are triggered by φ2d and φ1d is used to

trigger the second and fourth stages.

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 Figure 4.17: The new timing diagram

Proposed Calibration Technique

In traditional Pipelined ADC, to remove the sampling clock skew, a separate dedicated

front end SHA is generally used at the cost of distortion, noise and power consumption.

In the proposed ADC, the SHA is not a part of the architecture just to save the power and

noise. To improve the ADC performance by increasing the SFDR, SNR and SNDR

without increasing the sampling capacitors, multi-bit front stages are used. To nullify the

capacitor mismatching errors and nonlinear errors, high gain op-amps are used at each

stage of the Pipelined ADC. By using the proposed background digital calibration

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 technique, some of linear and non-linear errors including gain and mismatching errors

has corrected. The calibration technique which is proposed here is the arrangement of

signal depended dithering (SDD) calibration technique and a signal distributor butterfly

Shuffler. With the help of fifteen additional comparators from a1 to a15 for the first stage

of 3.5 bit MDAC stage, the residue voltage transfer function is improved now. This

improved transfer function shows that there are very less chances for the signal value to

go out of range as shown in Figure 4.18.

Figure 4.18: Residue plot for a 3.5 bit to determine the value of SDD.

4.6.1 Butterfly and SDD Calibration Technique

The dithering signal has been injected depending on the location of the residue voltage

(Vres) and on the current value of PN code. Depending upon the signal value on the

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residue plot, the circuit modifications and calibration algorithm applied for the 3.5 bit

MDAC stage as shown in Figure 4.19. The transfer function can be expressed as shown

in following equation if assume PN [2:5] =4’b0000

Ci C15
Vres= G. (Vin − ∑14
i=1 (Di. Vref Cs) − PNdither. Vref. ) 4. 7
Cs

Cs
and G = Cf+(Cs+Cf+Cp)/A

and Cs = ∑16
i=1 Ci.

The equivalent sampling capacitor is ‘Cs’ here, ‘Cp’ represents the comparable

input parasitic capacitor of op-amp, ‘Cf’ represents the feedback capacitor and G

represents the residue amplifier’s actual gain. When the pseudo random number PN

[2:5] comes to 4’b0000, indicates the insertion of the dithering signal to capacitor C15

and afterwards D1~ D14 would be the fourteen normal outputs of sub_ADC. If the PN

sequences PN [1] = {-1, 1} then the dither signal PNdither would be (PN [1] +loc_res)/2,

and loc_res can decide the location of output residue Vres. The residue transfer curve

could stay without any change or move down when the residue voltage Vres comes on

the higher half side of residue graph and loc_res= ’1’ can change the value to PNdither

= {0, 1} as shown in Figure 4.18. And when loc_res gets value ‘-1’ it could make

PNdither = {0, -1} that indicates the residue transfer curve can shift upwards or stay

without any change. Now how the errors are extracted and removed from the residue

signal is explained by following equations:

After multiplying equation (4.7) by 2,

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 Ci PN[1]+locres C15
Vres. (-2).PN [1] = -2G [ Vin − ∑14
i=1 (Di. Vref Cs) ( ).Vref. ]. PN[1]
2 Cs

𝐶15
= PN_modolate+G.Vref. as PN[1]2 =1 4.8
𝐶𝑠

Ci loc_res C15
Where PN_modolate = -2G [ Vin − ∑14
i=1 (Di. Vref Cs) − ( ) Vref. ] .PN[1].
2 Cs

PN_modulate could be considered as noise because loc_res is unrelated to PN [1] and

the noise could be removed using a low-pass filter, which should be able to average a

large number of samples and can ideally work as an accumulator. Represent the equation

(4.8) in a different way as the equation (4.9)

1
WG,15= N ∑N
i=1 −2 Vres(n). PN[1]|N → ∞

C15
= 𝐺. 𝑉𝑟𝑒𝑓. . 4.9
Cs

Because here the infinite samples have considered and those samples are averaged as

WG,15 so, it should include linear gain errors and capacitor mismatches errors both. The

four bit PN sequence PN [2:5] controls the insertion of dithering signal to all capacitors

Ci (i= 1 to 16). The process of injecting dithering is done by Butterfly Sampling

technique as shown in Figure 4.19 [81-82]. With the help of equation (6.8), different

values of WG (i=1 to 16) could be achieved. Table 4.1shows that how different values

of WG (i=1 to 16) saves in different registers as per their order and value. How the

butterfly shuffler is able to store different values in their respective registers is

demonstrated in Figure 4.20. Because the initial stages are more prone to noise as
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compare to backend stages so calibration is applied to initial stages and backend stages

are assumed ideal. After calibrating initial stages, the final digital output is assumed as

linear which is equal to G.Vin/4.

Figure 4.19: Modifications in circuit done with 3.5 bit Stage.

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Table 4.1: By using butterfly shuffler different values WG (i=1 to 16) are saving to
different registers.

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Figure 4.20: working of Butterfly shuffler for 3.5 bit stage.

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 Measurements

As mentioned above due to high resolution, high speed requirement with limited

manufacturing accuracy availability, the actual results may be different from the

expected/ideal results which introduces an error on transfer function. There are some

metrics to measure ADC’s static and dynamic performance.

For achieving large output swing and high gain and for the proposed 16-bit Pipelined

ADC, a 2 stage Miller compensated Op-amp is used here. As per design requirements,

the first stage of Op-amp can achieve desire results i.e a large gm and high gain by using

a telescopic structure using NMOS inputs with gain boosting logic. The loop gains of

first two stages may be slightly different to each other due to different design margins

and process variations.

4.7.1 Dynamic Performance Parameters:

As there is an increase in frequency, there would be an increase in parasitic capacitance

and at the same time decrease in gain also. At the sampling frequency of 125 MS per

second, the response of SNDR and SFDR of the ADC while the frequency ranges for

input varies in between 30 MHz to 150 MHz as shown in Figure 4.21. The proposed

ADC but without any calibration logic and by applying the FFT at sampling rate of 125

MS/s on that, the SFDR found as 80 dB and the value of SNDR found as 70.28 dB as

shown in Figure 4.22. Different frequencies of input signal ranges from 30 MHZ to 150

MHZ are used to test ADC’s dynamic performance with background digital calibration

technique, which results that below 150 MHZ of input signal, the SFDR and SNDR gives

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better results than high frequencies above 150 MHZ. After applying the FFT at 125

MS/s of sampling and 30 MHz full-scale input, the proposed Pipelined ADC is able to

accomplish interesting values of SNDR and SFDR and these values are 97.74 dB and

79.77 dB respectively as shown in Figure 4.23. And at sampling frequency of 125 MS/s

and 150 MHz full scale input by applying the FFT, the values of SNDR and SFDR are

shown in Figure 4.24. The proposed Pipelined ADC with background calibration

technique can achieve SNDR as 73.5 dB and SFDR of 88.9 dB. Because the jitter noise

caused by the clock generator could disturb the performance of ADC so the proposed

ADC has been tested after subtracting out the clock generator’s jitter. The approximation

of internal jitter of the current ADC is 70 fs. Due to low-jitter in the clock generation

circuit, there could be a slow drop SNDR at high frequencies which is a warning signal

to take care.

Figure 4.21: SFDR and SNDR plots w.r.t input signal frequency.

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 Figure 4.22: FFT plot before calibration.

Figure 4.23: At 125 MS/s, 30 MHz input for a calibrated ADC, the FFT plot

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Figure 4.24: At 125 MS/s, 150 MHz input for a calibrated ADC, the FFT plot.

4.7.2 Static Performance Parameters:

On an ADC’s transfer characteristic, the maximum deviation from the best fit line of the

transfer curve to the actual transition points is called Integral nonlinearity (INL). For this

measurement of INL, gain errors and offset errors have assumed set to zero. The

maximum absolute difference from the actual code widths and the ideal code width is

called Differential non-linearity (DNL). A perfect INL indicates a perfect DNL also. In

actual ADCs, when DNL comes within ± ½ LSB, means no missing code in final output.

Here with this proposed ADC with proposed calibration technique, the INL has improved

from 8.7/-8.8 (without calibration) to 0.5/-0.5 (with calibration). The DNL is also

changed from 0.33/-1 (without calibration) to 0.57/-0.48 (with calibration). Figure 4.25

and 4.26 shows the changes in INL and DNL after calibration.

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 Figure 4.25: DNL plot of uncalibrated ADC at 125 MS/s (above) and INL plot of
uncalibrated ADC at 125 MS/s (below).

Figure 4.26: DNL plot of calibrated ADC at 125 MS/s (above) and INL plot of calibrated
ADC at 125 MS/s (below).

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With this proposed ADC working at a 1.8 V supply, the total power consumption is 300

mW including the CMOS output drivers. With the sampling rate of 125 MS/s, the time

for calibration of stage 1 and 2 is around 40s.

Summary

A Pipelined ADC of 16-bit, SHA-less sampled at 125 MS/s having first two stages as

3.5 bit and other five stages of 2.5 bit/stage and a 3-bit flash ADC is used for last stage.

Final digital output of 16-bit has achieved after bit truncation and alignment. To relax

ADC from linear errors, a grouping of signal-dependent dithering and butterfly shuffler

calibration technique is applied in initial stages. To stop the kickback and setting the

voltage signal within available settling time voltage reference separation has been used

which improved the ADC’s performance also. At each stage, high gain op-amps has been

adopted in this proposed design to avoid nonlinear errors and capacitor mismatching.

The total power consumption for this proposed ADC is 300 mW. The improvement in

INL is from 8.7/-8.8 to 0.5/-0.5 after calibration and improvement in DNL is from 0.33/-

1 to 0.57/-0.48. The improvement in dynamic performance is also visible with proposed

calibration technique. While sampling with 30 MHz full scale input at 125 MS/s, SFDR

raised to 97.74 dB and SNDR raised to 79.77 dB and with sampling with 150 MHz full

scale input at 125 MS/s, SFDR raised to 88.9 dB dB and SNDR raised to 73.5 dB values.

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 A Comparison with other ADC Implementations

A comparison has been done with other published ADC designs in various papers, based

on their features, calibration techniques and performance results.

Parameter S. D.S Shylu R.Payne Van De Vel Y.Miyahara C.Yongzhe This work

Devarajan, “A 1.8V “A 16-Bit “A 1.2-V “A 14b 60 n “14-bit

“A 16-bit, 22mW 10 100 to 160 250-mW MS/s 100 MS/s

125 MS/s, bit 165 MS/s SiGe 14-b 100- Pipelined 121 mW

385 mW, MSPS BiCMOS MS/s ADC pipelined

78.7 dB Pipelined Pipelined Digitally Adaptively ADC” JS

SNR ADC for ADC With Calibrated Cancelling (IOPScien

CMOS Video 100 dB Pipeline Opamp Gain ce). 2015,

Pipeline Applicatio SFDR”. ADC in 90- and vol. 36,

ADC” ns” nm Nonlinearity”

CMOS”

Technology( 0.18 0.18 0.25 0.09 0.18 0.18 0.18

μm) BiCmos
Sampling 125 165 160 100 60 100 125

Rate(MS/s)
Resolution 16 10 16 14 14 14 16

Supply (V) 2 1.8 3.3/5 1.2 1.6 1.8 1.8

SFDR (dB) 87 64 102 90 84 82.7 97.74

SNDR (dB) 78.6 56.1 76.16 73 73.3 69.1 79.77

DNL (LSB) 0.5 0.41 1.6 0.9 0.5 0.65 0.5

INL (LSB) 1.5 0.6 4 1.3 0.6 3.86 0.57

Power (mW) 385 22 1600 250 67.8 121 300

Table 4.2: Comparison Table.

CMOS Pipeline ADC” IEEE JSSC 2009 vol. 44[85] is a SHA-less front-end, 16-bit 125

MS/s and is capable to realize high values of SNDR and SFDR, but the calibration

technique to make the ADC error-free is the foreground factory digital calibration, which

means calibration and conversion are at different times. In the ADC proposed by D.S

Shylu “A 1.8V 22mW 10 bit 165 MSPS Pipelined ADC for Video Applications” Wseas

Trans.CS. 2014, vol. 13 [86], is able to reduce power consumption by using amplifier

sharing technique and double sampling MDACs but for low resolution of 10 bits. Some

of applications are suitable for low resolutions and low values of SNDR and SFDR like

Video applications. So the ADC proposed here is better than others and capable to give

better static and dynamic performance with a resolution of 16-bit and a supply voltage

of 1.8V using CMOS process technology only. The ADC presented by R. Payne “A 16-

Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC with 100 dB SFDR”. IEEE JSSC

2010 vol. 45 [87] is a low distortion 16-bit Pipelined ADC which can work well at

sampling rate of 100MS/s to 160MS/s but with SiGe BiCMOS process technology only.

Due to Bi-CMOS process technology, this ADC consumes a large power and have a

complicated implementation. The paper “A 1.2-V 250-mW 14-b 100-MS/s Digitally

Calibrated Pipeline ADC in 90-nm CMOS” written by Van De Vel. IEEE JSSC 2009,

vol. 44 [88] is a 14-bit Pipelined ADC, implemented in Nano process technology of 90

nm. Because the values of INL and DNL are high, so limited applications for this.

Another problem of this ADC is that the digital post processing is taken care off-chip by

using a PC, means not completely integration on chip. The ADC presented by Y

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Miyahara “A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Op-amp Gain and

Nonlinearity”, IEEE JSSC 2013, vol. 49 [89] is using the calibration technique based on

an auxiliary error amp. and sign sign LMS adaption method. It has a limited scope due

to poor performance on high sampling frequencies. The ADC presented by C.Yongzhen

“14-bit 100 MS/s 121 mW pipelined ADC” JS (IOPScience). 2015, vol. 36 [90], is

working based on the stage reduction theory. For achieving a low power consumption,

two cascading MDACs are shared the same residual amplifiers. This ADC could achieve

the value of INL higher but value of SNDR decreased. A Pipelined ADC of Multi bit,

SHA-less has been designed during this research work. The effective way to avoid the

kickback and settling within the available settling time and to increase ADC performance

is the use of voltage reference separation method. For this design implementation to

avoid nonlinear errors and capacitor mismatching, high gain op-amps are preferred for

each stage. The arrangement of signal dependent dithering and a butterfly shuffler

distributor is used as digital back ground calibration to the initial two stages. The power

consumption with this proposed ADC is 300 mw. The improvement in DNL is from

0.33/-1 to 0.57/-0.48. The INL has achieved value 0.5/-0.5 after calibration which was

8.7/-8.8 before calibration. With sampling rate of 125 MS/s and a 30 MHz full scale

input, the value achieved by SFDR is 97.74 dB and 79.77 dB achieved by SNDR. With

sampling rate of 125 MS/s and a 200 MHz full scale input, the value achieved by SFDR

is 88.9 dB and 73.5 dB achieved by SNDR by using the proposed Pipelined ADC.

113