/ Tutorial 7

Thursday, 18 May, 2023 11:00 PM

1)Network Interface Card

2)-I/O technique
-Bus system

Bus system: A bus is a shared communication link

: It uses one set of wires to connect multiple subsystems

The need to support a range of devices with:

-Widely varying latencies
-Widely varying data transfer rates

3)
Programmed I/O - data are exchanged between the processor and the I/O
module. The processor executes a program that gives it direct control of the I/O
operation, including sensing device status, sending a read or write command, and
transferring the data. When the processor issues a command to the I/O module, it
must wait until the I/O operation is complete. If the processor is faster than the
I/O module, this is waste of processor time.

Interrupt-driven I/O - the processor issues an I/O command, continues to

execute other instructions, and is interrupted by the I/O module when the latter
has completed its work. With both programmed and interrupt I/O, the processor is
responsible for extracting data from main memory for output and storing data in
main memory for input.

Direct memory access (DMA) - the I/O module and main memory exchange data
directly, without processor involvement.

4)
When the processor, main memory, and I/O share a common bus, two modes of
addressing are possible: memory mapped and isolated I/O.

Memory-mapped I/O:
• There is a single address space for memory locations and I/O devices.
• The processor treats the status and data registers of I/O modules as
memory locations and uses the same machine instructions to access both
memory and I/O devices.
• For example, with 10 address lines, a combined total of 210 = 1024
memory locations and I/O addresses can be supported, in any
combination.
• An advantage of memory-mapped I/O is that this large repertoire of
instructions can be used, allowing more efficient programming.
• A disadvantage is that valuable memory address space is used up.

Isolated I/O:
• The bus equipped with memory read and write plus input and output
command lines. The command line specifies whether the address refers to
a memory location or an I/O device.
• The full range of addresses may be available for both. With 10 address
lines, the system may now support both 1024 memory locations and 1024
I/O addresses. Because the address space for I/O is isolated from that for
memory
• The I/O ports are accessible only by special I/O commands, which activate
the I/O command lines on the bus (only a few I/O instructions).

5)
Four general categories of techniques are in common use for device identification:
o Multiple interrupt lines
o Software poll
o Daisy chain (hardware poll, vectored)
o Bus arbitration (vectored)

Multiple interrupt lines

• most straightforward approach to the problem
• provide multiple interrupt lines between the processor and the I/O modules
• impractical to dedicate more than a few bus lines or processor pins to
interrupt lines
• Consequently, even if multiple lines are used, it is likely that each line will
have multiple I/O modules attached to it.

Software poll
• When the processor detects an interrupt it branches to an interrupt-service
routine (also called an interrupt handler is a software routine that hardware
invokes in response to an interrupt) whose job is to poll each I/O module
to determine which module caused the interrupt
• The poll could be in the form of a separate command line (e.g., TESTI/O).
In this case, the processor raises TESTI/O and places the address of a
particular I/O module on the address lines. The I/O module responds
positively if it set the interrupt.
• Alternatively, each I/O module could contain an addressable status
register. The processor then reads the status register of each I/O module to
identify the interrupting module. Once the correct module is identified, the
processor branches to a device-service routine specific to that device.
• Time consuming

Daisy chain (hardware poll, vectored)

• For interrupts, all I/O modules share a common interrupt request line.
• The interrupt acknowledge line is daisy chained through the modules.
• When the processor senses an interrupt, it sends out an interrupt
acknowledge. This signal propagates through a series of I/O modules until
it gets to a requesting module.

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 it gets to a requesting module.
• The requesting module typically responds by placing a word on the data
lines.
• This word is referred to as a vector and is either the address of the I/O
module or some other unique identifier.
• In either case, the processor uses the vector as a pointer to the appropriate
device-service routine.

6)
• The processor pauses for each bus cycle stolen by the DMA module.
• During DMA the CPU is idle and it has no control over the memory buses.
The DMA controller takes over the buses to manage the transfer directly
between the I/O devices and the memory unit.
• Note that this is not an interrupt; the processor does not save a context and
do something else. Rather, the processor pauses and cause the processor to
execute more slowly.

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