Name Daniyal Masood Roll no BSEE18015

VLSI DESIGN
ASSIGNMENT # 5
Question 1:
a) Draw the butterfly diagram of the gates M1, M2 and M3.
Butterfly Diagrams are drawn on the front page on given diagrams.

b) Comment if the gates M1, M2 and M3 are digital or not based on butterfly diagram.
Since this part can be commented on the basis of 𝑁𝑀 𝑎𝑛𝑑 𝑁𝑀 values. After
computing these values for each of the diagram I have the following comments:
 For M1, since its 𝑁𝑀 is equal to 0, but 𝑁𝑀 is positive that’s why we can say
it’s partially digital.
 For M2, since both of the 𝑁𝑀 𝑎𝑛𝑑 𝑁𝑀 are positive, that’s why we can say it’s
perfectly digital.
 For M3, since the value of 𝑁𝑀 is negative that’s why we can say that it’s not
digital.

c) Now consider only cascade of M2 and M3. Draw single VTC for the cascade
considering V2 as input and V4 as output of cascaded gate.
Since when M2 and M3, will be in cascaded form we can observe that when 𝑉 is in the
range of 0V to 0.2V, the output of the M2 will be 1.2V which corresponds that the output
of the combined M2 and M3 which is M4 is 𝑉 = 0.3, this will remain fix until the
output of 𝑀 reaches at 1V which is 𝑉 in the case of 𝑀 the output of M4 linearly
increases until the output of M2 reaches until the 𝑉 reaches at 0.2V, which is the 𝑉 in
the case of 𝑀 . After that the output voltage of 𝑀 will be constant 1.2V, in the range of
input voltage 0.867V to 1.2V, The VTC diagram is drawn on the back of first page.

d) Compute the numerical values of the noise margins in Volts for the cascade VTC.
From the above VTC diagram we have the following data:
𝑉 = 0.333𝑉 𝑉 = 0.3𝑉 𝑉 = 1.2𝑉 𝑉 = 0.86𝑉
Now the noise margin for the cascaded gates can be calculated as:
𝑁𝑀 =𝑉 − 𝑉 = 0.333𝑉 − 0.3𝑉 = 𝟎. 𝟎𝟑𝟑𝑽
𝑁𝑀 =𝑉 − 𝑉 = 1.2𝑉 − 0.86𝑉 = 𝟎. 𝟑𝟒𝑽

e) Draw butterfly diagram for the cascade of the two gates

The butterfly diagram is drawn on the back side of first page on the VTC diagram in
black color.
f) Determine whether the cascade of the two gates is digital or not?
Since both noise margins are positive, M4 is definitely a digital gate.
Question 2:
Gate or switching thershold voltage is an input voltage where current of pull-up network
and current of pull-down network becomes equal. Derive the expression of switching
threshold voltage for
a) Long Channel Model:
We know that 𝐼 and 𝐼 is given as.
𝛽
𝐼 = (𝑉 − 𝑉 )
2
𝛽
𝐼 = 𝑉 − 𝑉 − |𝑉 |
2
Now equate the both currents
𝛽 𝛽
𝐼 =𝐼 => (𝑉 − 𝑉 ) = 𝑉 − 𝑉 − |𝑉 |
2 2
𝛽 𝛽 𝛽 1
(𝑉 − 𝑉 ) = 𝑉 − 𝑉 − |𝑉 | , 𝑤ℎ𝑒𝑟𝑒 = 𝑟 => =
𝛽 𝛽 𝛽 𝑟

𝑇𝑎𝑘𝑖𝑛𝑔 𝑠𝑞𝑢𝑎𝑟𝑒 𝑟𝑜𝑜𝑡 𝑜𝑛 𝑏𝑜𝑡ℎ 𝑠𝑖𝑑𝑒𝑠 𝑤𝑒 𝑔𝑒𝑡

1
(𝑉 − 𝑉 ) = 𝑉 − 𝑉 − |𝑉 |
𝑟

1 1
𝑉 +𝑉 = 𝑉 +𝑉 − |𝑉 |
𝑟 𝑟

1 1
𝑉 1+ =𝑉 − 𝑉 + 𝑉
𝑟 𝑟

𝟏
𝑽𝑫𝑫 − 𝑽𝒕𝒑 + 𝑽
𝒓 𝒕𝒉
𝑽𝑴 =
𝟏
𝟏+
𝒓
b) fully velocity saturated transistors.
We know that when the transistor is fully saturated than the values of the 𝐼 and 𝐼 is
given as.
𝐼 =𝑊𝐶 𝑣 (𝑉 − 𝑉 ) 𝐼 =𝑊𝐶 𝑣 (𝑉 − 𝑉 − |𝑉 |)
 Now equate the both currents
𝐼 =𝐼 => 𝑊 𝐶 𝑣 (𝑉 − 𝑉 ) = 𝑊 𝐶 𝑣 (𝑉 − 𝑉 − |𝑉 |)
𝑊𝐶 𝑣 (𝑉 − 𝑉 ) 𝑊𝐶 𝑣 1 𝑊𝐶 𝑣
= , 𝑤ℎ𝑒𝑟𝑒 = => =𝑟
𝑊𝐶 𝑣 (𝑉 − 𝑉 − |𝑉 |) 𝑊𝐶 𝑣 𝑟 𝑊𝐶 𝑣
1 𝑉 − 𝑉 − |𝑉 | 1 1
= = 𝑉 − 𝑉 =𝑉 − 𝑉 − |𝑉 |
𝑟 𝑉 −𝑉 𝑟 𝑟
1 1
𝑉 1+ =𝑉 − 𝑉 + 𝑉
𝑟 𝑟
𝟏
𝑽𝑫𝑫 − 𝑽𝒕𝒑 + 𝑽𝒕𝒉
𝑽𝑴 = 𝒓
𝟏
𝟏+
𝒓
Question 3:
a) A CMOS inverter is built in a process where 𝒌’𝒏 = 100μA/V2 , 𝒌’𝒑 = 42μA/V2, 𝑽𝒕𝒏 =
𝑾
0.7V, 𝑽𝒕𝒑 = -0.8V,and 𝑽𝑫𝑫 = 3.3V. Find the switching threshold voltage 𝑽𝑴 if =
𝑳 𝒏
𝑾
10 and = 14.
𝑳 𝒑
We know that according to the switching threshold voltage 𝑉 of the CMOS inverter.
1
𝑉 +𝑉 +𝑉
𝑟
𝑉 =
1
1+
𝑟
But firstly we need to calculate the value of 𝑟, which is as followed
𝑊
𝛽 𝑘 100 × 10 (10)
𝐿
𝑟= = = = 1.7
𝛽 𝑊 42 × 10 (14)
𝑘
𝐿
Now using the value of the 𝑟 we can find the value of the 𝑉
1 1
𝑉 +𝑉 +𝑉 3.3 − 0.8 + 0.7
𝑟 1.7
𝑉 = = 𝑉 = = 𝟏. 𝟒𝟖𝑽
1 1
1+ 1+
𝑟 1.7
b) Find the values of 𝜷𝒏 and 𝜷𝒑 needed to obtain an inverter thershold voltage 𝑽𝑴 of
1.3V with 𝑽𝑫𝑫 = 3V. Assume that 𝑽𝒕𝒏 = 0.6V, 𝑽𝒕𝒑 = -0.82V. What would be the
relative device sizes if 𝒌’𝒏 = 100μA/V2 and the mobility values are related by 𝝁𝒏 =
𝟐. 𝟐 𝝁𝒑 ?
We know that the values of the both 𝛽 and 𝛽 can be calculated as.
According to following relationship we know that
 𝛽 𝑘 𝜇
= = =𝑟
𝛽 𝑘 𝜇
Using that relationship, we can have deduced that,

𝑘 𝜇 100 × 10 2.2𝜇
= = =
𝑘 𝜇 𝑘 𝜇
100 × 10 𝐴
𝑘 = 45.45μ 2
2.2 𝑉
𝑊 𝑊
𝐴𝑠𝑠𝑢𝑚𝑖𝑛𝑔 𝑡ℎ𝑎𝑡 𝑎𝑛𝑑 𝑎𝑟𝑒 𝑡𝑎𝑘𝑖𝑛𝑔 𝑎𝑠 𝑖𝑡 𝑖𝑠 𝑏𝑒𝑐𝑎𝑢𝑠𝑒 𝑤𝑒 ℎ𝑎𝑣𝑒 𝑛𝑜 𝑣𝑎𝑙𝑢𝑒𝑠 𝑜𝑓 𝑡ℎ𝑒𝑠𝑒.
𝐿 𝐿
𝑾 𝑾
𝜷 𝒏 = 𝒌𝒏 = 𝟏𝟎𝟎 × 𝟏𝟎 𝟔
𝑳 𝒏 𝑳 𝒏
𝑾 𝑾
𝜷 𝒑 = 𝒌𝒑 = 𝟒𝟓. 𝟒𝟓 × 𝟏𝟎 𝟔
𝑳 𝒑 𝑳 𝒑