INTERNATIONAL JOURNAL FOR INNOVATIVE RESEARCH IN MULTIDISCIPLINARY FIELD ISSN – 2455-0620 Volume - 2, Issue - 10, Oct - 2016

Design of Image by Morphological Dilation Technique using Xilinx tool on FPGA

Dr.E.N.Ganesh
ECE Dept / Saveetha Engineering College, Chennai, India.
Email.- [email protected]

Abstract: Mathematical morphology is a well known image and signal processing technique. However,
most morphological tools such Matlab are not suited for strong real-time constraints. We address this
problem through hardware implementation on FPGAs. This paper gives the algorithm and implementation of
morphological image processing on FPGA. The design is implemented on a Xilinx xc3s500e-4fg320 FPGA
chip. The design is tailored to exploit certain features of sliding windows.

Keywords: Morphology, Matlab, FPGAs, Image Processing, xc3s500e-4fg320.

1. INTRODUCTION: hardware design is still required, but the learning curve is

much lower than other design choices .
DIGITAL image processing is an ever expanding and
dynamic area with applications reaching out into our Field Programmable Gate Arrays are reconfigurable
everyday life such as medicine, space exploration, devices. Hardware design techniques such as parallelism
surveillance, authentication, automated industry and pipelining techniques can be developed on a FPGA,
inspection and many more areas. Applications such as which is not possible in dedicated DSP designs.
these involve different processes like image enhancement Implementing image processing algorithms on
and object detection. Implementing such applications on a reconfigurable hardware minimizes the time-to-market
general purpose computer can be easier, but not very time cost, enables rapid prototyping of complex algorithms and
efficient due to additional constraints on memory and simplifies debugging and verification. Therefore, FPGAs
other peripheral devices. are an ideal choice for implementation of real time image
processing algorithms.
Application specific hardware implementation offers
much greater speed than a software implementation. With FPGAs have traditionally been configured by hardware
advances in the VLSI (Very Large Scale Integrated) engineers using a Hardware Design Language (HDL).
technology hardware implementation has become an The two principal languages used are Verilog HDL
attractive alternative. Implementing complex computation (Verilog) and Very High Speed Integrated Circuits
tasks on hardware and by exploiting parallelism and (VHSIC) HDL (VHDL) which allows designers to design
pipelining in algorithms yield significant reduction in at various levels of abstraction.
execution times.
Given the importance of digital image processing and the
There are two types of technologies available for significance of their implementations on hardware to
hardware design. Full custom hardware design also called achieve better performance, this work addresses
as Application Specific Integrated Circuits (ASIC) and implementation of image processing algorithms like
semi custom hardware device, which are programmable median filter, orphological, convolution and smoothing
devices like Digital signal processors (DSPs) and Field operation and edge detection on FPGA using VHDL
Programmable Gate Arrays (FPGA’s). language. Also novel architectures for the above
mentioned image processing algorithms have been
Full custom ASIC design offers highest performance, but proposed. Gray-level images are very common in image
the complexity and the cost associated with the design is processing. These types of images use eight bits to code
very high. The ASIC design cannot be changed and the each pixel value, which results in 256 different possible
design time is also very high. ASIC designs are used in shades of grey, ranging from 0 (black value) to 255 (white
high volume commercial applications. value). Latest generations FPGAs compute more than 160
billion multiplication and accumulation (MAC)
In addition, during design fabrication the presence of a operations per second.
single error renders the chip useless. DSPs are a class of
hardware devices that fall somewhere between an ASIC 2. IMAGE PROCESSING ALGORITHM:
and a PC in terms of the performance and the design
complexity. This section discusses the theory of most commonly used
image processing algorithms like (1) Filtering, (2)
DSPs are specialized microprocessors, typically Morphological operations
programmed in C, or with assembly code for improved
performance. It is well suited to extremely complex math A. Median Filtering: A median filter is a non-linear
intensive tasks such as image processing. Knowledge of digital filter which is able to preserve sharp signal
changes and is very effective in removing impulse noise

Design of Image by Morphological Dilation Technique using Xilinx tool on FPGA Page 618
INTERNATIONAL JOURNAL FOR INNOVATIVE RESEARCH IN MULTIDISCIPLINARY FIELD ISSN – 2455-0620 Volume - 2, Issue - 10, Oct - 2016

(or salt and pepper noise). An impulse noise has a gray

level with higher or lower value that is different from the
neighborhood point.

Linear filters don’t have ability to remove this type of

noise without affecting the distinguishing characteristics
of the signal. Median filters have remarkable advantages
over linear filters for this particular type of noise.
Therefore median filter is very widely used in digital
signal and image/video processing applications.

A standard median operation is implemented by sliding a

window of odd size (e.g. 3x3 window) over an image. At
each window position, the sampled values of signal or
image are sorted, and the median value of the samples
replaces the sample in the center of the window as shown
in Figure1.

3 x 3 window
Figure 2. Simulation result of median Filter.

The most basic morphological operations are dilation and

erosion. Dilation adds pixels to the boundaries of objects
in an image, while erosion removes pixels on object
boundaries. The number of pixels added or removed from
the objects in an image depends on the size and shape of
the structuring element used to process the image.

In the morphological dilation and erosion operations, the

state of any given pixel in the output image is determined
by applying a rule to the corresponding pixel and its
neighbors in the input image.

Rules for Dilation and Erosion: Dilation- The value of the

output pixel is the maximum value of all the pixels in the
input pixel's neighborhood. In a binary image, if any of
Median the pixels is set to the value 1, the output pixel is set to 1.
B. Morphological Operation
The term morphological image processing refers to a class Erosion- The value of the output pixel is the minimum
of algorithms that transforms the geometric structure of an value of all the pixels in the input pixel's neighborhood. In
image.
a binary image, if any of the pixels is set to 0, the output
Morphology can be used on binary and gray scale images, pixel is set to 0.
and is useful in many areas of image processing,
such as skeletonization, edge detection, restoration and The grayscale erosion is performed by minimum filter,
texture analysis. whereas the dilation is performed by maximum filter. In a
3 x 3 minimum filter, the centre pixel is replaced by a
Centre pixel replaced with median value minimum
value of the pixels in the window. In a maximum filter,
the centre pixel is replaced y a maximum value of the
pixels in the window. The implementation of minimum
and maximum filters is similar to the median filters
implementation.

Morphological Dilation of a grayscale image

Figure 1. Median Filter.

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INTERNATIONAL JOURNAL FOR INNOVATIVE RESEARCH IN MULTIDISCIPLINARY FIELD ISSN – 2455-0620 Volume - 2, Issue - 10, Oct - 2016

Figure 4. Simulation result of Dilation.

Input image

Figure 5. Simulation result of Erosion.

Output image
Figure 3. Block schematic of sort-3 A: Implementation
The entire implementation of image acquisition, image
processing and image retrieval is shown in block diagram
III. ALGORITHM of figure 4. In order to reduce complexity of data
Step I: First the numbers are sorted vertically i.e. sort transactions, RAM is implemented on FPGA.
elements of each column in the ascending order. UART is implemented to felicitate data acquisition and
communication between PC and FPGA board.
Step II: Numbers are sorted horizontally i.e. sort elements
of each row in the ascending order.

Step III: Sort the cross diagonal elements and pick up the
middle element as the median element of the window.
Minimum is the first and maximum is the last element in
the window of the nine elements.

The block schematic of sort-3 is shown in Figure 3.

3 x 3 window pixels values are sorted and outputs H[7:0],

M[7:0], L[7:0] correspond to maximum, median and
minimum values respectively.

Figure 6. Simulation result of RAM

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INTERNATIONAL JOURNAL FOR INNOVATIVE RESEARCH IN MULTIDISCIPLINARY FIELD ISSN – 2455-0620 Volume - 2, Issue - 10, Oct - 2016

REFERENCES:

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WEB REFERENCES:
www.xilinx.com
www.mathworks.com

Figure 8 Block diagram of design implemented on FPGA

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