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This document describes the components and operation of a basic CPU architecture. It contains: 1) Registers that are used to read data from memory and write results back to memory. 2) An ALU that performs arithmetic and logical operations on data from registers. 3) Control lines that determine the operation of the CPU by specifying the register addresses, ALU operation, and whether to write results or branch the program counter.

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Coa Assignment

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ray ban
22 views4 pages
This document describes the components and operation of a basic CPU architecture. It contains: 1) Registers that are used to read data from memory and write results back to memory. 2) An ALU that performs arithmetic and logical operations on data from registers. 3) Control lines that determine the operation of the CPU by specifying the register addresses, ALU operation, and whether to write results or branch the program counter.

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Computer organization and architecture assignment

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coa assignment

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This document describes the components and operation of a basic CPU architecture. It contains: 1) Registers that are used to read data from memory and write results back to memory. 2) An ALU that performs arithmetic and logical operations on data from registers. 3) Control lines that determine the operation of the CPU by specifying the register addresses, ALU operation, and whether to write results or branch the program counter.

Copyright:

© All Rights Reserved
Download as PDF, TXT or read online from Scribd
Download as pdf or txt
22 views4 pages

Coa Assignment

Uploaded by

ray ban
This document describes the components and operation of a basic CPU architecture. It contains: 1) Registers that are used to read data from memory and write results back to memory. 2) An ALU that performs arithmetic and logical operations on data from registers. 3) Control lines that determine the operation of the CPU by specifying the register addresses, ALU operation, and whether to write results or branch the program counter.

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© All Rights Reserved
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0

M
u
x
ALU
Add result 1
Add Shift PCSrc
RegDst left 2
4 Branch
MemRead
Instruction [31 26] MemtoReg
Control
ALUOp
MemWrite
ALUSrc
RegWrite

Instruction [25 21] Read


PC Read register 1
address Read
Instruction [20 16] data 1
Read
register 2 Zero
Instruction 0 Registers Read ALU ALU
[31– 0] 0 Read
M Write data 2 result Address 1
Instruction u register M data
u M
memory Instruction [15 11] x u
1 Write x Data
data x
1 memory 0
Write
data
16 32
Instruction [15 0] Sign
extend ALU
control

Instruction [5 0]
0
M
u
x
ALU
Add result 1
Add Shift PCSrc
RegDst left 2
4 Branch
MemRead
Instruction [31 26] MemtoReg
Control
ALUOp
MemWrite
ALUSrc
RegWrite

Instruction [25 21] Read


PC Read register 1
address Read
Instruction [20 16] data 1
Read
register 2 Zero
Instruction 0 Registers Read ALU ALU
[31– 0] 0 Read
M Write data 2 result Address 1
Instruction u register M data
u M
memory Instruction [15 11] x u
1 Write x Data
data x
1 memory 0
Write
data
16 32
Instruction [15 0] Sign
extend ALU
control

Instruction [5 0]
0
M
u
x
ALU
Add result 1
Add Shift PCSrc
RegDst left 2
4 Branch
MemRead
Instruction [31 26] MemtoReg
Control
ALUOp
MemWrite
ALUSrc
RegWrite

Instruction [25 21] Read


PC Read register 1
address Read
Instruction [20 16] data 1
Read
register 2 Zero
Instruction 0 Registers Read ALU ALU
[31– 0] 0 Read
M Write data 2 result Address 1
Instruction u register M data
u M
memory Instruction [15 11] x u
1 Write x Data
data x
1 memory 0
Write
data
16 32
Instruction [15 0] Sign
extend ALU
control

Instruction [5 0]
0
M
u
x
ALU
Add result 1
Add Shift PCSrc
RegDst left 2
4 Branch
MemRead
Instruction [31 26] MemtoReg
Control
ALUOp
MemWrite
ALUSrc
RegWrite

Instruction [25 21] Read


PC Read register 1
address Read
Instruction [20 16] data 1
Read
register 2 Zero
Instruction 0 Registers Read ALU ALU
[31– 0] 0 Read
M Write data 2 result Address 1
Instruction u register M data
u M
memory Instruction [15 11] x u
1 Write x Data
data x
1 memory 0
Write
data
16 32
Instruction [15 0] Sign
extend ALU
control

Instruction [5 0]

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