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Clock Numberin Start Count Overflow 5 5 1 5 5 5 5 5 X 0 1 2 2 FF 0 1 0 X

This homework asks students to design a counter circuit that counts the number of times the number "5" appears in a 4-bit input stream. Specifically, it wants a gate-level schematic showing: - An 8-bit counter (Count) that tracks the number of "5" appearances since the Start signal went low. - An Overflow signal that goes high if the counter overflows and stays high until Start is asserted again. - Use of only D flip-flops for storage, clocked only by the clock signal. It provides an example timing diagram and expects familiarity with common digital logic concepts like gates, adders, multiplexors, and finite state machines. The

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73 views2 pages

Clock Numberin Start Count Overflow 5 5 1 5 5 5 5 5 X 0 1 2 2 FF 0 1 0 X

This homework asks students to design a counter circuit that counts the number of times the number "5" appears in a 4-bit input stream. Specifically, it wants a gate-level schematic showing: - An 8-bit counter (Count) that tracks the number of "5" appearances since the Start signal went low. - An Overflow signal that goes high if the counter overflows and stays high until Start is asserted again. - Use of only D flip-flops for storage, clocked only by the clock signal. It provides an example timing diagram and expects familiarity with common digital logic concepts like gates, adders, multiplexors, and finite state machines. The

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Copyright
© © All Rights Reserved
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ECE 464/520

Homework 0

The purpose of this REQUIRED homework and associated Moodle quiz is to evaluate
your preparation for this course. If you feel you need to review material to do this
homework, there are several good basic digital logic texts in the library (see the last page
of this homework). Turn in the solutions with your name on it on-line or in class.

The design question is worth 20 points.

Question 1

This is a design question. Please design a counter that counts the number of times the
number “5” appears in an 4-bit input stream. The I/O are as follows:

NumberIn : 4-bits wide (input)


Start: Set counter and overflow flag to zero while start is high on rising edges of the
clock. (counter and overflow and synchronized to the clock).
Count: 8-bit unsigned count (of the number of “5”s that have occurred since start went
low (output) (More specifically if start is low on the rising edge of the clock then
that input is counted – see example below).
Overflow: Goes high if count overflows (count is unsigned, so you only need to monitor
the adder carry out) and stays high until start is re-asserted.

This is NOT A VERILOG question; I want to see a gate level schematic. Design this
functional unit down to the logic (gate) level. An adder is required – you can represent
this as a “+” unit – no need to design its detail. There is no need to optimize the design.
The only flip-flop you can use is a D flip-flop, and its clock input can only be connected
to “clock”. You can NOT use a flip-flop with preset or clear. Muxes and adders can be
drawn as single blocks, you do not have to design their internal structure.

An exemplar timing diagram can be found below (x=unknown). Note the following:
- Count and Overflow are changing just after the rising edges of the clock
- Overflow stays high until the clock cycle after start goes back to one

clock …
NumberIn 5 5 1 5… 5 5 5 5
Start
Count X 0 1 2 2 … FF 0 1 0
Overflow x

1
Revision Notes

I do expect you to be very familiar with at least the following concepts:


o Different combinational logic structures, including gates, adders, multipliexors,
coders, decoders, etc.
o Combinational logic optimization
o Flip-flops and latches, and their operation.
o Timing diagrams. How to produce one.
o Finite State Machines – purpose, operation, types, state vector encoding
o MOST IMPORTANTLY, I expect you to be able to design a logic function to a
specification (like in this homework with relative ease)

If any of these topics are NOT familiar to you, I suggest reviewing your undergraduate
logic course or logic course text. If that is not available to you, there are many suitable
texts in the library. Authors include Katz, Wakerley, Mano, but there are many others.

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