NORTH SOUTH UNIVERSITY

DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING

EEE413L/CSE413L/ETE419L: Verilog HDL: Modeling, Simulation & Synthesis

Lab 7_Part 1: Design an 8 function ALU using case statement of behavioral modeling.
Also do the synthesis in Xilinx

Design an 8 functions ALU that takes 4-bit inputs a and b and a 3-bit input signal select, and gives a 5-bit
output out. The ALU implements the following functions based on a 3-bit input signal select.

Select Signal Function

3’b000 out = a
3’b001 out = a+b
3’b010 out = a-b
3’b011 out = a/b
3’b100 out = a%b (remainder)
3’b101 out = a<<1
3’b110 out = a>>1
3’b111 out = (a>b) (magnitude compare)

Main Module:
module alu(out,select,a,b);
output [4:0]out;
input [3:0] a,b;
input [2:0] select;
reg [4:0]out;
always@(select,a,b)
begin
case(select)
3’b000: out =a;
3’b001: out =a+b;
3’b010: out =a-b;
3’b011: out =a/b;
3’b100: out =a%b;
3’b101: out =a<<1;
3’b110: out =a>>1;
3’b111: out =a>b;
default:$display(“invalid”);
endcase
end
endmodule
 NORTH SOUTH UNIVERSITY
DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING
EEE413L/CSE413L/ETE419L: Verilog HDL: Modeling, Simulation & Synthesis

Test bench:
module stimulus;
wire [4:0]out;
reg [3:0] a,b;
reg [2:0] S;
alu a1(out,S,a,b);
initial
$monitor($time,“out=%b,a=%b,b=%b, select=%b”, out, a,b,S);
initial
begin
a=4’b1010; b=4’b0101;
S=3’b000;
#5 S=3’b001;
#5 S=3’b010;
#5 S=3’b011;
#5 S=3’b100;
#5 S=3’b101;
#5 S=3’b110;
#5 S=3’b111;
#5 $stop;
end
endmodule
 NORTH SOUTH UNIVERSITY
DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING
EEE413L/CSE413L/ETE419L: Verilog HDL: Modeling, Simulation & Synthesis

Lab 7_Part 2: Design a traffic control system using finite state machine approach of
behavioral modeling. Also do the synthesis using Xillinx
Finite State Machine (FSM):
A finite-state machine (FSM) or finite-state automaton (FSA, plural: automata), finite automaton, or simply a
state machine, is a mathematical model of computation. It is an abstract machine that can be in exactly one of a
finite number of states at any given time. The FSM can change from one state to another in response to some
inputs; the change from one state to another is called a transition. An FSM is defined by a list of its states, its
initial state, and the inputs that trigger each transition.
The behavior of state machines can be observed in many devices in modern society that perform a
predetermined sequence of actions depending on a sequence of events with which they are presented. Simple
examples are vending machines, which dispense products when the proper combination of coins is
deposited, elevators, whose sequence of stops is determined by the floors requested by riders, traffic lights,
which change sequence when cars are waiting, and combination locks, which require the input of a sequence of
numbers in the proper order.

Traffic Signal Controller:

Consider a controller for traffic at the intersection of a main highway and a country road.

The following specifications must be considered.

 The traffic signal for the main highway gets highest priority because cars are continuously present on the
main highway. Thus, the main highway signal remains green by default.

 Occasionally, cars from the country road arrive at the traffic signal. The traffic signal for the country
road must turn green only long enough to let the cars on the country road go.

 As soon as there are no cars on the country road, the country road traffic signal turns yellow and then
red and the traffic signal on the main highway turns green again.

 There is a sensor to detect cars waiting on the country road. The sensor sends a signal X as input to the
controller. X = 1 if there are cars on the country road; otherwise, X= 0.
 NORTH SOUTH UNIVERSITY
DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING
EEE413L/CSE413L/ETE419L: Verilog HDL: Modeling, Simulation & Synthesis

 There are delays on transitions from S1 to S2, from S2 to S3, and from S4 to SO. The delays must be
controllable.
The state machine diagram and the state definitions for the traffic signal controller are shown in the figure
given below:

Figure: FSM for Trafiic Signal Controller

Main Module:
`define TRUE l’bl
`define FALSE l'b0
`define RED 2 'd0
`define YELLOW 2'dl
`define GREEN 2'd2

//State definition HWY CNTRY

`define S0 3'd0 //GREEN RED
`define S1 3'dl //YELLOW RED
`define S2 3'd2 //RED RED
`define S3 3'd3 //RED GREEN
`define S4 3'd4 //RED YELLOW

//Delays
`define Y2RDELAY 3 //Yellow to red delay
`define R2GDELAY 2 //Red to green delay
 NORTH SOUTH UNIVERSITY
DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING
EEE413L/CSE413L/ETE419L: Verilog HDL: Modeling, Simulation & Synthesis

module sig-control (hwy, cntry, X, clock, clear);

//I/O ports
output [1:0] hwy, cntry; //2-bit output for 3 states of signal GREEN, YELLOW, RED;
reg [1:0] hwy, cntry; //declared output signals are registers
input X; //if TRUE, indicates that there is car on the country road, otherwise FALSE
input clock, clear;

//Internal state variables

reg [2:0] state;
reg [2:0] next-state;

//Signal controller starts in SO state

initial
begin
state = `SO;
next-state= `SO;
hwy = `GREEN;
cntry = `RED;
end

//state changes only at positive edge of clock

always @ (posedge clock)
state = next-state;

//Compute values of main signal and country signal

always @(state)
begin
case (state)
`SO: begin
hwy = `GREEN;
cntry = `RED;
end
`S1: begin
hwy = `YELLOW;
cntry = `RED;
end
`S2: begin
hwy = `RED;
cntry = `RED;
end
`S3: begin
hwy = `RED;
cntry = `GREEN;
end
 NORTH SOUTH UNIVERSITY
DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING
EEE413L/CSE413L/ETE419L: Verilog HDL: Modeling, Simulation & Synthesis

`S4: begin
hwy = `RED;
cntry = `YELLOW;
end
endcase
end

//State machine using case statements

always @ (state or clear or X)
begin
if (clear)
next-state = `SO;
else
case (state)
`SO: if (X)
next-state = `Sl;
else
next-state = `SO;
`Sl: begin //delay some positive edges of clock
repeat(`Y2RDELAY) @ (posedge clock);
next-state = `S2;
end
`S2: begin //delay some positive edges of clock
repeat (`R2GDELAY) @ (posedge clock)
next-state = `S3;
end
`S3: if(X)
next-state = `S3;
else
next-state = `S4;
`S4: begin //delay some positive edges of clock
repeat(`Y2RDELAY) @ (posedge clock);
next-state = `SO;
end
default: next-state = `SO;
endcase
end
endmodule
 NORTH SOUTH UNIVERSITY
DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING
EEE413L/CSE413L/ETE419L: Verilog HDL: Modeling, Simulation & Synthesis

Test Bench:
//Stimulus Module
module stimulus;
wire [l: 0] MAIN-SIG, CNTRY-SIG;
reg CAR-ON-CNTRY-RD;
//if TRUE, indicates that there is car on
//the country road
reg CLOCK, CLEAR;
//Instantiate signal controller
sig-control SC (MA1N-SIG, CNTRY-SIG, CAR-ON-CNTRY-RD, CLOCK, CLEAR);
//Set up monitor
initial
$monitor ($time,"Main Sig = %b Country Sig = %b Car-on-cntr = %b”, MAIN-SIG, CNTRY-SIG, CAR-
ON-CNTRY-RD);
//Set up clock
initial
begin
CLOCK = `FALSE;
forever #5 CLOCK = -CLOCK;
end
//control clear signal
initial
begin
CLEAR = `TRUE
repeat (5) @ (negedge CLOCK);
CLEAR = `FALSE;
end
//apply stimulus
initial
begin
CAR-ON-CNTRY-RD = `FALSE;

#200 CAR-ON-CNTRY-RD = `TRUE;

#l00 CAR-ON-CNTRY-RD = `FALSE;

#200 CAR-ON-CNTRY-RD = `TRUE;

#l00 CAR-ON-CNTRY-RD = `FALSE;

#200 CAR-ON-CNTRY-RD = `TRUE;

$100 CAR-ON-CNTRY-RD = `FALSE;
#100 $stop;
end
endmodule