a fret rrry PAN pcre PTT Lea: Digilent FPGA CDE es lean Bal ele pec alesPreface A major revolution in digital design has taken place over the past decade. Field programmable gate arrays (FPGAs) can now contain over a million equivalent logic gates and tens of thousands of flip-flops. This means that it is not possible to use traditional methods of logic design involving the drawing of logic diagrams when the digital circuit may contain thousands of gates, The reality is that today digital systems are designed by writing software in the form of hardware description languages (HDLs). The most common HDLs used today are VHDL and Verilog. Both are in widespread use. When using these hardware description languages the designer typically deseribes the behavior of the logic circuit rather than writing traditional Boolean logic equations. Computer-aided design tools are used to both simulate the VHDL or Verilog design and to synthesize the design to actual hardware. This book assumes no previous knowledge of digital design. We use 30 examples to show you how to get started designing digital circuits that you ean implement on a Xilinx Spartan3E FPGA using either the Digilent BASYS™ system board that can be purchased from wwwdigilentine.com for $59 or the Digilent Nexys-2 board that costs $99. We will use Active-HDL from Aldec to design, simulate, synthesize, and implement our digital designs. A free student edition of Active-HDL is available from Aldec, Inc. (www.aldee.com). To synthesize your designs to a Spartan3E FPGA you will need to download the free ISE WebPACK from Xilinx, Ine. (www.xilinx.com). The Xilinx synthesis tools_are_called from within the Aldec Active-HDL integrated GUI. We will use the ExPort utility to download your synthesized design to the Spartan3E FPGA. ExPort is part of the Adept software suite that you can download free from Digilent, Inc. wwww.digilentine.com), A more complete book called Digital Design Using Digilent FPGA Boards — VHDL / Active-HDL Edition is also available from igilent or LBE Books (www-lbebooks.com). This more comprehensive book contains over 75 examples including examples of using the VGA and PS/2 ports. Similar books that use Verilog are also available from Digilent or LBE Books. Many colleagues and students have influenced the development of this book. ‘Their stimulating discussions, probing questions, and critical comments are greatly appreciated. Richard E, Haskell Darrin M. HannaIntroduction 1 Introduction Digital Design Using FPGAs The first integrated circuits that were developed in the early 1960s contained less that 100 transistors on a chip and are called small-scale integrated (SSI) circuits. Medium-scale integrated (MSI) circuits, developed in the late 1960s, contain up to several hundreds of transistors on a chip. By the mid 1970s large-scale integrated (LSI) circuits containing several thousands of transistors had been developed. Very-large-scale integrated (VLSI) circuits containing over 100,000 transistors had been developed by the early 1980s. This trend has continued to the present day with 1,000,000 transistors on a chip by the late 1980s, 10,000,000 transistors on a chip by the mid-1990s, over 100,000,000 transistors by 2004, and up to 1,000,000,000 transistors on a chip today This exponential growth in the amount of digital logic that can be packed into a single chip has produced serious problems for the digital designer. How can an engineer, or even a team of engincers, design a digital logic circuit that will end up containing millions of transistors? In Appendix C we show that any digital logic circuit can be made from only three types of basic gates: AND, OR, and NOT. In fact, we will see that any digital logic circuit can be made using only NAND gates (or only NOR gates), where each NAND or NOR gate contains four transistors. These basic gates were provided in SSI chips using various technologies, the most popular being transistor-transistor logic (TTL). These TIL chips were-the-mainstay of digital design throughout the 1960s and 1970s. Many ‘MSI TTL chips became available for performing all types of digital logic functions such as decoders, adders, multiplexers, comparators, and many others. By the 1980s thousands of gates could fit on a single chip. Thus, several different varieties of programmable logic devices (PLDs) were developed in which arrays containing large numbers of AND, OR, ahd NOT gates were arranged in a single chip without any predetermined function. Rather, the designer could design any type of di 1 circuit and implement it by connecting the internal gates in a particular way. This is usually done by opening up fuse links within the chip using computer-aided tools. Eventually the equivalent of many PLDs on a single chip led to complex programmable logic devices (CPLDs). Field Programmable Gate Arrays (FPGAs) A completely different architecture was introduced in the mid-1980’s that uses RAM-based lookup tables instead of AND-OR gates to implement combinational logic. ‘These devices are called field programmable gate arrays (FPGAs). The device consists of an array of configurable logic blocks (CLBs) surrounded by an array of V/O block: ‘The Spartan-3E from Xilinx also contains some blocks of RAM, 18 x 18 multipliers, as well as Digital Clock Manager (DCM) blocks. These DCMs are used to eliminate clock distribution delay and can also increase or decrease the frequency of the clock.2 Introduction Each CLB in the Spartan-3E FPGA contains four slices, each of which contains two 16 x 1 RAM look-up tables (LUTs), which can implement any combinational logic function of four variables. In addition to two look-up tables, each slice contains two D flip-flops which act as storage devices for bits. ‘The basic architecture of a Spartan-3E FPGA is shown in Fig. 1. Figure 1 Architecture of a Spartan-3E FPGA The BASYS board from Digilent contains a Xilinx Spartan3E-100 TQ144 FPGA. This chip contains 240 CLBs arranged as 22 rows and 16 columns. There are therefore 960 slices with a total of 1,920 LUTs and flip-flops. This part also contains 73,728 bits of block RAM. Half of the LUTs on the chip can be used for a maximum of 15,360 bits of distributed RAM. By contrast the Nexys-2 board from Digilent contains a Xilinx Spartan3E-500 £G320 FPGA. This chip contains 1,164 CLBs arranged as 46 rows and 34 columns. ‘There are therefore 4,656 slices with a total of 9,312 LUTs and flip-flops. This part also contains 368,640 bits of block RAM. Half of the LUTs on the chip can be used for a maximum of 74,752 bits of distributed RAM. In general, FPGAs can implement much larger digital systems than CPLDs as illusirated in Table 1. The column labeled No. of Gates is really equivalent gates as we have seen that FPGAs really don’t have AND and OR gates, but rather just RAM look-up tables. (Each slice does include two AND gates and two XOR gates as part of carry and arithmetic logic used when implementing arithmetic functions including addition andIntreduction 3 multiplication.) Note from Table 1 that FPGAs can have the equivalent of millions of gates and tens of thousands of flip-flops. ‘Table 1_ Comparing Xilinx CPLDs and FPGAs Xilinx Part No. of Gates No. of Os _| No. of CLBs | No. of Flip-flops | Block RAM (bits) CPLDs | 9500 family 800 - 6,400 34-192 36 - 288 | | FPGAs I | ‘Spartan 5,000- _40,000| __77~224| 100 ~ 784 360 ~ 2,016 | Spartan | 15,000- 200,000| _86—284| _96-1,176 642-5,556| 16,384 —- 57,344 Spartan IE | 23,000— 600,000| _182—514| se4~3,456| 2,082- 15,366 92,768 ~ 204,012 Spartan 3 | 50,000-5,000,000| 124-74] 192—28,320| 2.280=71,264 [73,726 — 1,916,028 ‘Spartan-3E _|100,000— 1,600,000] 108-376 | 240-3,688| 1.920- 29.505 | 73,728- 663,552 Virtex | 57,908 —1,124,022| 180-512 | 384~ 6,144 | 2,076~26,112| 32,768- 131,072 VirtexE | 71,693 4,074,387 | 176 — 804 | 384—16,224| 1,888 - 66,604] 66,596 — 857,968 Virtex-ll__| 40,960—8,388,608 881,108 64—11,648| 1,040 — 99,832 [73,728 — 3,096,576 Modern Design of Digital Systems The traditional way of designing digital circuits is to draw logic diagrams containing SSI gates and MSI logic functions. However, by the late 1980s and carly 1990s such a process was becoming problematic. How can you draw schematic diagrams containing hundreds of thousands or millions of gates? As programmable logic devices replaced TTL chips in new designs a new approach to digital design became necessary. Computer-aided tools are essential to designing digital circuits today. What has become clear over the last decade is that today’s digital engineer designs digital systems by writing software! This is a major paradigm shift from the traditional method of designing digital systems. Many of the traditional design methods that were important when using TIL chips are less important when designing for programmable logic devices. Today digital designers use hardware description languages (HDLs) to design I systems. The most widely used HDLs are VHDL and Verilog. Both of these hardware description languages allow the user to design digital systems by writing a program that describes the behavior of the digital circuit. The program can then be used to both simulate the operation of the cirenit and synthesize an actual implementation of the circuit in a CPLD, an FPGA, or an application specific integrated circuit (ASIC). Another recent trend is to design digital circuits using block diagrams or graphic | symbols that represent higher-level design constructs. ‘These block diagrams can then be ‘compiled to produce Verilog or VHDL code. We will illustrate this method in this book. We will use Active-HDL from Aldec for designing our digital circuits. This integrated tool allows you to enter your design using either a block diagram editor (BDE) or by writing Verilog or VHDL code using the hardware description editor (HDE). Once your hardware has been described you can use the functional simulator to produce waveforms that will verify your design. This hardware description can then be synthesized to logic equations and implemented or mapped to the FPGA architecture.4 Introduction We include a tutorial for using Active-HDL in Appendix A. A fice student version of Active-HDL is available on their website.! “We will use Xilinx ISE for synthesizing our VHDL designs. You can download a free version of ISE™ WebPACK™ from the Xilinx website? This WebPACK™ synthesis tool can be run from within the Aldec Active-HDL development environment as shown in the tutorial in Appendix A. The implementation process creates a .bit file that is downloaded to a Xilinx FPGA on the BASYS board or Nexys-2 showa in Fig. 2. The BASYS board is available 10 students for $59 from Digilent, Inc3 This board includes a 100k-gate equivalent Xi Spartan3E FPGA (250k-gate capacity is also available), 8 slide switches, 4 pushbutton switches, § LEDs, and four 7-segment displays. The frequency of an on-board clock can be set to 25 MHz, 50 MHz, or 100 MHz using a jumper. There are connectors that allow the board to be interfaced to external circuits. The board also includes a VGA port and a PS2 port. The use of these ports are described in a different book — Another more advanced board, the Nexys-2 board, is also available to students for $99 from Digilent. The Nexys-2 board is similar to the BASYS board except that it contains a 500k- or 1200k-gate equivalent Spartan 3E FPGA, a Hirose FX2 interface for additional add-on component boards, 16 MB of cellular RAM, 16 MB of flash memory, a 50 MHz clock and a socket for a second oscillator. The Nexys-2 is ideally suited for embedded processors, All of the examples in this book can be used on both the BASYS board and the Nexys-2 board. The only difference is that you would use the file basys2.ucf to define the pinouts on the BASYS board and you would use the file nexys2.uef to define the pinouts on the Nexys-2 board. Both of these files are available to download from wwwilbebooks.com. Table 2 shows the jumper settings you would use on the two boards. Oui imnennn Figure 2 (a) BASYS board, (b) Nexys-2 Board 1 hup:/iwww aldec.com/education/ 2 hutpywww.xilinx.com 3 hups/www.digilentine.com 4 Digital Design Using Digilent FPGA Boards ~ VHDL / Active-HDI Edition; available from www. [bebooks.com.Introduction 5 Table 4.2 Board Jumper Settings CL BASYS Board Nexys-2 Board Sat the JPS jumper to JTAG Set the POWER SELECT jumper to USB Remove the JP4 jumper to select a 50 MAZ | Set the MODE jumper to JTAG clock VHDL. VHDL is based on the Ada software programming language but it is nor Ada nor is it a software programming language. VHDL is a hardware description language that is designed to model digital logic circuits. It simply has syntax similar to the Ada programming language but the way it behaves is different. In this book you will learn VEDL by studying the examples we use to describe digital logic and then doing some of the VHDL problems at the end of each chapter. In this book we begin by using the Active-HDL block diagram editor to draw logic circuits using basic gates. When you compile these block diagrams Active-HDL will generate the corresponding VHDL code. The block diagram representing your logic circuit can then be used as a module in a higher-level digital design. This higher-level design can then be compiled to produce its corresponding VHDL code. This hierachical block diagram editor will make it easy to design top-level designs. Sometimes it will be easier to design a digital module by writing a VHDL program directly rather than drawing it using gates. When you do this you can still use the block diagram for this module in higher-level designs. We will illustrate this process in many of our examples. Just like any programming language, you can only leam VHDL by actually writing VHDL programs and simulating the designs using a VHDL simulator that will display the waveforms of the signals in your design. This is a good way to learn not only VHDL but digital logic as well A companion book’ that uses Verilog instead of VHDL is available from wanv.digilentine.com or www.lbebooks.com. More comprehensive Verilog and VEDL books are also available.67 5 Introduetion to Digital Design Usign Digilent FPGA Boards — Block Diagran/Varilog Examples 6 Digital Design Using Digilent FPGA Boards — Verilog / Active-HDI. Edition, LBE Books, 2009. 7 Digital Design Using Digilent FPGA Boards ~ VHDL / Active-HDL Edition, LBE Books, 2009.6 Example 1 Example 1 Switches and LEDs In this example we will show the basic structure of a VHDL program and how to write logic equations for 2-input gates. Example 1a will show the simulation results using Aldec Active-HDL and Example Ib will show how to synthesize the program to a Xilinx FPGA on the BASYS or Nexys-2 board, Prerequisite knowledge: None Learned in this Example: Use of Aldec Active-HDL — Appendis 1.1 Slide Switches ‘The slide switches on the BASYS and Nexys-2 boards are connected to pins on the 3.3V FPGA through a resistor R as shown in Fig. 1.1. The value of R is 4.7 kQ on the BASYS board 4 Ry — swa and 10 kQ on the Nexys-2 board. When the slide switch is down it is connected to ground and the [ input sw(i) to the FPGA is read as a logic 0. * When the slide switch is up it is connected to 3.3 Figure 1.1. Slide switch connection V and the input sw(i) to the FPGA is read as a logic 1. There are eight slide switches on the BASYS and Nexys-2 boards. The eight pin numbers on the FPGA corresponding to the eight slide switches are given in a .ucf file. The file basys2.uef shown in Listing 1.1 defines the pin numbers for all I/O on the BASYS board. Note that we have named the slide switches sw(i), i = 0:7, which correspond to the switch labels on the board. We will always name the slide switches sw(i) in our top-level designs so that we can use the basys2.ucf file without change. Because the pin numbers on the Nexys-2 board are different from those on the BASYS board we will use a different file called nexys2.uef to define the pin numbers on the Nexys-2 board. The names of the I/O ports, however, will be the same for both boards. Therefore, all of the examples in this book can be used with either board by simply using the proper .uof file when implementing the design. Both of these .xcf files can be downloaded from www.]bebooks.com. 1.2 LEDs A light emitting diode (LED) emits light when current flows through it in the positive direction as shown in Fig. 1.2. Current flows through the LED when the voltage on the anode side (the wide side of the black triangle) is made higher than the voltage onSwitches and LEDs e the cathode side (the straight line connected to the apex of the black triangle). When current flows through a lighted LED the forward voltage across the LED is typically between +1.5 and +2.0 volts. If voltage 7? in Fig. 1.2 is less than or equal to voltage 7 then no current can flow through the LED and therefore no light will be emitted. If voltage /2 is greater than voltage M7 then current will flow through the resistor R and the LED. The resistor is used to limit the amount of current that flows through the LED. Typical currents needed to light LEDs range from 2 to 15 milliamps. Listing 1.1 basys2.ucf @ Pin assignment for LEDs MET "1de7>" Loc = "p2" ; NET "Ide6>" LOC = "p3" NET "Ides" Loc = "pa" NET "1de4>" LOC = "pS" NET "Ide3s" LOC = "p7" NET "1de2>" LOC = "pa" NET "Idel>" LOC = "pla" ; NET "Ide0>" LOC = "pis" ; # Pin assignment for slide switches NET "swe7>" LOC = "D6"; NET "awe6>" LOC = "plo"; NET "ewe5>" NET "swea>" NET "sue3o" NET "swe25" NET "swel>" LOC = "p36"; NET "sweO>" LOC ~ "p30"; # Pin assignment for pushbutton switches NET "btnc}>" "pals; NET "btn<2>" "paT"; NET "btnel>" wpaae, NET "bencd>" "pea"; # Pin assignment for 7-segment displays NET "a_to_ge6>" LOC NET "alto ge5>" LOC = NET "a_to_g<4>" LOC NET "ato g<3>" LOC NBT "a_to_g<2>" LOC = NET "ato gels" Loc NET "a_to_g<0>" LOC = "p NET "dp" Loc = "p22"; NET "anc3s" LOC = "past; NET “anc2>" LOC = "p32"; NET "ancl>" LOC = "p33"; NET "ancOs" LOC = "p34"; # Pin assignment for clock NET "nek" Loc = "p54";8 Exemple 1 There are two different ways that an I/O Noeaiet’ — oii pin of an FPGA can be used to turn on an LED. yp > vieve The first is to connect the FPGA pin to V2 in Fig. R is 1.2 and to connect M7 to ground. Bringing the pin (72) high will then turn on the LED. To turn off the LED the output pin would be brought low. a light ‘This is the method used for the LEDs la(7) - (0) . on the BASYS and Nexys-2 boards. va viva The second method is to connect the R LED FPGA pin to V2 in Fig. 1.2 and to connect 72 t0 Figure 1.2°Trtig can‘ LED a constant voltage. Bringing the pin (V1) low will then tum on the LED. To tum off the LED the output pin would be brought high. This voltage should be equal to V2 to make sure no current flows through the LED. This second method is the method used for the 7- segment displays on the BASYS and Nexys-2 boards. Examples 9 and 10 will show how to display hex digits on the 7-segment displays. 1.3 Connecting the Switches to the LEDs Part 1 of the tutorial in Appendix A shows how to connect the input switches to the output LEDs using the block “5 diagram editor (BDE) in Active-HDL. The result is shown in [~ 90S rns =a Fa naaceneae Figure 1.3 Connecting the eight switches to the eight LEDs‘Switches and LEDs 9 Compiling the file sw2led.bde generates the VHDL file sw2led.vhd shown in Listing 1.2. Alternatively, by selecting the hardware description editor (HDE) the ent and architecture declarations are automatically generated but you will need to write your own assignment statements. This can lead to the simpler VHDL program shown in (ing 1.3 where we can write a single assignment statement using the assignment operator, <=, to replace the two intermediate assignment statements in Listing 1.2. It is unnecessary to define the intermediate bus BUS23(7:0). isting 1.2 sw2led.vhd library IEEE; use TEEE.std_logic_1164.a12; entity sw2led is port ( ew : in STD_LOGIC_VECTOR(7 downto 0) ; 1d + out $TB_LOGIe_VECTOR(7 downto 0) ds end sw2led; architecture sw2led of sw2led is signal declarations used on the diagram -- eignal BUS23 : STD_LOGIC_VECTOR (7 downto 0); begin ‘Terminal assignment - -+ Inputs terminals BUS23 <= sw; -+ Output\buffer terminals 1d <= BUS23 end _su2led, Listing 1.3 sw2led2.vhd library 1: use IEEE.std logic 1164.a12; entity sw2led2 is port ( sw + in STD_LOGIC_VECTOR(7 downto 0); 1d : out STD_LOGIC_VECTOR(7 downto 0) iy end sw2led2; architecture ew2led2 of sv2led2 is begin10 Example 1 Note in the entity in Listing 1.3 that the input sw and the output /d are defined to be of type STD_LOGIC_VECTOR (7 downto 0). For simulation purposes this type is defined to have nine possible values. In addition to the usual 0 and | the other seven possible values are U (uninitialized), X (unknown), Z (high impedance). W (weak unknown), L (weak 0), H (weak 1), and (don’t care). In Parts 2 and 3 of the tutorial in Appendix A we show how to synthesize, implement, and download the design to the FPGA board. In summary, the steps you follow to implement a digital design on the BASYS or Nexys-2 board are the following: Create a new project and design name. Using the BDE create a logic diagram. Save and compile the .bde file, Optionally simulate the design (see Example 2). Synthesize the design selecting the Spartan3E family and the 3s100etql44 device for the BASYS board and the 3s5002f2320 device for the Nexys-2 board. 6. Implement the design using either basys2.ucf or nexys2.uef'as the custom constraint file. Check Allow Unmatched LOC Constraints under Translate and uncheck Do Not Run Bitgen under BitStream, Select JTAG Clock as the start-up clock under Startup Options. 7. Use ExPort to download the .bit file to the FPGA board. yeep At this point the switches are connected to the LEDs. Turning on a switch will light up the corresponding LED. Problem 1.1 The four pushbuttons on the BASYS and Nexys-2 boards are connected to pins on the FPGA using the circuit shown in Fig. 1.4. The value of B is 4.7 kO on the BASYS board and 10 kO on the Nexys-2 board. When the pushbutton is up the two resistors pull the input down to ground and the input bmn(i) to the FPGA is read asa logic 0. When the pushbutton is pressed the input is pulled up to 3.3 V and the input bmn(i) to the FPGA is read as a logic 1. Create a .bde file using Active-HDL that will connect the four pushbuttons to the rightmost four LEDs. Compile and implement the program. Download the bi file to the FPGA board and test it by pressing the pushbuttons. R 33 a btn(i) R Figure 1.4 Pushbutton connection2Input Gates "1 Example 2 2-Input Gates In this example we will design a circuit containing six different 2-input gates. Example 2a will show the simulation results using Aldec Active-HDL and Example 2b will show how to synthesize the program to a Xilinx FPGA on a Digilent board. Prerequisite knowledge: ‘Appendix C— Basic Logie Gates Appendix A — Use of Aldec Active-HDL 2.1 Generating the Design File gates2.bde Part 4 of the tutorial in Appendix A shows how to connect two inputs a and 6 to the inputs of six different gates using the block diagram editor (BDE) in Active-HDL. ‘The result is shown in Fig. 2.1. Note that we have named the outputs of the gates the name of the gate including an underscore. Identifier names in VHDL can contain any letter, digit, underscore _, or $. The identifier can not begin with a digit or be a VHDL keyword. VHDL is not case sensitive. The name of this file is gates2.4de. When you compile this file the VHDL program gates2.vhd shown in Listing 2.1 is generated. Figure 2.1 Circuit diagram for Example 212 Example 2 isting 2.1 gates2.vhd =~ Example 2a: gates2 library TEES; use IEEZ.std logic 1164.all; entity gates? is port ( a : in STD _Losrc; b : in STD_LOGIC; and_gate : out STD_LOGIC; nand_gate : out STD_LoctC; nor_gate : out STD LocIc; or_gate : out STD Locrc; xmor_gate : out STD_LOGIC; xor_gate : out STD_Locrc bi end gates2; architecture gates2 of gates2 is begin ---- Component instantiations and_gate <= b and a; nand_gate <= not(b and a); |——or-gate <= b or a; nor_gate <= not(b or a); xor_gate <= b xor a; mmor_gate <= not(b xor a); end _gates2; The logic diagram in Fig. 2.1 contains six different gates. This logic circuit is described by the VHDL program shown in Listing 2.1. The first line in Listing 2.1 is a comment. Comments in VHDL follow the double dash --. All VHDL programs begin with an entity statement containing the name of the entity (gates? in this case) followed by a list of all input and output signals together with their direction and type. We will generally use lower case names for signals. The direction of the input and output signals is given by the VHDL statements in, out, or inout (for a bi-directional signal), To describe the output of each gate in Fig. 2.1 we simply write the logic equation for that gate preceded by the assignment operator, <=. ‘These are concurrent assignment statements which means that the statements can be written in any order. 2.2 Simulating the Design gates2.bde Part 4 of the tutorial in Appendix A shows how to simulate this VHDL program using Active-HDL. The simulation produced in Appendix A is shown in Fig, 2.2. Note that the waveforms shown in Fig. 2.2 verify the truth tables for the six gates. Also note that two clock stimulators were used for the inputs a and b, By making the period of the clock stimulator for the input a twice the period of the clock stimulator for the input & all four combinations of the inputs a and 6 will be generated in one period of the input a.2-Input Gates, 13 Olivares Figure 2.2. Simulation of logic circuit in Fig. 2.4 2.3 Generating a Top-Level Design Part 5 of the tutorial in Appendix A shows how to create a top-level design for the gates2 circuit. In order to use the constraint files basys2.uef or nexys2.uef described in Example 1 we must name the switch inputs sw(j) and the LED outputs {d(i). This top- level design, as created in Part 5 of Appendix A is shown in Fig. 2.3. The module gates? in Fig. 2.3 contains the logic cireuit shown in Fig. 2.1. Note that each wire connected to a bus must be labeled to identify its connection to the bus lines. U1 sw(1:0) D—_sw(1) ld(S) ——D 1d(5:0)- Ja ja and gate} Swi) ib nand_gate| l(a = 143) ot gate ‘or_gats| We} Ida} smor_gate [4 xor_gete}» 200} gates2 Figure 2.3. Top-level design for Example 214 Example 2 Compiling the top-level design shown in Fig. 23 will generate the VHDL program shown in Listing 2.2. The inputs are now the two rightmost slide switches, sw(1:0), and the outputs are the six right-most LEDs /d(5:0). To associate these inputs and outputs with the inputs a and b and the six output in the gares? component in Fig. 2.1 and Listing 2.1 we use the VHDL port map statement Ul: gates2 port map( a => sw(1), b => sw(0), and_gate => 14(5), nand_gate => 14(4), nor_gate => 1d(3), or_gate => 1d(2), mndr_gate => 1a(1), xor_gate => 14(0) 19 2.2 gates2_top.vhd Example 2b: gates2_top library TEE; use IEEE. std logic 1164.a11; library EKAMPLE2; entity gates2_top is port ( ew ld: in STD_LOGIC_VECTOR(1 downto 0); out STD_LOGIC_VECTOR(S downto 0) y; end gates2_top; architecture gates? top of gates? top is component gates? port ( a: in std_logic; and_gate : out std_logic; b : in std_logic; nand_gate + out std_logic; nor_gate : out std_logic; ox_gate : out std logic; wnbr_gate : out std_logic; xor_gate : out std logic ; end component; begin UL: gates2 port map( a => sw), b => sw(0), and_gate => 14(5), nand_gate => 14(4), nor_gate => 14(3), ox_gate => 14(2), 1a), 14(0)2-Input Gates 15 This VHDL port map statement begins with an arbitrary name for the component in the top-level design. Here we call it Ul. This is followed by the name of the ‘component being instantiated, in this case gates? from Listing 2.1. Then using the port map statement enclosed in parentheses are the inputs and outputs from Listing 2.1 associated with corresponding inputs and outputs in the top-level design in Fig. 2.3. Note that we connect the input a in Listing 2.1 to the input sw(1) on the FPGA board. The input b in Listing 2.1 is connected to sw(0) and the outputs and_gate, nand_gate, or_gate, nor_gate, xor_gate, and xnor_gate are connected to the corresponding LED outputs /d{5:0). ‘These associations can be made in this way in any order. The port map statement in Listing 2.2 generated from the top-level block diagram are associated in alphabetical order. Follow the steps in the tutorial in Appendix A and implement this design on the FPGA board. Note that when you change the settings of the two right-most slide switches the LEDs will indicate the outputs of the six gates.6 Example 3 Example 3 Multiple-Input Gates In this example we will design a circuit containing multiple-input gates. We will create a logic circuit containing 4-input AND, OR, and XOR gates. We will leave it as a problem for you to create a logic circuit containing 4-input NAND, NOR, and XNOR gates. Prerequisite knowledge: Appendix C — Basic Logic Gates Appendix A — Use of Aldec Active-HDL 3.1 Behavior of Multiple-Input Gates The AND, OR, NAND, NOR, XOR, and XNOR gates we i». studied in Example | had two inputs. The basic definitions hold *2—] for multiple inputs. A multiple-input AND gate is shown in Fig. "| 3.1. The output of an AND gate is HIGH only if all inputs ar HIGH. To describe this multiple-input AND gate in VHDL we Figure 3.1 could simply write the logie equation as ‘Mulipie-input AND gate, z= x(1) and x(2) and ... and x(n); x0 A multiple-input OR gate is shown in Fig. 3.2, The “= z output of an OR gate is LOW only if all inputs are LOW. Just »07 As with the AND gate we can write the logic equation as Figure 3.2 z <= x(1) or x(2) or or x(n); Maole input OR ote. A multiple-input NAND gate is shown in Fig. 3.3. «nf The_output of a NAND gate is LOW only if all inputs are *2—) yyy yp —2 HIGH. We can write the logic equation as : xo— 2 <= not(x(1) and x(2) and and x(a); Figure 3.3 Multiple-input NAND gate. A multiple-input NOR gate is shown in Fig. 3. output of a NOR gate is HIGH only ifall inputs are LOW. can write the logic equation as 7g ce mot(x(a) oF 12) OF ... oF x(n Figure 3.4 = == (Ne Muttipie-input NORMuttiple-Input Gates 7 A multiple-input XOR gate is shown in Fig. so — What is the meaning of this multiple-input gate? Following x2) 2 the methods we used for the previous multiple-input gates we —J can write the logic equation as TT Figure 3.5 2 <= x(1) xor x(2) Kor... mor x(n); Multiple-input XOR gate. We will create a 4-input XOR gate in this example to determine its meaning but first consider the multiple-input XNOR gate shown in Fig. 3.6. What is the meaning of this multiple-input gate? (See Problem 3.1 at the end of this example for the answer.) Following the methods we used for the previous multiple-input gates we ean write the logic equation as Figure 3.6 ‘Multiple-input XNOR gate. 2 ex not(x(2) xor x(2) tor... xor x(n)); or we can use the following gate instantiation statement for an XNOR gate. z <= x(1) xno x(2) xnor ... xnor x(n); 3.2 Generating the Design File gates4.bde Use the block diagram editor (BDE) in Active-HDL to create the logic circuit called gares4.bde shown in Fig. 3.7. A simulation of this circuit is shown in Fig. 3.8. From this simulation we see that he output of an XOR gate is HIGH only if the number o us is ODD. x3:0) D143) QS AB andd_gate Figure 3.7 Block diagram for gates4.bde18 Example 3 If you look at the file gates4.vhd that is generated when you compile gates4.bde you will see that Active-HDL defines separate components for the 4-input AND, OR, and XOR gates and then uses a VHDL instantiation and port map statement to "wire" them together. Alternatively, we could use the HDE editor to write the simpler VHDL program called gates4.vhd shown in Listing 3.1 that uses standard VHDL logical operators to implement the three 4-input gates. This VHDL program will produce the same simulation as shown in Fig. 3.8. Figure 3.8 Simulation of the design gates4.bde shown in Fig. 3.7 Listing 3.1: gates4b.vhd =-Example 3: 4-input gates library IEEE; use IEEE.STD LOGIC _1164.a11; entity gatesab is port ( x : dn STD_LOGTC_VECTOR(4 downto 1); and4_gate out STD_LOGIC; or4_gate : out STD_LOGIC; xord_gate : out STD_LOGIC de end gatesb; architecture gatesdb of gatesb is begin and4_gate <= x(1) and x(2) and x(3) and x(4); or4_gate (2) oF x(2) or x(3) or x(4); xord_gate <= x(1) nor x(2) xnor x(3) xnor x(4); end gates;Multiple-Input Gates 19 3.3 Generating the Top-Level Design gates4_top.bde Fig. 3.9 shows the block diagram of the top-level design gates4_top.bde. The module gares4 shown in Fig. 3.9 contains the logic circuit shown in Fig. 3.4. If you compile gates4 top.bde the VHDL program gates4_top shown in Listing 3.2 will be generated. Compile, synthesize, implement, and download this design to the FPGA board. ut a 1d(2:0) sw(3:0) D> asia) ends_gate[»—22) rat) ext, gte] 20 ord _gute}> 00} gates4 Figure 3.9 Block diagram for the top-level design gates4_top.bde Lis . [Example 2; 4-input gates - top level Library IEEE; use IEEE. std logic 1164.11; Library EXAMPLES; entity gates4_top is port ( sw: in atd_logic_vector (2 downto 0); 3d: out STD_LOGIG VECTOR(2 downto 0) end gates4_top; architecture gates_top of gates4_top is component gates port xt in std_logic vector(2 downto 0); anag_gate 7 out std logic: ort_gate + out ota logic; Sori. gate ; owt std_togic Vi end component; begin Ul : gatesé port map( andé_gate => 14(2), or4_gate => 14(1), xoré_gate => 14(0) i end gates¢_top;20 Example 3 Problem 3.1 Use the BDE to create a logic circuit containing 4-input NAND, NOR, and XNOR gates. Simulate your design and verify that the output of an NNOR gate is HIGH only if the number of HIGH inputs is EVEN. Create a top-level design that connects the four inputs to the rightmost four slide switches and the three outputs to the three rightmost LEDs. Implement your design and download it to the FPGA board, 3.2 The circuit shown at the right is for a 2 x 4 decoder. x x0 Use the BDE to create this circuit and simulate it -—+ —$ using Active-HDL. Choose a counter stimulator for | \7. | V x(1:0) that counts every 20 ns, set en to a forced if ==— value of 1, and simulate it for 100 ns. Make a truth poe table with (x(1), x(0)) as the inputs and y(0:3) as the — | outputs. What is the behavior of this decoder? TeEquality Detector a Example 4 Equality Detector In this example we will design a 2-bit equality detector using two NAND gates and an AND gate. Prerequisite knowledge: ‘Appendix C— Basic Logic Gates Appendix A ~ Use of Aldec Active-HDL 4.1 Generating the Design File eqdet2.bde ‘The truth table for a 2-input XNOR gate is shown in Fig. 4.1. Note that the output z is 1 when the inputs x and y are equal. ‘Thus, the XNOR gate can be used as @ 1- bit equality detector. Figure 4.1 The XNOR gate is a 1-bit equality detector By using two XNOR gates and an AND gate we can design a 2-bit equali detector as shown in Fig, 4.2. Use the BDE to create the file eqder2.hde using Active- HDL. — sit) 0) a: bi) pao) 80) Figure 4.2. Block diagram of a 2-bit equality detector, eqdet2.bde22 Example 4 If you compile the file eqder2.bde Active-HDL will generate the VHDL program eqdei2.vha shown in Listing 4.1. A simulation of egder2.bde is shown in Fig. 4.3. Note that the output eq is 1 only if (1:0) is equal to B(1:0).. Listing 4.1: eqdet2.vhd =~ Title + eqder2, library IEEE; use IEEE.std logic 1164.a11; entity eqdet2 is port ( a : dn STD_LOGIC_VECTOR(1 downto 0); b : in STD_LOGIC_VECTOR(1 downto 0); eq : out STD_LocTC de end eadet2; architecture eqdet2 of eqdet? is signal eqi : STD_LOGIC; signal eq2 : STD_LOGIC; begin eq eq ea jot (b(1) or a(1)); jot (b(0) xor a(0)); eq2 and eal; end eqdet2; ie Edt Search View Workspace Design Simulation Waveform Tools Window Bios[kQtmleagagiae vae[Snae [eww we Figure 4.3 Simulation ofthe 2-bit equality detector, eqdet2.bde Create a top-level design called egder2_top.bde that connects a(1:0) and B(1:0) to the rightmost four slide switches and connects the output eq to /d(0). Implement your design and download it to the FPGA board.2.to-1 Multiplexer: i7Statement 23 Example 5 : if Statement 2-to-1 Multiplexe In this example we will show how to design a 2-to-1 multiplexer and will introduce the VHDL i statement. Section 5.1 will define a multiplexer and derive the logic equations for a 2-to-1 multiplexer. Section 5.2 will illustrate the use of two versions of the VHDL statement. Prerequisite knowledge: Karnaugh Maps ~ Appendix D Use of Aldee Active-HDL — Appendix A 5.1 Multiplexers An rinput multiplexer (called a MUX) is an n-way digital switch that switches one of 7 inputs to the output, A 2-input multiplexer is shown in Fig. 5.1. The switch is controlled by the single control line s. This bit selects one of the two inputs to be "connected" to the output. This means that the logical value of the output y will be the same as the logical value of the selected input. From the truth table in Fig. 5.1 we see that y=a if s=0 and y=bif's=1. The Kamaugh map for the truth table in Fig. 3.1 is shown in Fig. 3.2. We see that the logic equation for y is — y= -sea|sab jn Note that this logic equation describes the sably circuit diagram shown in Fig. 5.3. 0-0 0| 0 | aoijo 4 o1o0fi muxf—?Y o1ala b—>| 100]o aoaja f 11o0]o 5 aaala Figure 6.1. A 2-to-1 multiplexer y=-s&a[s&b Figure 5.2 K-map fora 2-0-1 multiplexer24 Example 5 Use the BDE to create the block diagram mux2/.bde shown in Fig. 5.3 that implements logic equation (5.1). Compiling muc2/.bde will generate a VHDL file, mux21.vhd, that is equivalent to Listing 5.1. A simulation of mx2].bde is shown in Fig. 5.4, Note in the simulation that y = a if s = 0 and y = 6 if. library TEI use IEEE.std_logic_1164.al1; entity mux21 is port ( a: in STD_tocrc; b : in STD_LOGIC; 8 : in STD_LOGIC; y + out STD LoGre a; end mux21; architecture mux2i of mux2l is signal aout : STD_LOGIC; ignal bout : STD_LOGIC; signal nots : STD_LOSIC; begin aout <= nots and a; bout <- 6 and b; nots <= not(s); y <= bout or aout; end mux2t;240-1 Multiplexer ifStatement 25 Ble Edt Search View Workspace Design Simulation Waveform Tools Window |Help « [eas Seliooi;asnlaga” 20 Figure 5.4. Simulation of the 2-1o-1 MUX in Fig. 6.3, 5.2 The VHDL if statement ‘The behavior of the 2 x 1 multiplexer shown in Fig. 5.1 can be described by the VHDL statements We saw that the assignment statements in VHDL using the assignment operator <= are concurrent and execute in parallel. On the other hand the if statement is an xample of a procedural, or sequential, statement. Procedural statements must be contained within a process and are executed in the order that they appear in the code. ‘Thus, the VHDL if statement must be contained in a process as shown in Listing 5.2. The process begins with the statement slabel>: process ( —J BS. & aa 2 om Figure 6.1 The quad 2-to-1 MUX, mux24.bde, contains four 2-40-1 MUXs28 Example 6 Ifyou compile the file mux24.bde Active-HDL will generate the VHDL program mec24.vhd shown in Listing 6.1. A simulation of nnex24.bde is shown in Fig. 6.2. Note that the output y(3:0) will be either a(3:0) or (3:0) depending on the value of s. Listing 6.1_ Example6a.vhd =- Example 6a: mux24 library IEEE; use IEEE.std logic 1164.a11; library EXAMPLEG; entity mux24 is port ( s : in std_logic; a + in STD LOGIC VECTOR(3 downto 9); b : in STD_LOGIC_VECTOR(3 downto 0); Yy + out STD_LOGTC_VECTOR(3 downto 0) ly end mux24; architecture mux24 of mux24 is component mux21 port ( a : in sté_toaie; b: in std_logic: 3 : in stdvlogic; ¥ 1 out std_logic i end component; begin un: maxza port map( a => a(3), b => b(3), 6 => 6, y => y(3) ) U2: mux21 port map( a => a(2), b => b(2), 6 => 8, y => ¥(2) i U3 + mux22 port map ( a=> a(1), b=> bt), § y= ya) de Ua: mux21 port map( a => a(0), b => b(0), 5 => 8, y => y(0)Quad 2-to-1 Multiplexer 29 Figure 6.2. Simulation of the quad 2-to-1 MUX in Fig. 6.1 Use the BDE to create the top-level design called mux2/_top.bde shown in Fig. 6.3. Note that a(3:0) are connected to the four leftmost slide switches, 6(3:0) are connected to the rightmost four slide switches, and (3:0) are connected to the four rightmost LEDs. Also note that s is connected to di(0), and the input hfn(0:0) must be declared as a std_logie_vector, even though there is only one element, so that we can use the constraint file basys2.uef or nexys2.uef without change. Implement your design and download it to the FPGA board. ‘Test the operation of the quad 2-to-1 multiplexer by setting the switeh values and pressing pushbutton bin(0). Ifyou compile the file mux24_top.bde Active-HDL will generate the VHDL program mec24_top.vhd shown in Listing 6.2. A simulation of mux24_top.bde is shown in Fig. 64, potas: Figure 6.3 Top-level design for testing the quad 2-to-1 MUX Listing 6.2 Exampleéb.vhd =- Example 6b: mux24_top library TEEE; use ZEEE.std logic _i164.al1; Library EXAMPLES; entity mux24_top is port ( btn : in STD_LOGIC VECTOR(O downto 0 sw: in std_logic vector(7 downto 0) 1d : out std_logic_vector(3 downto 0) dy end mux24_top;30 Example 6 ‘architecture mux24 top of mux2é top is component mux24 : in std logic vector (3 downte 0); : in std logic vector(3 downto 0); : in sta_logic; : out std_legic_vector(3 downto 0) d; end component; begin UL: mux24 port map( a(0) => ew(4), a(t) => aw(5), a(2) => sw(6),. a(3) => sw(7), (0) => sw(0), b(1) => sw(1), (2) => sw(2), b(3) => sw(3), 8 => btn(0), y= ld dM: end mux24_top; (Be EG Seach vow Worlapace Desgn Swuston Wavelom Toole Qawaagg” Leelee. Figure 6.4 Simulation of mux24_top.bde in Fig. 6.1 6.2 A Quad 2-to-1 Multiplexer Using an if Statement In Listing 5.2 of Example 5 we used a VHDL if statement to implement a 2-10-1 MUX. Listing 6.3 is a direct extension of Listing 5.2 where now the inputs and outputs, are 4-bit values rather that a single bit. The VHDL program shown in Listing 6.3 will produce the same simulation as shown in Fig. 6.2. The module mex24b defined by the VHDL program in Listing 6.3 could be used in place of the mux24 module in the top- level design in Fig. 6.3Quad 240-1 Multiplexer 34 Listing 6.3 mux24b.vhd ~-Example 6c: Quad 2-to-i MUX using If statement library TEEE; use IEEE.STD LOGIC _1164.al2; entity mux24b te port ( a: in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIG_VECTOR(3 downto 0); 8 : dn STD_LoGT ¥ + eut STD_LOGIC_VECTOR(3 downte 0) end mux24b; architecture mux24b of mux24b ie signal s4: STD LOGIC VECTOR(3 downto 0); begin pl: process (2, b, s) begin ifs end if; end process; end mux24b; 6.3 Generic Multiplexers: Parameters We can use the VHDL generic statement to design a generic 2-to-1 multiplexer with input and output bus widths of arbitrary size. Listing 6.4 shows a VHDL program for a generic 2-to-1 MUX. Note the use of the generic statement that defines the bus width to have a default value of 4. This value can be overridden when the multiplexer is instantiated as shown in Listing 6.5 for an 8-line 2-to-1 multiplexer called MS. The parameter override clause is automatically included in the port map statement when you copy it in Active- HDL as shown in Listing 6.5. We will always use upper-case names for parameters. The simulation of Listing 6.5 is shown in Fig. 6.5. If you compile the VHDL program muec2g.vhd shown in Listing 6.4 it will generate a block diagram for this module when you go to BDE. If you right-click on the symbol for mu2g and select Properties, you can change the default value of the parameter V by selecting the Parameters tab and entering an actual value for N.32 Example 6 Listing 6.4 mux2g.vhd =- Example 6d: Generic 2-to-1 MUX using @ parameter Library TESE; use IESE.STD LOGIC 1164.a11; entity mx2g ie neric(N:integer := 4); Port ( a + dn STD_LOGIC_VECTOR(N-1 downto 0); b : 4n STD LOGIC VECTOR (N-1 downto 0); s : in STD_LOGIC; y + out STD_LOGIC_VECTOR(N-1 downto 0) Me end mux2g: architecture mux2g of muxdg is begin pl: process (a, b, s) begin ifs = '0' then yor ar = else y <= br end if; end process; end mux2g; Listing 6.5 mux28.vhd =-Example 6e: 6-line 2-to-1 MUX using a parameter library IEEE; use IEBE.STD LOGIC _1164.a11; entity mux28 is port ( in STD_LOGIC_VECTOR(7 downto 0); in STD_LOGIC VECTOR(7 downto 0); in STD_LOGIC; + out STD LOGIC VECTOR(7 downto 0) ope Li end mux28; architecture mux28 of mux28 ie component mux2g is generic(N: positive := 4 port ( in STD_LOGIC_VECTOR(N-1 downto 0) iin STD_LOGIC_VECTOR(N-1 downto 0); in STD_LOGIC; out STD_LOGIC_VECTOR(N-1 downto 0) soon ‘end component;Quad 240-1 Multiplexer 33 Listing 6.5 (cont) mux28.vhd begin MS: mux2g generic map(N => 8) port map end mux26; Fie Edt Scorch View Workspace Design Simulation Waveform ods Whdow Heb « [eal Peel sira=negaelaunam” Name _[Velie[Simuictor [+ 20) 40 1 @ + @ 0 os Ws ORO TF Figure 6.5 Simulation result from the VHDL program in Listing 6.534 Example 7 Example 7 4-to-1 Multiplexer In this example we will show how to design a 4-t0-1 multiplexer. In Section 7.1 we will make a 4-to-1 multiplexer by witing together three of the 2-to-1 multiplexers that we designed in Example 5. In Section 7.2 we will derive the logic equation for a 4-t0-] MUX. In Section 7.3 we will show how a 4-to-1 multiplexer can be designed using a single VHDL case statement and in Section 7.4 we design a quad 4-to-1 multiplexer. Prerequisite knowledge: _ Example 5 —2-to-1 Multiplexer 7.1 Designing a 4-to-1 MUX Using 2-to-1 Modules A 4-to-1 multiplexer has the truth table shown in Fig. 7.1 By using three instances of the 2-to-1 MUX, mux2J.bde, that we designed in Example 5, we can design a 4-to-1 multiplexer as shown in Fig. 7.2. Use the BDE to create the file muacd/.bde using Active-HDL. Note that you will need to add the file mucc2].bde to your project. In Fig. 7.2 when s(1) =0 itis v, the output of U2 Figure 7.1 that gets through to z. If s(0) = 0 in U2 then it is c(0) ‘Truth table for a. 4-to-1 MUX that gets through to v and therefore to z. If s(0) = 1 in U2 then itis e(1) that gets through to v and therefore to z. a uz 00 v, b=>™, 5 => 8(1), ) 2: mux2i port map( a => ¢(0), b=> c(t), § => 8(0), y =v ) us: mux22 port map( a => ¢(2), b => ¢(3), 5 => 5(0), y => ) end muxdia;36 Example 7 Tule elon ak Wan ep z t aQalan feria tay Now (Vee |Sieer | Oe we eee 't eayte, a ec] ithayCo.@ eee a ee eee Oe ee ee ee Figure 7.3 Simulation of the VHDL program in Listing 7.1 If you were going to create this top-level design using HDE instead of BDE you would begin by defining the inputs c(3:0) and s(1:0) and the output z and the two signals vand w. You would then “wire” the three components together using the three port map statements shown in Listing 7.1. “The easiest way to generate this port map statement is to first compile the file mux27.vhd from Example 5 using Active-HDL, expand the library icon (click the plus sign), right click on »uec2/, and select Copy VHDL Instantiation as shown in Fig. 74. Paste this into your top-level mux-4J.vhd file. per e Fa cs Bom,4-t0-1 Multiplexer a7 At this point you would have the statement Label : mux21 Ort map( 2 s ¥y de Make three copies of this prototype and change the name of Label! to U1, U2, and U3 in the three statements. Now you just “wire up” each input and output variable by changing the values in the parentheses to the signal that it is connected to. For example, the mux U1 input a is connected to the wire v so we would writes => v. Ina similar way the mux input 6 is connected to wire w and the mux input s is connected to input s(1). The mux output y is connected to the output z in Fig. 7.2. Thus, the final version of this port map statement would be UL + mux2i port map( b s ¥ The other two modules, U2 and U lar port map statements. 7.2 The Logic Equation for a 4-to-1 MUX The 4-to-] MUX designed in Fig. 7.2 can be represented by the logic symbol shown in Fig. 7.5. This multiplexer acts like a digital switch in which one of the inputs (3:0) gets connected to the output z. The switch is controlled by the two control lines (1:0). The two bits on these control lines select one of the four inputs to be "connected" to the output, Note that we constructed this 4-to-1 multiplexer using three 2-to-1 multiplexers in a tree fashion as shown in Fig-7.2: Ut leo fe a) “yatta. + Figure 7.5 A 4-to-1 multiplexer38 Example 7 Recall from Eq. (5.1) in Example 5 that the logic equation for a 2-to-1 MUX is given by ys -sea|sebd (nay Applying this equation to the three 2-o-1 MUXs in Fig. 7.2 we can write the equations for that 4 x 1 MUX as follows. ve -s0 cd | 80 & cl w= -s0 @c2 | 50 & 3 z= -slev| slew 2 2-91 & (-s0 @ cO | 50 ect) | 81 & (~s0 & c2 | 50 & C3) or, z= si & -60 6 co ] “21 2 so ger (7.2) | 51 & -s0 & 2 | sie soees Equation (7.2) for 2 also follows from the truth table in Fig. 7.1. Note that the tree structure in Fig. 7.2 can be expanded to implement an 8-to-1 multiplexer and a 16-10 1 multiplexer. ‘A VHDL program that implements a 4-to-1 MUX using the logic equation (7.2) is given in Listing 7.2. A simulation of this program will produce the same result as in Fig. 7.3 (without the wire signals v and w).. Listing 7.2 mux4tb.vhd =- Example 7b: 4-to-l MUX using logic equation library IEEE; use IEEE.STD_LOGIC_1164.a11; entity muxdib is port ( ¢ + in STD_LOGTC_VECTOR(3 downto 0); 8 + dn STD_LOGIC_VECTOR(1 downto 0): + out STB_LOGIG Ye end muxtib; architecture muxtib of mux begin 2 <= (not 5(1) and not s(0) and c(0)) or (not 5(1) and = s(0) and c(1)) or ( s(i) and not s(0) and c(2)) or ( s(2) and 8(0) and o(3)); end muxét4440-1 Multiplexer 39 7.3 4-to-1 Multiplexer: case Statement The same 4-to-1 multiplexer defined by the VHDL program in Listing 7.2 can be implemented using a VHDL case statement. The VHDL program shown in Listing 7.3 does this. The case statement in Listing 7.3 directly implements the definition of a 4-t0-1 MUX given by the truth table in Fig. 7.1. The case statement is an example of a procedural statement that must be within a process. A typical line in the case statement, such as when "10" => 2 <= ¢(2); will assign the value of c(2) to the output z when the input value s(1:0) is equal to 2 (binary 10). In the case statement the value following the when statement represents the value of the case parameter, in this case the 2-bit input s. These values are the same as the case parameter type by default, in this case STD_LOGIC_VECTOR(I:0). If you want to write @ hex value you precede the number with X’as in "A" which is a hex value A. However, hex values are in multiples of 4 bits, therefore "A" represents a binary 1910. Since s is only 2 bits, we can’t use the hex notation because the bus sizes would not match, Listing 7.3 muxéte.vhd =- Example 7c: 4-to-1 MUX using case statement library IEEE; use IEEE.STD_LOGIC_1164.211; entity muxéic is port ( in STD_LOGIC_VECTOR(3 downto 0); in STD_LOGIC_VECTOR(1 downto 0); 2 2 out STD_LOGIC end muxdic; architecture muxtic of muxdic is begin pl: process(c, s) begin case s is when "00" => z <= c(0); when "01" => 2 <= ¢(2); when "10" => z <= ¢(2); when "Li" => 2 <= o(3); when others => z <= c(0); end case; end process; end muxéic;40 Example 7 Alll case statements should include a when others line as shown in Listing 7.3. This is because all cases need to be covered and while it looks as if we covered all cases in Listing 7.3, recall that VHDL actually defines nine possible values for each bit of type STD_LOGIC_VECTOR. A simulation of the program in Listing 7.3 will produce the same result as in Fig. 7.3 (without the wire signals v and w). 7.4 A Quad 4-to-1 Multiplexer To make a quad 4-t0-1 multiplexer we could combine four 4-to-1 MUXs as we did for a quad 2-to-1 multiplexer module in Fig. 6.1 of Example 6. However, it will be easier to modify the case statement program in Listing 7.3 to make a quad 4-to-1 MUX. Because we will use it in Example 10 we will define a single 16-bit input x(15:0) and we will multiplex the four hex digits making up this 16-bit value. Listing 7.4 is a VHDL program for this quad 4-to-1 multiplexer. Note that the four hex digits making up the 16-bit value of x(15:0) are multiplexed to the output 2(3:0) depending of the value of the control signal s(1:0). A simulation of this quad 4-to-1 multiplexer is shown in Fig, 7.6 and its BDE symbol is shown in Fig. 7.7. Listing 7.4 muxdd.vhd = Example 7d: quad ¢-to-l MUX library IEEE; use-TEEE-STD_LOGIC_1154.al1; entity muxad is port ( x 1 in STD_LOGIC_VECTOR(1S downto 0); § : 4n STD_LOGIC_VECTOR(1 downto 0); Z : out STD_LOGIG VECTOR (3 downto 0) oe end maxed; architecture muxéé of muxia is begin ‘pl: process (x, s) begin when "00 <= x(3 downto 0); when "01" (7 downto 4); when "10" x(11 downto 8); when "11 <= x(15 downto 12); when others => z <= x(3 downto 0); end case; end process; end mudd;4-t0-1 Multiplexer fs Edt Search View Workspace Design Simulation Waveform Tools « 7% [RAS we QQ e&/ wu” Figure 7.7 A quad 4-to-t multiplexer 4a42 Example 8 Example 8 Clocks and Counters The Nexys-2 board has an onboard 50 MHz clock. The BASYS board has a jumper that allows you to set the clock to 100 MHz, 50 MHz, or 25 MHz. Alll of the examples in this book will assume an input clock frequency of 30 MHz. If you are using the BASYS board you should remove the clock jumper, which will set the clock frequency to 50 MHz. This 50 MHz clock signal is a square wave with a period of 20 ns. The FPGA pin associated with this clock signal is defined in the constraints file basys2.uef or nexys2.uef with the name melk. In this example we will show how to design an N-bit counter in VHDL artd how to use a counter to generate clock signals of lower frequencies. Prerequisite knowledge: Appendix A — Use of Aldec Active-HDL 8.1 N-Bit Counter The BDE symbol for an N-bit counter is shown in Fig. 8.1. If the input clr = 1 then all V of the outputs q(i) are cleared to zero asynchronously, i.e., regardless of the value of the input cl. If clr 0, then on the next rising edge of the clock input clk the N- bit binary output q(WV-1:0) will be incremented by 1. That is, on the rising edge of the clock the N-bit binary output _g(N-1:0) will count from 0 to N-1 and then wrap around to 0. Ut fell git:0) counter Figure 8.1 An A-bit counter ‘The VHDL program shown in Listing 8.1 was used to generate the symbol shown in Fig. 8.1. Note that the sensitivity list of the process contains the signals clk and clr. This means that the if statement within the process will execute whenever either clr or elk goes high. If clr goes high then the output q(N-1:0) will go to zero, The statement count <= (others => '0'); sets all bits of count(V-1:0) to zero. The phrase clk'event and clk =Clocks and Counters 43, in the elsif clause in Listing 8.1 means that there was an event on the signal elf, ie., it changed value and it ended up at 1. That is, there was a rising edge of the clock. Thus, if clr = 0 and there is a rising edge of the clock signal clk then the output g(N=1:0) will be incremented by 1. Note that count(V-1:0) is defined to be a signal in Listing 8.1. This is necessary because the output ¢ can not be read and therefore you can nor use a statement such as acaqtl in Listing 8.1. Rather you must increment the signal cowni(N-1:0) within the process in Listing 8.1 and then assign the output q to count outside the process. Listing 8.1 counter.vhd =- Example Sa: N-bit counter library TEBE; use IEEE.STD_LOGIC_1164.all; use ISEE.STD_LOGIC_unsigned.all; entity counter is generic(N : integer := 8); port ( clr : in sTD_Locrc; clk : in STD_LOGIG; @ + owt STD LOGIC _VECTOR(N-1 downto 0) dy end counter; architecture counter of counter signal count: STD_LOGIC_VECTOR(N-1 downto 0); begin process (clk, clr) begin if cle = '1' then count <= (others => '0'); elsif clk'event and clk = '1' then count <= count + 1; end if; end process; @ <= count; end counter ‘The default value of the parameter N’in Listing 8.1 is 4. A simulation of this 4-bit counter is shown in Fig. 8.2. Note that this counter counts from 0 to F and then wraps around to 0. To instantiate an 8-bit counter from Listing 8.1 that would count from 0 — 255 (or 00 — FF hex) you would use an instantiation statement something like cutis : counter N jeneric map( ) port map ( clr => clr, clk => clk, q => ¢ de44 Example 8 You can also set the value of the parameter V from the block diagram editor (BDE) by right-clicking on the symbol in Fig. 8.1 and selecting Properties and then the Parameters tab. Note in Listing 8.1 that we have included the additional use statement use IEEE. STD_LOGIC_unsigned.all; This statement will include the library file unsigned.vhd in the project. This is required in order to use the + sign to implement the counter by adding 1 to the signal count. fie Edt Search View Worlspace Design Simulation Waveform cols Window a HRA mW eQQg wu 1 1 WO Os as a0 Figure 8.2. Simulation of a 4-bit counter using Listing 8.1 In the simulation in Fig. 8.2 note that the output g(0) is a square wave at half the frequency of the input clA. Similarly, the output q(1) is a square wave at half the frequency of the input q(0), the output 4(2) is a square wave at half the frequency of the input g(1), and the output g(3) is a square wave at half the frequency of the input 4(2). Note how the binary numbers q(3:0) in Fig. 8.2 count from 0000 to 1111. ‘The simulation shown in Fig. 8.2 shows how we can obtain a lower clock frequency by simply using one of the outputs 4(i). We will use this feature to produce a 24-bit clock divider in the next section. 8.2 Clock Divider The simulation in Fig. 8.2 shows that the outputs q(i) of a counter are square waves where the output 4(0) has a frequency half of the clock frequency, the output q(1) has a frequency half of q(0), ete. Thus, a counter can be used to divide the frequency fof a clock, where the frequency of the output q(f) is f= /2"'. The frequencies and periods of the outputs of a 24-bit counter driven by a 50 MHz clock are shown in Table 8.1. Note in Table 8.1 that the output q(0) has a frequency of 25 MHz, the output q(17) has a frequency of 190.73 Hz, and the output (23) has a frequeney of 2.98 Hz.Clocks and Counters 45 Table 8.1. Clock divide frequencies ‘ii)_ | Frequency (Hz) | Period (ms) i s0900000.00 0.00002 ‘o|25000000.00 | 0.00004 4 | 12500000.00 | 0.00008 2{ 6250000.00| 0.00016 3 3125000.00| 0.00032 4[_1562500.00| 0.00064 5 781250.00 | 0.00128 6 '390625.00 | 0.00256 7 19531250 | _0.00512 8 97656.25| 0.01024 8 48828.13 | 0.02048 40 2441405 | _ 0.04096 rT 1207.03 | 0.08192 12 6103.52 0.16384 13 3051.76 | 0.32768, 14 1525.88 | _ 0.65535, 16 762.94 | 1.31072 16 aeia7 | 2.62144 17 190.73 | 6.24288 18 95.37 | 10.48576 19 47.68 | _20.97152 20 23.84 | 41.94304 24 44.92] 63.88608 22 5.96 | 167.7216 23 2.98 | 335.54432 The VHDL program shown in Listing 8.2 is a 24-bit counter that has three outputs, a 25 MHz clock (cl425), a 190 Hz clock (clk190), and a 3 Hz clock (cik3). You can modify this efkdiv module to produce any output frequeney given in Table 8.1. We will use such a clock divider module in many of our top-level designs. Listing 8.2 clkdiv.vhd =- Example @b: clock divi library IEEE; use TEEZ.STD_LOGIC_1164.a11; use IEEE.STD_LOGIC _unsigned.all; entity clkdiv is port ( melk : in STD_LOGIC; clr : in STD _Loaic; c1k190 : out STD_LOGIC; elkaa : out s7D_Locic % end clkdiv;46 Example 6 Listing 8.2 (cont) clkdiv.vhd architecture clkdiv of clkdiv is signal q:STD_LOGIC_VECTOR(23 downto 0); begin =- clock divider process (mclk, clz) begin if clr = ‘1! then q <= x"000000"; elsif mclk'event and mclk = '1' then aqeg+l; end if; end process; clkas c1k190 «: end clkdiv; 48 He 190 Hz (20); (18); Note in Listing 8.2 that we define the internal signal q(23:0). The BDE symbol generated by compiling Listing 8.2 is shown in Fig. 8.3. You can edit either Listing 8.2 or the block diagram shown in Fig. 8.3 to bring out only the clock frequencies-you need ina particular design. For example, the top-level design shown in Fig. 8.4 will cause the eight LEDs on the FPGA board to count in binary at a rate of about three counts per second. The corresponding top-level VHDL program is shown in Listing 8.3. U1 — }melk elk > fer elkt90)> tka clkdiv Figure 8.3 A clock divider Ut u2 olka vin a «(v4.0 Dp14(7:0) melk {>————r| mete es + fetn counter bin(3:3) Figure 8.4 Counting in binary on the eight LEDsClocks and Counters a7 Listing 8.3 count8_top.v ~~ Example ac: counté top library IEEE; use IEEE.std_logic_1164.al1; Library EXAMPLES; entity counté_top is port ( melk : in std logic; btn : in STD_LOGIC_VECTOR(3 downto 3); ld : out std_logic vector (7 downto 0) de end counts_top: architecture counté_top of counté_top is component clkdiv pert ( clr : in std_logic; molk : in std_logic; c1k3 : out std_logic ds end component; component counter generic( No: INTEGER := 8 7 port ( clk : in std_logic; cle : in std_logic; q : out std_logic_vector(N-1 downto 0) a+ end component; signal clk3 : std_logic: begin UL : clkdiv port map( C1k3 => clk3, cle => btn(3), melk => melk); U2 : counter generic map ( N => 8) port map( clk => clk3, clr => btn(3), g => 1d( 7 downto 0 )); end _count@ top: Internally, a counter contains a collection of flip-flops. We saw in Fig. 1 of the Introduction that each of the four slices in a CLB of a Spartan3E FPGA contains wo flip-flops. Such flip-flops are central to the operation of all synchronous sequential circuits in which changes take place on the rising edge of a clock. The examples in the second half of this book will involve sequential circuits beginning with an example of an edge-triggered D flip-flop in Example 16.48 Example 9 Example 9 7-Segment Decoder In this section we will show how to design a 7-segment decoder using Karnaugh maps and write a VHDL program to implement the resulting logic equations. We will also solve the same problem using a VHDL case statement. Prerequisite knowledge: Karnaugh maps — Appendix D case statement ~ Example 7 LEDs— Example 1 * 9.1 7-Segment Displays Seven LEDs can be arranged in a pattern to form different digits as shown in Fig. 9.1. Digital watches use similar 7-segment displays using liquid crystals rather than LEDs. The red digits on digital clocks are LEDs. Seven segment displays come in two flavors: common anode and common cathode. A common anode 7-segment display has all of the anodes tied together while a common cathode 7-segment display has all the cathodes tied together as shown in Fig. 9.1 43.3 Common ‘Anode def g co awe ge t ° i abe abc | e Common co Cathode d Figure 9.1 A 7-segment display contains seven light emitting diodes (LEDs) The BASYS and Nexys? boards have four common-anode 7-segment displays. This means that all the anodes are tied together and connected through a pnp transistor to +3.3V. A different FPGA output pin is connected through a 1000 current-limiting resistor to each of the cathodes, a — g, plus the decimal point. In the common-anode case, an output 0 will turn on a segment and an output I will tum it off. The table shown in7-Segment Decoder 49 Fig. 9.2 shows output cathode values for each segment a — g needed to display all hex values from 0—F. 1 = 0: 0=0 a = fE of b mn g a cy d CoH OHSOCO CO OHOOHOlp HHOHHOOCCHHOOOOOly HHOHCSoODC OOD OHOOls HocooHooHooHooHoals coc oooh OMOHHHOHOl® BN BATPOMRIANAYNH OK CoH ODOC OHO OOHEHOlm Figure 9.2 Segment values required to display hex di 9.2. 7-Segment Decoder: Logic Equations The problem is to design a hex (0 7-segment decoder, called hex7seg. that is shown in Fig. 9.3. The input is a 4-bit hex number, x(3:0), and the outputs are the 7- segment values a — g given by the truth 73.9) ——5| a to g[6:0 table in Fig. 9.2. We ean make aKamaugh *!2"0] hex7seg pam 2_t0_9[6:0] map for each segment and then write logic equations for the segments a — g. For example, the K-map for the segment, e, is Figure 9.3 A hex to 7-segment decoder shown in Figure 9.4. = 73 8x0 13 832 & x1 | ZB WHI BO x1 x0 sx30\_001 0 110 1 a7 oo} og Dy 33.30 gu 3812 85a a 1 N\ | 7T—\ x2 &=x1 & x0) Figure 9.4 K-map for the segment o in the 7-segment decoder50 Example 9 You can write the Karnaugh maps for the other six segments and then write the VHDL program for the 7-segment decoder shown in Listing 9.1. A simulation of this program is shown in Fig. 9.5. Note that the simulation agrees with the truth table in Fig. 9.2. Listing 9.1 hex7seg_le.vhd Example 9a: Hex to 7-segment decoder; a-g active low library IESE; use IEEE.STD_LOGIC_1164 aL} entity hex7seg_le is port ( x + 4m STD_LOGIC_VECTOR(3 downto 0); a_to_g : out STD LOGIC VECTOR(6 downto 0) de end hex7seg_le; architecture hex7seg_le of hex7seg_le is begin a_to.g(6) <= (not x(3) and not x(2) and not x(1) and x(0))- for (not x(3) and x(2) and not x(1) and not x(9)) for (x(3) and x(2) and not x(1) and x(0)) or (<(3) and not—x(2)—and x(1) and x(0)) ; ato_g(5) <= (x(2) and x(1) and not x(0)) or (x(3) and x(2) and x(0)) for (not x(3) and x(2) and not x(1) and x(0)) or (x(3) and x(2) and mot x(1) and not x(0)); ato_g(4) <= (mot x(3) and not x(2) and x(1) and not x(0))--c for (x(3) and x(2) and x()) or (<(3) and x(2) and not x(0)); ato.g(3) <= (mot x(3) and not x(2) and not x(1) and x(0))--a for (not (2) and x(2) and not x(1) and not x(0)) fo (x(3) and not x(2) and x(1) and not x(0)) or («(2) and x(1) and x(0)); ate.g(2) <= (mot x(3) and x(0)) a2 or (not x(3) and x(2) and not x(1)) or (not x(2) and not x(1) and x(0)); <= (not x(3) and not x(2) and x(0)) -£ or (not x(3) and mot (2) and x(1)) or (not x(3) and x(t) and x(0)) or (x(3) and x(2) and not x(1) and x(0)); ato.g{0) <= (mot x(3) and not x(2) and not x(1)) 3 or (x(3) and x(2) and not x(1) and not x(0)) or (not x(3) and x(2) and x(1) and x(0)); end hex?seg_le; atog To EW Soomh Wow Wovens Daven” Snuston he i RAS waa @ al w Figure 9.5 Simulation of the VHDL program in Listing 9.17-Segment Decoder El 9.3 7-Segment Decoder: case Statement We can use a VHDL case statement to design the same 7-segment decoder that wwe designed in Section 9.2 using Kamnaugh maps. The VHDL program shown in Listing 9.2 is a hex-to-seven-segment decoder that converts a 4-bit input hex digit, 0 F, to the appropriate 7-segment codes, a — g. The case statement in Listing 9.2 directly implements the truth table in Fig. 9.2. Recall that a typical line in the case statement, such as when "0011" => a_to_g <= "0000110"; --3 will assign the 7-bit binary value, 0000110, to the 7-bit array, 2 to_g, when the input hex value x(3:0) is equal to 3 (0011). In the amay aco g the value a ro_o(6) corresponds to scement @ and the value a_to_o(0) corresponds to segment g. . Note that in VHDL a hex number is preceded by an-X. In the case statement the value following the when statement in each line represents the value of the case parameter, in this case the 4-bit input x. The VHDL program in Listing 9.2 shows the implementation of the 7-segment decoder using a case statement, Recall that all case statements should include a when others line as shown in Listing 9.2. This is because all cases need to be covered and while it looks as if we covered all cases in Listing 9.2, as mentioned previously VHDL actually defines nine possible values for each bit of type STD_LOGIC_VECTOR (see Example 1). A simulation of Listing 9.2 will produce the same results as shown in Fig. 9.5. It should be clear from this example and Example 7 that using the VHDL case statement is often easier than solving for the logic equations using Karnaugh maps. To test the 7-segment displays on the BASYS or Nexys-2 board create a new project and add the files hex7seg.vhd from Listing 9.2 and the top-level design hex7seg_top.vid given in Listing 9.3. Each of the four digits on the 7-segment display is enabled by one of the active low signals an(3:0) and all digits share the same a_t0_(6:0) signals. If an(3:0) = 0000 then all digits are enabled and display the same hex digit. This is what we do in Fig. 9.6 and Listing 9.3. Making the output dp = 1 will cause the decimal points to be off. You should be able to display all of the hex digits from 0 —F by changing the four right-most switches. ut $030) D—80) 29,10) ‘a_to_g(6:0) hax7seg jvec Dap GND.GND.GND.GKD, oD an(3:0) __GND Figure 9.6 Top-level design for testing ex7seq