Delay Test

• Delay test definition

• Circuit delays and event propagation
• Path-delay tests
§ Non-robust test
§ Robust test
§ Five-valued logic and test generation
• Path-delay fault (PDF) and other fault models
• Test application methods
§ Combinational, enhanced-scan and normal-scan
§ Variable-clock and rated-clock methods
• At-speed test
• Timing design and delay test
• Summary

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 Delay Test Definition
• A circuit that passes delay test must produce correct outputs when inputs are
applied and outputs observed with specified timing.
• For a combinational or synchronous sequential circuit, delay test verifies the
limits of delay in combinational logic.
• Delay test problem for asynchronous circuits is complex and not well
understood.
• A delay fault means that the delay of one or more paths (not necessarily the
critical path) exceeds the clock period.

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Digital Circuit Timing
Input Output Transient
Signal region
Observation
changes instant

Inputs
Comb.
logic

Outputs
Synchronized
With clock
time
Clock period
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Circuit Delays
• Switching or inertial delay is the interval between input change and output
change of a gate:
§ Depends on input capacitance, device (transistor) characteristics and
output capacitance of gate.
§ Also depends on input rise or fall times and states of other inputs
(second-order effects).
§ Approximation: fixed rise and fall delays (or min-max delay range, or
single fixed delay) for gate output.
• Propagation or interconnect delay is the time a transition takes to travel
between gates:
§ Depends on transmission line effects (distributed R, L, C parameters,
length and loading) of routing paths.
§ Approximation: modeled as lumped delays for gate inputs
• See Section 5.3.5 for timing models.

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Event Propagation Delays
Single lumped inertial delay modeled for each gate
PI transitions assumed to occur without time skew
Path P1

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0 1

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P2 1

0 2 3
P3

0 2 5

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Circuit Outputs
• Each path can potentially produce one signal
transition at the output.
• The location of an output transition in time is
determined by the delay of the path.

Clock period
Final value

Initial value

Fast transitions Slow transitions

time
Initial value Final value

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Singly-Testable Paths
(Non-Robust Test)
• The delay of a target path is tested if the test propagates a transition via
path to a path destination.
• Delay test is a combinational vector-pair, V1,V2, that:
§ Produces a transition at path input.
§ Produces static sensitization -- All off-path inputs assume non-
don’t controlling states in V2.
care
V1 V2 Off-path inputs
V1 V2

Target
path

Static sensitization guarantees a test when the target path is the

only faulty path. The test is, therefore, called non-robust. It is a test
with minimal restriction. A path with no such test is a false path.
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Non-Robust Test continued…

By the end of the clock period, all signals other than the on-path signals of
the path under test must be in their steady-state.

Since the off-path steady-state signals sensitize the entire path under test,
the path destination signal is uniquely controlled by the transition
propagating through the path.

If the path delay exceeds the clock period, then the observed value at the
path destination at the end of the clock period will differ from the steady-
state output due to test vector-2, which is the correct expected value.

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Robust Test
• A robust test guarantees the detection of a delay
fault of the target path, irrespective of delay faults
on other paths.
• A robust test is a combinational vector-pair, V1, V2,
that satisfies following conditions:
• Produce real events (different steady-state values for V1 and
V2) on all on-path signals.
• All on-path signals must have controlling events arriving via the
target path.
• A robust test is also a non-robust test.
• Concept of robust test is general – robust tests for
other fault models can be defined.

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A Five-Valued Algebra
• Signal States: S0, U0 (F0), S1, U1 (R1), XX.
• On-path signals: F0 and R1.
• Off-path signals: F0=U0 and R1=U1.
Input 1 Input 1
AND S0 U0 S1 U1 XX OR S0 U0 S1 U1 XX

S0 S0 S0 S0 S0 S0 S0 S0 U0 S1 U1 XX
U0 S0 U0 U0 U0 U0 U0 U0 U0 S1 U1 XX
Input 2

Input 2
S1 S0 U0 S1 U1 XX S1 S1 S1 S1 S1 S1
U1 S0 U0 U1 U1 XX U1 U1 U1 S1 U1 U1
XX S0 U0 XX XX XX XX XX XX S1 U1 XX

Input
S0 U0 S1 U1 XX Ref.:
NOT
Lin-Reddy
S1 U1 S0 U0 XX IEEETCAD-87
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 Robust Test Generation
Test for P3 – falling transition through path P3: Steps A through E

E. Set input of AND gate to

S0 to justify S0 at output
XX S0 S0
U0 D. Change off-path input
C. F0 interpreted as U0;
to S0 to Propagate R1
propagates through U0
through OR gate
AND gate

A. Place F0 at R1
path origin
Path P3
F0

XX F0 R1
U0 Robust Test:
B. Propagate F0 through OR gate; S0, F0, U0
also propagates as R1 through
NOT gate

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Non-Robust Test Generation
Fault P2 – rising transition through path P2 has no robust test.

C. Set input of AND gate to

propagate R1 to output
D. R1 propagates through
XX U1 OR gate since off-path
R1 input is U0
R1

Path P2 R1
A. Place R1 at
path origin
R1
R1 U1 U0 Non-robust test requires
XX Static sensitization:
S0=U0, S1=U1
U0
B. Propagate R1 through OR gate;
interpreted as U1 on off-path signal; Non-robust test:
propagates as U0 through NOT gate U1, R1, U0

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 Other Delay Fault Models
• Segment-delay fault -- A segment of an I/O path is assumed to have large
delay such that all paths containing the segment become faulty.
• Transition fault -- A segment-delay fault with segment of unit length (single
gate):
§ Two faults per gate; slow-to-rise and slow-to-fall.
§ Tests are similar to stuck-at fault tests. For example, a line is initialized to
0 and then tested for s-a-0 fault to detect slow-to-rise transition fault.
§ Models spot (or gross) delay defects.
• Line-delay fault – A transition fault tested through the longest delay path.
Two faults per line or gate. Tests are dependent on modeled delays of
gates.
• Gate-delay fault – A gate is assumed to have a delay increase of certain
amount (called fault size) while all other gates retain some nominal delays.
Gate-delay faults only of certain sizes may be detectable.

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Delay Test Methodologies

The application of delay tests depends on the type of circuit and

the DFT hardware used.
• Slow-clock combinational test
• Enhanced-scan test
• Normal-scan sequential test
• Variable-clock non-scan sequential test
• Rated-clock non-scan sequential test

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 Slow-Clock Test
Input Combinational Output
latches circuit latches

Input Output
test clock test clock

Ø This procedure is applicable to combinational circuits or to those sequential circuits that are internally
combinational with flip-flops only at PIs and POs
Ø Input and output test clocks control the application of vectors and latching of combinational outputs,
respectively.
Ø These clocks should be independently controllable to allow a phase delay or skew.

Ø A two-vector delay test assumes that all signals due to the first vector V1 will have reached their steady
state when V2 is applied.
Ø If this assumption is not valid, then the actual circuit may still have some transient signals when V2 is
applied.
Ø These transients can interfere with the testing of the targeted path.
Ø To avoid this problem, vectors are applied at a slower than the rated clock frequency
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 Slow-Clock Test
Ø The output clock is skewed by an amount that equals the rated-clock period, which is the
time allowed for the V1-to- V2 transitions to flow through the combinational logic.

Ø If the delay of the activated path is longer than the rated-clock period, then the output
produced by V1 will be captured in the output latch and an observation of its state will
detect the fault.

Test Rated
clock clock
period period
Input
test clock
Output
test clock
V1 V2
applied applied Output
latched
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 Enhanced-Scan Test
Ø This method is applicable to scan types of sequential circuits. Its main advantage is that any arbitrary vector-
pair can be applied.

Ø Each vector contains two parts, namely, bits corresponding to the Pis and bits corresponding to state
variables. The state portion of V1 is serially shifted in the scan register via the SCANIN terminal by setting
test control TC = 0 and applying the clock CK. Often, scan is done using a slow-clock to reduce the power
dissipation.

Ø However, it is also necessary that any delay faults in the scan path do not interfere with the vector. Scanned
V1 bits are then transferred to hold latches (HL) by activating the HOLD signal while the PI bits of V1 are
applied at PI.
Ø As signals due to V1 stabilize, the state bits of V2 are scanned in.

Ø Next, simultaneous activation of HOLD and application of V2 bits to PI provides a V1-to-V2 transition at the
input of combinational logic.

Ø Test control TC = 1 sets the circuit in normal mode for exactly one rated-clock period, at the end of which the
clock CK latches the combinational outputs in flip-flops.

Ø This one cycle of clock must have the rated period. PO signals are directly observed and flip-flop states are
scanned out. 32
Enhanced-Scan Test
CK
period

PI Combinational PO
CK
circuit
SCAN- CK TC
OUT HOLD
HL SFF
Scanout
V1 settles result
HL SFF
SCANIN

Normal
Normal
HOLD

mode
mode
Scan mode
CK TC TC
CK: system clock Scanin Scanin
TC: test control V1 V2 states Result
HOLD: hold signal states latched
SFF: scan flip-flop V1 PI V2 PI
HL: hold latch applied applied
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 Normal-Scan Test
Ø Normal full-scan circuits (with no hold latches) can be tested for delay faults, but the vector-pairs must be especially
generated.

Ø Here, the first vector V1 is scanned in (usually with a slow scan clock) and is then replaced in the scan register by either
(a) applying a one-bit shift to the scan register, or
(b) propagating V1 through the combinational logic in the normal mode.

Scan-shift delay test or skewed-load delay test:

v scan in of V1 is followed by one extra cycle of slow-clock while the circuit is still in the scan mode TC = 0. The test is so
designed that V2 is obtained by a one-bit translation of V1. So, only the bit in the flip-flop closest to the SCANIN input is
supplied externally.
v PI bits of two vectors, which are not restricted, are directly applied at the proper time. As soon as V2 is applied, the mode is
changed from scan to normal (TC = 1) and one application of clock CK with the rated period latches the outputs. The
observation of PO is synchronized with the rated-clock and flip-flop states are scanned out for observation.

Broad-side delay test:

The state portion of V2 must be justified by V1 applied to the combinational logic. When the vector-pair has this characteristic,
scanning in of V1 and application of its PI bits automatically produce the state portion of V2 at the output of the combinational
logic.
An application of the clock in the normal mode and application of the PI part of V2 creates the V1-to-V2 transition.
Keeping the circuit in the normal mode, one rated-clock period later, the outputs are observed at PO or scanned out.
Both methods are used for testing path-delay and transition faults. 34
Normal-Scan Test
V2 states generated, (A) by one-bit scan shift of V1, or
(B) by V1 applied in functional mode. Result
latched
V1 PIs V2 PIs
PI Combinational PO applied applied
Scanin Gen. V2 Path Result
circuit
V1 states states tested scanout
SCAN- CK TC t
OUT Slow clock Rated
SFF CK period

TC

Normal
mode
Scan mode Scan mode
SFF (A)
SCANIN
Slow CK
CK TC period

TC
CK: system clock (B) Scan mode Normal mode Scan mode
TC: test control
SFF: scan flip-flop

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 Variable-Clock Sequential Test
Ø Testing of a delay fault in a non-scan sequential circuit requires more than two vectors.
Ø First, the vector-pair should be like the one used in the second method of the last subsection. That is, V2 should be
justified by V1 through the combinational function.

Ø Second, V1 should be generated, by a set of vectors starting at some initial state. We will call this set a justification
sequence.

Ø Third, if the path destination is a flip-flop then the state should be propagated to some PO. We will call this part of
the test as the propagation sequence. This test scenario is depicted in Figure (next slide) by the time-frame
expansion as was used in Chapter 8 for sequential circuit ATPG.

q In Figure (next slide), vector V1 is applied in time-frame T(n-1) and the target path is partially sensitized. Recall
that the path has to be fully sensitized only in V2. That is why we have shown the path with a broken line (see Fig.
Next). In V1 produces V2 states in the three flip-flops.

q However, to ensure that V2 is correctly produced and is not affected by some delays in T(n-1) we must allow extra
time for V1 to propagate through the circuit. This is done by using a slow-clock, which is also used for the same
reason for justification and propagation sequences. Thus, only one vector, i.e., V2, in the entire test sequence uses
the rated clock. This procedure is known as the slow-clock or variable-clock delay testing.

The slow-clock prevents the delays in the circuit from interfering with the detection of
the target fault. 36
Variable-Clock Sequential Test
Off-path
flip-flop

PI PI PI PI PI PI

0 1
T 1 T n-2 1 T n-1 1 T n 1 T n+1 T n+m

2 2 2
0 D

PO PO PO PO PO PO
Path Fault effect
Initialization sequence activation propagation
(slow clock) (rated sequence
Clock) (slow clock)
Note: Slow-clock makes the circuit fault-free in the presence of
delay faults.
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Rated-Clock Sequential Test
• All vectors are applied with rated-clock.
• Paths are singly and multiply activated potentially in
several time-frames.
• Test generation requires a 41-valued logic (Bose, et al.,
IEEETVLSI, June 1998).
• Test generation is extremely complex for non-scan
circuits (Bose and Agrawal, ATS-95).
• Fault simulators are effective but work with
conservative assumptions (Bose, et al., IEEETVLSI, Dec.
1993; Parodi, et al., ITC-98).

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Comparing PDF Test Modes

PDFs
testable
Combinationally
by variable-
testable PDFs
clock seq.
test
All PDFs of
seq. circuit

PDFs testable by
rated-clock seq. test

Ref.: Majumder, et al., VLSI Design - 98

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At-Speed Test
• At-speed test means application of test vectors at the rated-clock speed.
• Two methods of at-speed test.
• External test:
§ Vectors may test one or more functional critical (longest delay) paths and a large
percentage (~100%) of transition faults.
§ High-speed testers are expensive.
• Built-in self-test (BIST):
§ Hardware-generated random vectors applied to combinational or sequential logic.
§ Only clock is externally supplied.
§ Non-functional paths that are longer than the functional critical path can be
activated and cause a good circuit to fail.
§ Some circuits have initialization problem.

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Timing Design & Delay Test
• Timing simulation:
• Critical paths are identified by static (vector-less) timing analysis
tools like Primetime (Synopsys).
• Timing or circuit-level simulation using designer-generated functional
vectors verifies the design.
• Layout optimization: Critical path data are used in
placement and routing. Delay parameter extraction,
timing simulation and layout are repeated for iterative
improvement.
• Testing: Some form of at-speed test is necessary. PDFs
for critical paths and all transition faults are tested.

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Summary
• Path-delay fault (PDF) models distributed delay defects. It verifies the
timing performance of a manufactured circuit.
• Transition fault models spot delay defects and is testable by modified
stuck-at fault tests.
• Variable-clock method can test delay faults but the test time can be long.
• Critical paths of non-scan sequential circuits can be effectively tested by
rated-clock tests.
• Delay test methods (including BIST) for non-scan sequential circuits using
slow ATE require investigation:
§ Suppression of non-functional path activation in BIST.
§ Difficulty of rated-clock PDF test generation.
§ Long sequences of variable-clock tests.

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Thanks

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