HDM Fpga Asic
HDM Fpga Asic
Vin_Rx_RF
Vout_TX
V_tail_PLL
Vout_RX
Vref (DAC) B1
S/H clk B2
ADC clk B3
Vin (ADC) B4
DAC out B5
b6 B6
TRNG
b5 o/p
TRNG
b1 b2 b3 b4
o/p gnd Agnd
Classification
General Purpose
•Die size = 112 mm2
• 90 nm Process Technology
• 16 kB L1 Cache, 1 MB L2
Cache
• 125000000 transistors
Application Specific
• Die size = 2.25 mm2
• Core size = 1 mm2
• 180 nm Process Technology
• No Cache memory (Used
only registers)
• Clock Freq = 20 MHz
Commercial
Technology
2. UMC
3. IBM
4. Samsung
5. Global Foundries
6. ST Microelectronics
7. IHP Germany
8. SCL India
FPGA Providing Vendors for FPGA based
Systems:
• Xilinx
• Toshiba
• Concurrent logic
• Altera
• AMD
• Actel
• Quicklogic
• Crosspoint
Recent Trends on VLSI Technology Industry:
Hardware Design
Computer Science
(CPU, GPU, DSP)
Software Design
(Applications) How fast a complex system can be realized,
which is in working condition and sellable ?
Design Management and Execution:
Provided by Semiconductor
Manufacturing Companies SPICE Simulation
1. Design Rules
2. Transistor models
3. Passive device models
4. I/O pads, Bond pads
System Examples:
1. OPAMP Design
2. Transceiver Design SPICE Simulation
3. Power Supply Design
4. Memory Design
Test Plan of Transceiver chip:
+++++ -------
------ +++++
P+ N+ N+ P+ P+
P+ N+
NMOS PMOS
NWell
P Substrate
C B E B C
N+
P
N
Fixed AND
ARRAY
PAL:
A B C
Fixed OR ARRAY
AB
A C’
A B’
B C’
Programmable
AND ARRAY
x y
PLA:
A B C
Programmable
OR ARRAY
AB
A C’
A B’
BC
Programmable
AND ARRAY
x y
CPLD:
High Logic to Interconnect ratio
Ideal option for implementation of simple functions
Look up Tables:
• DFF
• Unlatched combinational circuit output
• Latched combinational circuit output
Basic Elements of FPGA:
1. Logic Block
2. Interconnect Block
3. I/O Block
CPLD vs FPGA:
FPGA providing vendors:
• Xilinx
• Toshiba 1. SRAM based Programming
• Concurrent logic 2. Floating gate based programming
• AMD
• Actel
• Quicklogic
• Crosspoint
Antifuse based Programming:
• Actel
• Quicklogic
• Crosspoint
• Altera
• AMD
• Xilinx
• Toshiba
• Concurrent logic
Programming an FPGA:
Application:
Software
Hardware
Applications
Operating System
Compiler Firmware
[1] David Patterson, “50 years of Computer Architecture: From the Mainframe CPU to
the Domain-Specific TPU and the Open RISC-V Instruction Set, ISSCC 2018.”
Hardware Software Productivity gap:
VLSI Technology
(Scaling)
Hardware Design
(CPU, GPU, DSP)
Software Design
(Applications)
Methods for Algorithm Execution:
Microprocessor
+
Reconfigurable Logic
Coupling:
Partitioning of Tasks
[2] Axel Jantsch, Peeter Ellervee, Johnny Oberg, and Ahmed Hemani, “A Case Study on Hardware software
Partitioning”, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines, 1994, pp. 111-118.
TOP Down Design Process for Systems:
Specification
System Architecture
Integration Integration
System Test
Courtsey: Wayne Wolf
Applications:
Summary:
If PA and PB are the probabilities the inputs A and B are 1, then the
output transition probability P01 can be expressed as
For NAND, P01 = P0 . P1 = PA PB (1- PA PB)
For NOR, P01 = P0 . P1 = [1- (1- PA )(1- PB)] [(1- PA )(1- PB)]
Probability of switching:
+++++ -------
------ +++++
P+ N+ N+ P+ P+
P+ N+
NWell
P Substrate
Inverter Voltage Transfer Characteristics:
Inverter Voltage Transfer Characteristics:
Noise Margin of Inverter:
VOH
Logic 1
VIH
Undefined
VIL
Logic 0
VOL
Inverter Layout:
Power Estimation of Inverter:
NAND2, NOR2 Optimization:
VTC of NAND2, NOR2 w.r.t. Inverter :
VTC of NAND2 :
VTC of NOR2 :
Logic Families:
• Static CMOS
• Complementary CMOS
• Pseudo NMOS
• Pass transistor
• Dynamic Circuit
• Domino Logic
SIMD:
Temporal Architecture is
used by CPUs and GPUs.
Controller and register file is
shared by all ALUs.
Provided by Semiconductor
Manufacturing Companies SPICE Simulation
1. Design Rules
2. Transistor models
3. Passive device models
4. I/O pads, Bond pads
System Examples:
1. OPAMP Design
2. Transceiver Design SPICE Simulation
3. Power Supply Design
4. Memory Design
PDK for Fully Custom Design:
SS S G D D G S SS
+++++ -------
------ +++++
P+ N+ N+ P+ P+
P+ N+
NMOS PMOS
NWell
P Substrate
C B E B C
N+
P
N
R1 in out 1K
C1 out 0 1p
Vin in 0 AC PULSE(0 1.8 1n 1n 1n 10n 20n)
.plot transient v(in) v(out)
Inverter Design:
S G D D G S VDD
+++++ -------
------ +++++
P+ N+ N+ P+ P+
P+ N+
NWell
P Substrate
SPICE Code for Inverter (AIMSPICE):
Inverter Design
vdd 3 0 dc 1.8
Vin in 0 dc 0.0 PULSE(0 1.8 2n 2n 2n 25n 50n)
Vout
Vin
Can you use this as an amplifier ?:
Slope =-1
|Gain| > 1
Slope =-1
vdd 3 0 dc 1.8
vin in 0 dc 0.0 sin(0.85 0.01 1KHz 0 0)
m1 2 in 3 3 ptype l=180n w=4800n
m2 2 in 0 0 ntype l=180n w=2400n
vdd 3 0 dc 1.8
vin in 0 dc 0.0 sin(0.75 0.01 1KHz 0 0)
R1 2 3 10K
m1 2 in 0 0 ntype l=180n w=2400n
R2 out 3 10K
Design Tips:
1. With technology scaling, gds value of MOSFET increases.
2. Therefore, intrinsic voltage gain gets affected.
3. Use higher channel length than the minimum value.
4. Overdrive voltage > 200 mV but should be < 500 mV
Small Signal Analysis
Small Signal Analysis
Small Signal Analysis
Biasing
Biasing is needed With biasing, amplified output
to fix the DC operating point should be received
Biasing
• VDS changes due to RL value
• IDS changes due to VDS • AC power will be received
• Transistor may go towards linear • Biasing will not be affected
Biasing
• Bias and Signal has same ref value
• Bias is shorted.
• Bias from supply
• Don’t have control on bias voltage
Biasing
• Now VGS is different than VDD
• Advantage of negative feedback
• Use a coupling capacitor
• Gain improved
Capacitor Replacement
• Use - supply to avoid CG
• Use circuit with low o/p resistance to avoid CD
Capacitor Replacement
• Replace CS
• Use a low impedance path
SPICE Code of Differential Amplifier
vdd 3 0 dc 1.8
.defwave vo = v(out1)-v(out2)
.defwave vi = v(in1)-v(in2)
RS was replaced by m3 Transistor .plot ac vdb(vo,vi)
In SPICE code
.MODEL ntype NMOS (use parameters)
.MODEL ptype PMOS (use parameters)
Results of Diff Amp:
CE/CS Amplifier
Miller Capacitance
The capacitance value is amplified that effects the
bandwidth of the CE/CS amplifier
Bandwidth of CS Amplifier
Question1 (DC Bias effect):
Circuit 1 Circuit 2
Circuit 1 Circuit 2
Circuit 1 Circuit 2
Circuit 1 Circuit 2
.plot ac vdb(2,4)
.plot v(2) v(4)
RL
R0
CS with source degeneration
Negative feedback by the resistor, RS
Independent on transistor internal parameters
Approximately, AV = -RL/ RS
CS with source degeneration, current load
r01
High value
If somebody did mistake in connection,
then what will be output ?
Linearity
K = Boltzmann constant
R = Resistance
T = Temperature
B = Bandwidth
vdd 5 0 dc 1.8
R1 1 5 100K
R2 1 0 157K
Rd 4 5 5K
Rs 2 0 1.5K
c1 2 3 1u
c2 4 0 10p
vin 3 0 dc 0.0 ac 1.0 sin(0.5 0.5 1KHz 0 0)
Find f3db ?
Detailed Analysis of CS Amplifier
(2)
(3)
(2)
(3)
(4)
.plot ac vdb(vout,v1)
.MODEL ntype NMOS (Use parameters)
.MODEL ptype PMOS (Use parameters)
Results of Diff Amp:
Operational Amplifier Design:
SPICE Code of Operational Amplifier:
vdd 3 0 dc 1.8
vin1 v1 0 dc 0.85 ac 1 sin(0.5 0.4 1KHz 0 0)
vin2 v2 0 dc 0.85
C1 p2 vout 2.2p
C2 vout 0 10p
.plot ac vdb(vout,v1)
.MODEL ntype NMOS (Use All parameters here)
.MODEL ptype PMOS (Use All parameters here)
Results of 2-stage OPAMP:
Thank you