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Module Seven

This module displays time on a 7-segment display by taking in clock input and time values as inputs. It uses a counter to cycle through the digits to display. A case statement decodes the binary time values into the 7-segment display values. The current time mode is tracked and the time can be set or displayed depending on button presses.

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DUY NGUYỄN HẠO
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10 views

Module Seven

This module displays time on a 7-segment display by taking in clock input and time values as inputs. It uses a counter to cycle through the digits to display. A case statement decodes the binary time values into the 7-segment display values. The current time mode is tracked and the time can be set or displayed depending on button presses.

Uploaded by

DUY NGUYỄN HẠO
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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module Seven_Segment_Module(

input clk,

input [3:0] min_1, //0-9 , 9-->1001

input [3:0] min_2,

input [3:0] hrs_1,

input [3:0] hrs_2,//1

output reg [6:0] seg1,

output reg [6:0] seg2,

output reg [6:0] seg3,

output reg [6:0] seg4

);

reg [1:0] digit_display = 0;

reg [6:0] display [3:0];

reg [18:0] countt = 0;

parameter max_count = 1_000_000 ; //100MHz/100 Hz mô phỏng cho đúng với tần số


500_000

wire [3:0] four_bit [3:0];

assign four_bit[0] = min_1;

assign four_bit[1] = min_2;

assign four_bit[2] = hrs_1;

assign four_bit[3] = hrs_2;

always @(posedge clk) begin

if (countt < max_count) begin

countt <= countt+1;


end else begin

digit_display <= digit_display + 1;

countt <= 0;

end

// g f e d c b a

case(four_bit[digit_display])

4'b0000 : display[digit_display] <= 7'b1000000; //0

4'b0001 : display[digit_display] <= 7'b1111001; //1

4'b0010 : display[digit_display] <= 7'b0100100; //2

4'b0011 : display[digit_display] <= 7'b0110000; //3

4'b0100 : display[digit_display] <= 7'b0011001; //4

4'b0101 : display[digit_display] <= 7'b0010010; //5

4'b0110 : display[digit_display] <= 7'b0000010; //6

4'b0111 : display[digit_display] <= 7'b1111000; //7

4'b1000 : display[digit_display] <= 7'b0000000; //8

4'b1001 : display[digit_display] <= 7'b0011000; //9

endcase

case(digit_display)

0: seg1 <= display[0];

1: seg2 <= display[1];

2: seg3 <= display[2];

3: seg4 <= display[3];


endcase

end

endmodule

module DigitalClock_24hrFormat(

input clk,

input center,

input right,

input left,

input up,

input down,

output [6:0] seg1,

output [6:0] seg2,

output [6:0] seg3,

output [6:0] seg4,

output clock_mode_led

);

reg [31:0] countt =0;

parameter max_count=25_000_000; // 100_000_000

reg [5:0] hrs, min, sec = 0;//hrs 0 - 23, min 0 -59, sec 0 - 59

reg [3:0] min_1, min_2, hrs_1, hrs_2 = 0;

reg toggle = 0;

reg clock_mode = 0;

assign clock_mode_led = clock_mode;

Seven_Segment_Module SSM(clk, min_1, min_2, hrs_1, hrs_2 , seg1, seg2,seg3,seg4);


parameter display_time = 1'b0;

parameter set_time = 1'b1;

reg current_mode = set_time;

always @(posedge clk) begin

case(current_mode)

display_time: begin // Clock mode - 00:00 to 23:59

if (center) begin

clock_mode <= 0;

current_mode <= set_time;

countt <= 0;

toggle <= 0;

sec <= 0;

end

if (countt <max_count) begin // time

countt <= countt + 1;

end else begin

countt <= 0;

sec <= sec + 1;

end

end

set_time: begin

if (center) begin

clock_mode <= 1;

current_mode <= display_time;

end
if (countt < (25_000_000)) begin

countt <= countt + 1;

end else begin

countt <= 0;

case (toggle)

1'b0: begin

if (up) begin

min <= min + 1;

end

if (down) begin

if (min > 0) begin

min <= min - 1;

end else if (hrs > 0) begin //1:00, 0:59

hrs <= hrs - 1;

min <= 59;

end

end

if (left || right) begin

toggle <= 1;

end

end

1'b1: begin

if (up) begin

hrs <= hrs + 1;

end
if (down) begin

if (hrs > 0) begin

hrs <= hrs - 1;

end else begin //0:00

hrs <= 23;

end

end

if (right || left) begin

toggle <= 0;

end

end

endcase

end

end

endcase

//Digital Clock 24hr_format

if (sec >= 60) begin // After 60 seconds, increment minutes

sec <= 0;

min <= min + 1;

end

if (min >= 60) begin // After 60 minutes, increment hours

min <= 0;

hrs <= hrs + 1;

end

if (hrs >= 24) begin // After 24 hours, reset the hours back to 0

hrs <= 0;

end
min_1 <= min % 10;

min_2 <= min / 10;

hrs_1 <= hrs % 10;

hrs_2 <= hrs / 10;

end

endmodule

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