SET – 1

1. A sequential circuit has three flip-flops A, B, C; one input x; and one output, y. The state
diagram is shown in Fig.P5-19. The circuit is to be designed by treating the unused states
as don’t-care conditions. Analyze the circuit obtained from the design to determine the
effect of the unused states.
a) Use D flip-flops in the design
b) Use J-K flip-flops in the design

2. find the SOP for the following using K –Map

i. f(a,b,c,d) = ∑(0,2,3,4,7,8,14)
ii. f = ∏(0,2,4,6,8)∙D(1,12,9,15)
3. Design a Code converter to convert BCD to 8421 code.
4. Design a sequential circuit using JK - FF that has 1 data input (w) and 1 data output (z).
The output z will become 1 only if the input w has been 1 for the last 5 clock cycles.
Draw the FSM diagram and write/simulate the Verilog code to verify it.
5. Write an HDL dataflow description of a 4-bit adder/subtractor of unsigned numbers. Use
the conditional operator.
6. Simplify the following using Boolean expression
 
i.  A  C  AD  A D  AC  C
 SET – 2
1. Simplify the following using Boolean expression
W X  X Y  YZ  W Z
2. find the SOP for the following using K –Map
i. x ' z  w' xy ' w( x ' y  xy ' )
3. A half adder is a circuit that adds two bits to give a sum and a carry. Give the truth table
for a half adder, and design the circuit using only two gates. Then design a circuit which
will find the 2’s complement of a 4-bit binary number. Use four half adders and any
additional gates.

4. Write an Verilog HDL description of a 4-bit CARRY SAVE ADDER.

5. Design a sequential circuit using T - FF that has 1 data input (w) and 1 data output (z).
The output z will become 1 only if the input w has been 1010 over the last 4 clock cycles.
Draw the FSM diagram and write/simulate the Verilog code to verify it.
6. A. 87 – 55 using both 1’s and 2’s complement
B. 23 - 91 using both 1’s and 2’s complement
 SET – 3

1. CONVERT THE FOLLOWING

a. 101011110.11101 = ___________9, ___16,H
b. 467.238 = _______4, 2, H
c. C49D.B7 = ___________2,8,7
2. Simplify the following using Boolean expression
i .[ x ( xy )' ][ y ( xy )' ]
ii .( a b  c d  e f )
iii .( a  c )( a  c )( a  b  c d ) tofourlite rals

3. A flow rate sensing device used on a liquid transport pipeline functions as follows. The
device provides a 5-bit output where all five bits are zero if the flow rate is less than 10
gallons per minute. The first bit is 1 if the flow rate is at least 10 gallons per minute; the first
and second bits are 1 if the flow rate is at least 20 gallons per minute; the first, second, and
third bits are 1 if the flow rate is at least 30 gallons per minute; and so on.The five bits,
represented by the logical variables A, B, C, D, and E, are used as inputs to a device that
provides two outputs Y and Z.
(a) Write an equation for the output Y if we want Y to be 1 iff the flow rate is less than 30
gallons per minute.
(b) Write an equation for the output Z if we want Z to be 1 iff the flow rate is at least 20
gallons per minute but less than 50 gallons per minute.
4. Draw a state diagram for a mealy type state machine specified as follows:
- Denote "a" the initial state of the machine
- set the initial output to the initial input (the input is presented to the machine bit by bit)
- The output changes value only when three successive inputs have the same value and that
value is opposite to the current output. For example, if the current output is 1 and the
machine detects three consecutive 0 it changes the output to 0.
design the circuit using D – FF and write the verilog HDL.
5. Design the 4 bit 7311 code to 53-1-1 code and write the Verilog HDL using if else statement.
 SET – 4

1. find the SOP for the following using K – map

i. A' B' C ' D' BC' D  A' C ' D  A' BC  AD'
ii. f = ∏(1,3,5,9,11,12,14)
iii. f = ∑(0,1,2,5,7,8,10,15)
2. Design a code converter to convert 84-1-2 to 5311 code.
3. Perform the following
(i) 93 – 14 using 1’s complement
(ii) 87 – 6 using 2’s complement
4. Find the minimum product of sums and sum of Product for
(a) F(a, b, c, d, e) =∑ m(1, 2, 3, 4, 5, 6, 25, 26, 27, 28, 29, 30, 31)
(b) F = M(1,4,5,8,10,13)
5. Draw a state diagram for a Moore type state machine specified as follows:
- Denote "a" the initial state of the machine
- set the initial output to the initial input (the input is presented to the machine bit by bit)
- The output changes value only when three successive inputs have the same value and that
value is opposite to the current output. For example, if the current output is 1 and the
machine detects three consecutive 0 it changes the output to 0.
- design the circuit using RS – FF and write the verilog HDL
6. Simplify the following using Boolean expression
i.a ' bcd  a ' bc ' d  b ' ef  cde' g  a ' def  a ' b ' ef ( reduced to sum of 3 terms)
ii.( x  y )( y  z )( x  z )  ( x ' y ' )( y ' z ' )( x ' z ' ) (give the algebraic proof)
iii. F = ∏(3,5,8,11)
 SET – 5

1. A combinational circuit is divided into two subcircuits N1 and N2 as shown. The truth
table for N1 is given. Assume that the input combinations ABC = 110 and ABC = 010
never occur. Change as many of the values of D, E, and F to don’t-cares as you can
without changing the value of the output Z.

2. Perform the following

i. 1100011 – 1011011 using 1’s and 2’s complement subtraction
ii. 98 – 24 using 1’s complement
3. Simplify the following using Boolean expression
i. AB ( D  C D )  B ( A  ACD ) to one literal
ii. ABCD + A’B’C’D + A’BCD + AB’CD + A’B’CD + ABCD’
4. A combinational circuit has four inputs (A, B, C, D) and four outputs (W, X, Y, Z). WXYZ
represents an excess-3 coded number whose value equals the number of 1’s at the input.
For example, if ABCD = 1101, WXYZ = 0110.
(a) Find the minterm expansions for X, Y, and Z.
(b) Find the maxterm expansions for Y and Z.
5. For the given code give the hardware equivalent circuit and convert the code using case
statement
module problem(input logic resetn, clock,
input logic x, y, z, c1, c2,
output logic f, g);
always_ff @(posedge clock or negedge resetn)
begin
if (!resetn) begin
f <= 1'b0;
end else begin
f <= x;
if (c1) f <= y;
if (c2) f <= z;
end
end
always_comb begin
if (c2) g = z;
else if (c1) g = y;
else g = x;
end
endmodule
6. Design a 4 bit serial adder with accumulator and write the Verilog HDL code.
 SET – 6
1. Given the enclosed source code, draw the equivalent hardware circuit.
module setr(input logic clock,
output logic[7:0] f);
logic[7:0] a, b, c;
always_ff @(posedge clock)
begin
a <= b + c;
b = c + a;
c = a + b;
end
assign f = c;
endmodule
2. Draw the Moore state diagram and state table for a serial even parity checker. The circuit
receives a word of 4-bits serially on its single input X and produces the even parity bit
after the fourth bit is received. The single output Z remains 0 except when the final
(fourth) bit is received and the total number of 1’s in the word is odd. The machine
returns to the reset initial state after the 4th input bit. Design the circuit using RS – FF
and write the code using gate level and dataflow.
3. Simplify using K – Map
i. f = ∑(0,6,8,13,14)+d(2,4,10)
ii. (A’+B+D’)(A’+B’+C’)(A’+B’+C)(B’+C+D’)
iii. F(v, w, x, y, z) = ∑m(4, 5, 8, 9, 12, 13, 18, 20, 21, 22, 25, 28, 30, 31)
4. Design a code converter to convert Excess – 1 Code to 8421 code.
5. Write the HDL for carry select adder which has 4 bits.
6. Design a 5 bit Twisted Ring counter using JK Flip flop.
 SET – 7
1. Perform the following
i. 11110011 – 1110011 using 1’s and 2’s complement subtraction
ii. 88 – 43 using 1’s complement
iii. 35 – 95 using 2’s complement
2. Reduce the combinational logic circuit in Fig. to a minimum form.

3. Simplify the following using Boolean algebra

i. f=m(1,2,4,7,10,12)

4. Identify each of the following expression as SOP, POS and its canonical form
respectively
a. AB  ABD  AC D
5. Design a finite state machine (FSM) for a counter that counts through the 3-bit prime
numbers downwards. Assume the counter starts with initial prime value set to 010 as its
first 3 bit prime number. You need to provide the state transition table and the state
transition diagram. Assume that the state is stored in three D-FFs. Write the HDL code
and simulate
Hint: The set of all 3-bit prime numbers includes 2, 3, 5 and7.
6. Gray codes have the useful property that consecutive numbers differ in only a single bit
osition. Design a 3-bit Gray code counter FSM with no inputs and three outputs. When
reset, the output should be 000. On each clock edge, the output should advance to the
next Gray code. After reaching 100, it should repeat with 000. Draw a schematic for this
counter using T flip-flops.
SET – 8

1. Evaluate the following expression

a. ( P  Q) R S  T  U
b. Simplify using K – map and give the SOP and POS

F = π(0,1,3,5,6,9,10,13,14)
2. Design an excess-3 code converter to drive a seven-segment indicator. The four
inputs (A, B, C, D) to the converter circuit represent an excess-3 digit. Input
combinations representing the numbers 0 through 9 should be displayed as decimal
digits. The input combinations 0000, 0001, and 0010 should be interpreted as an
error, and an “E” should be displayed. Assume that the input combinations 1101,
1110, and 1111 will never occur. Design your circuit using only two-, three-, and four
input NOR gates and inverters. Any solution with 18 or fewer gates and inverters (not
counting the four inverters for the inputs) is acceptable.

3. Subtraction using 1’s and 2’s complement

a. 673 – 76
b. 87 – 534
4. Design a home security system as follows. There are 3 input sensors called, e
(enable), w (window) and d (door). There is one output called s (alarm sound). After reset
the system is disarmed. The system stays in the disarmed state until e is pressed, when it
will move to the armed state. In this state, if e is pressed again the system will move back
to the disarmed state. If however, w or d sensors are sensed while the system is in the
armed state, the system will activate the alarm sound as follows. Signal s will be turned
on for 500 clock cycles then it will shut down for 300 clock cycles. This sequence will
repeat itself until e becomes 1, in which case the system returns to the disarmed state.
Derive the data-path elements and the FSM in the control-path. Write/simulate the
Verilog code to verify the entire design.

5. An up-down mod-4 binary counter has a single input x, such that the it counts up if x=0
and counts down if x=1:
Draw the Mealy state diagram of the circuit.
* Draw the state Moore diagram of the circuit.
* Implement both circuits using negative-edge triggered D-FFs.

6. Design a code converter to convert Excess – 1 Code to 84-2-1 code.

SET – 9
1. Simplify the following using Boolean law with minimum literals and implement
using Universal gates ` a.
Y  A  AB  ( A  B )C  ( A  B  C )D b.
prove that A B C  A BC  AB C  ABC  A B C  A  B  C
c. Show that A  B  C  D = ∑(0,3,5,6,9,10,12,15)
2. Simplify the following Using K –map,
a. F = ∑(0,2,3,6,7)+d(8,12,15)
b. F = ∑(0,2, 8,10,14,16,18,19,24)+d(4,11,15,23,27,28)
3. Design a circuit which can convert BCD to 2421 code.
4. In an application 4 inputs A, B, C, D are available in true and complement Form
.These are fed at a logic circuit which operates a relay. The relay is ON for
ABCD = 0000, 0010, 0101, 0110, 1101 and 1110. The states 1000 and 1001 don’t
occur. For remaining states the relay is OFF.
i. prepare truth table and minimize outputs F using K map
ii. Realize F using 3 input NAND gates.
5. Given the enclosed source code, draw the equivalent hardware circuit.
module setq(input logic clock,
output logic[7:0] f);
logic[7:0] a, b, c;
always_ff @(posedge clock)
begin
a = b + c;
b <= c + a;
c = a + b;
end
assign f = c;
endmodule
6. Draw a state diagram for a mealy type state machine specified as follows:
 Denote "a" the initial state of the machine
 set the initial output to the initial input (the input is presented to the
machine bit by bit)
 The output changes value only when three successive inputs have the
same value and that value is opposite to the current output. For example,
if the current output is 1 and the machine detects three consecutive 0 it
changes the output to 0.
Design the circuit using T – FF and write the verilog HDL.
SET – 10
1. Given the enclosed source code, draw the equivalent hardware circuit.
module setp(input logic c1, c2, c3, a, b,
output logic f, g);
always_latch
begin
if (c1) begin
f = a;
g = b;
end else if (c2) begin
f = b;
end else if (c3) begin
g = a;
end
end
endmodule
2. Design a 1-bit decrementer (a circuit which subtracts 1). Give
(a) the arithmetic relationship between input and out put signals
(b) the truth table,
(c) logic diagram.
Design a logic diagram of a 1-bit increment/decrement circuit controled by an id signal
(increment when id = 1, decrement otherwise). Write the HDL.
And Design a block diagram of a 4-bit increment/decrement circuit. Use the above HDL
and concatenate.
3. Convert the following
a. 11110010.1110012 = __________8,5,H
b. 32134 = __________2,10,8
c. 34D.EFF = _______4,2,O
4. Prove that:
a. A  B  AB  A  B
b. [(A+B)’ + (C+D)’]’ = (A+B)(C+D)
5. Design a Code converter to convert 4241 to excess 2 code using only NOR gates.
6. Simplify logic function using k – map minimization technique
5. Y( A , B , C, D) = ∑ m ( 0, 1, 3, 7, 8, 9,11,15)
6. Simplify the Boolean expression using four variables:
w’ z + x z + x’ y + w x’ z
7. Use algebraic techniques to determine whether or not the following Boolean
equation is valid:
( abd  ab  bd  c )(c  ab  bd )  b( a  c )(a  c )  d (b  c )
 SET – 11
1. I want to schedule a meeting among 6 individuals Alice, Brian, Charles, David, Elise and
Frank. The meeting must be scheduled so that the following rules are satisfied: • Exactly
one of Alice and Brian must be in the meeting. • Charles and David must be present in the
meeting together. If Charles is not available, David and Frank must be in the meeting
together. However, all three of Charles, David and Frank must not be present. • Elise is the
manager of the group, so she must be present in the meeting. Each of the 6 team members
indicates to me their availability for the meeting. I would like to construct a logic netlist
with a single output g, such that g is equal to ′1 ′ whenever the meeting can be scheduled.
(a) List the Boolean variables (b) Write down what both values of each variable indicate.
(c) Draw the circuit using logic gates.
(d) Implement the same using only NOR gates.
2. Find a minimum POS for the following
i. F(a,b,c,d,e) = m (4,5,8,9,12,13,18,20,21,22,25,28,30,31)
ii. F = M(9,10,4,7,2,8,13).d(0,2,15)
3. Design a code converter to convert 5311 to 24-2-1 code.
4. Using 1’s complement and 2’s complement do the following i.(-12-65), ii. 97 – 143
5. Design a serial subtractor with accumulator for 5-bit binary numbers. Assume that
negative numbers are represented by 2’s complement. Use a circuit of the form of Figure
18-1, except implement a serial subtractor using a D-CE flip-flop and any kind of gates.
Give the state graph for the control circuit. Assume that St will remain 1 until the
subtraction is complete, and the circuit will not reset until St returns to 0.write the HDL
using behavioural level.
6. Write the HDL code for 4 bit Manchester Adder.
SET – 12
1. Derive the state table and state diagram of the synchronous sequential circuit shown (X is
an input to the circuit). Explain the circuit function.

2. Write the HDL for 4 bit Braun’s Multiplier

3. Design a circuit that compares two binary numbers X and Y, each having two bits
(X=x2x1; Y=y2y1). It has a single output c which is supposed to be 1 when X > Y, and 0
otherwise. Do not use adders/subtractors for this design; instead use a fundamental
design process. Draw the minimum sum-of-products circuit using the correct circuit
symbols for all gates. Assume complemented inputs are NOT available, but multiple
input gates are. What is the delay of this circuit, assuming the delay for each gate is d?
4. Consider a function f on three variables a, b and c. Suppose f is completely specified, and
written as
f  ab c  a bc  abc  a bc  abc  abc
(a) Is the above expression a canonical SOP? If so, state why. If not, state why
not. (b) Construct a K-map for f
(c) Write down the prime implicants of f
(d) Write down a minimum SOP expression for f. (e) If
the input combination abc was a don’t care, then what write down the new prime
implicants of f. Also, write down a minimum SOP expression for f. What is the benefit of
using this minimum SOP for f over the one from part d)?
5. Convert the following
a. 12367.12310 = __________2,5,16
b. 11101001.101 = _________o,H,9
c. 654.128 = ______2,H
6. Evaluate the following expression
a. ( P  Q) R S  T  U + U
b. Simplify using K – map and give the SOP and POS
F = π(0,2,3,6,7,8,11,13,15)
 SET – 13
1. Consider the following circuit:

a. Give the algebraic expression of the function

b. Simplify the algebraic expression
c. Draw using only NAND gates
2. Find a minimum POS for the following
i. F(a,b,c,d,e) = m (4,5,8,10,12,14 ,18,20,21,22,25,28,30,31)
ii. F = M(12,10,5,1,2,3,8,13).d(0,11,15)
3. Simplify each of the following expressions:
ABCD  ABCD  BEF  CDEG  ADEF  ABEF
(reduce to a sum of three terms). Draw using only a. NAND gates, b. NOR gates
4. a. Perform the subtraction 64 – 31 and 99 – 7 in 1’s and 2’s complement method.
b. Simplify the following expression to a sum of two terms and then factor the result
to obtain a product of sums:
ab d f  bceg h  abd f  ac d e  bce
5. Design and write the Verilog HDL for 4 bit Vedic multiplier.
6. Draw the Mealy state diagram and state table for a serial even parity checker. The circuit
receives a word of 4-bits serially on its single input X and produces the even parity bit
after the fourth bit is received. The single output Z remains 0 except when the final
(fourth) bit is received and the total number of 1’s in the word is odd. The machine returns
to the reset initial state after the 4th input bit. Design the circuit using D – FF and write the
code using gate level and dataflow.
 SET – 14
1. Given the enclosed source code, draw the equivalent hardware circuit. Draw also
the periodic waveforms on the output signals f and g. If the reference clock is 200 MHz,
then what are the frequencies of signals f and g ?
module setm(input logic resetn, clock,
output logic f, g);
logic[9:0] counter;
always_ff @(posedge clock or negedge resetn)
if (!resetn) begin
counter <= 10'h000;
f <= 1'b0;
g <= 1'b0;
end else begin
f <= 1'b1;
if (counter > 10'd50 && counter < 10'd250) f <= 1'b0;
g <= 1'b0;
if (counter > 10'd150 && counter < 10'd400) g <= 1'b1;
if (counter < 10'd900) counter <= counter + 10'd1;
else counter <= 10'd0;
end
endmodule
2. Design a sequential circuit using D - FF to convert excess-3 code to BCD. This circuit
adds three to a binary-coded-decimal digit in the range 0 to 9.The input and output will be
serial with the least significant bit first.
3. Find the complements for the following numbers:
a. (100111.1100)2 = _______8,9,H
b. (751.33)8 = _____4,9,2
c. (52,784,630)10 = _____2,8,H
4. Each of three coins has two sides, heads and tails. Represent the heads or tails status of
each coin by a logical variable (A for the first coin, B for the second coin, and C for the
third) where the logical variable is 1 for heads and 0 for tails. Write a logic function F(A,
B, C) which is 1 iff exactly one of the coins is heads after a toss of the coins. Express F
a. as a minterm expansion.
b. as a maxterm expansion.
Draw the circuit using only NOR gate.
5. Find the minimum minterms using K – map
F(a, b, c, d, e) =π M(2, 4, 5, 6, 8, 10, 12, 13, 16, 17, 18, 22, 23, 24) • πD(0, 11,
30, 31)
6. Design a network of NAND gates and inverters that converts from 8-4-2-1 BCD code to 6-
3-1-1 code.
 SET – 15
1. PERFORM THE FOLLOWING
i. 1001101 – 1110011 using 1’s complement subtraction
ii. 1100011 – 10110011 using 2’s complement subtraction
iii. 93 – 65 using both 1’s and 2’s complement
iv. 57 - 99 using both 1’s and 2’s complement
2. Simplify the following using Boolean algebra
i. Y  (C  D ) AC D  A BC  A BCD  AC D
ii.

iii. F = M(3,7,8,10,12,13)
3. Simplify the following using K – map to SOP and POS
i. f = M(0,3,5,6,8,10)+d(11,13,14)
ii. F ( A, B, C , D )  A  B  D
iii. F = ∑(21,7,30,2,8,15,19,3) + d(0,18,15,6)
4. Design a Code Converter to convert 24-2-1 code to 2421 code
5. Given the enclosed hardware circuit, write/simulate the equivalent Verilog code.

6. Write the HDL for 4 bit BCD adder.

SET – 16
1. Design a sequential circuit using T - FF to convert BCD to excess-3 code. This circuit adds
three to a binary-coded-decimal digit in the range 0 to 9.The input and output will be serial
with the least significant bit first.
2. Write the HDL for 4 bit Kogge stone adder.
3. Figure below shows the intersection of a main highway with a secondary access road.
Vehicle- detection sensors are placed along lanes C and D (main road) and lanes A
and B (access road). These sensor outputs are LOW (0) when no vehicle is present
and HIGH (1) when a vehicle is present. The intersection traffic light is to be
controlled according to the following logic:

1. The east-west (E-W) traffic light will be green whenever both lanes C
and D are occupied.
2. The E-W light will be green whenever either C or D is occupied but
lanes A and B are not both occupied.
3. The north-south (N-S) light will be green whenever both lanes A and B
are occupied but C and D are not both occupied.
4. The N-S light will also be green when either A or B is occupied while C
and D are both vacant. 5. The
E-W light will be green when no vehicles are present. Using the sensor outputs A,
B, C, and D as inputs, design a logic circuit to control the traffic light.There
should be two outputs, N-S and E-W, that go HIGH when the corresponding light
is to be green. Simplify the circuit as much as possible and show all steps.
4. CONVERT THE FOLLOWING
i. 1010110110.10011 = ___________9, ___16,H
ii. 781.78 = _______4, 2, H
iii. 6A5D.E0 = ___________2,8,7
5. find the SOP for the following using K –Map
i. f(a,b,c,d) = ∑(0,2,3,4,7,8,10,13,14,15)
ii. f = ∏(0,2,4,6,7,8,13)∙D(1,12,10,15)
iii x ' z  w' xy ' w( x ' y  xy ' )
6. Simplify the following using Boolean expression
i. (𝐴 + 𝐶 )(𝐴𝐷 + 𝐴𝐷) + 𝐴𝐶 + 𝐶
iii. ab  bc  ca  ab  b c  c a
 SET – 17
1. A manufacturing plant needs to have a horn sound to signal quitting time. The horn should
be activated when either of the following conditions is met:
a. It’s after 5 o’clock and all machines are shut down.
b. It’s Friday, the production run for the day is complete, and all machines are
shut down.
c. Design a logic circuit that will control the horn. (Hint: Use four logic input
variables to represent the various conditions; for example, input A will be
HIGH only when the time of day is 5 o’clock or later.)
2. Simplify using K – Map and give the SOP and POS
i. F = m(7,13,5,30,17,5,27,8,14,19)+d(0,11,12,15,21)
ii. Y = C ( A B D  D )  A BC  D
iii. Determine the minimum expression for each K map given below

3. Convert the Following

i. 86753.12 = ___________2,H
ii. 11110001.11 = ______________O,9,4
iii. AED.87 = ______________9,2
4. Design a code converter to convert 53-1-1 to 84-2-1
5. Given the enclosed hardware circuit, write/simulate the equivalent Verilog code.

6. Write the HDL for 4 bit Booth Multiplier.

 SET – 18

1. Write the Verilog code using if else condition and truth table for the circuit given below.

2. Write the HDL for 4 bit ALU.

3. Perform the subtraction 52 – 73 and 111011 - 100101 using 1’s and 2’s complement
method.
4. i. Reduce the combinational logic circuit in Fig. to a minimum form.
ii. Draw the optimized circuit using only NAND gate

5. Simplify the following using Boolean algebra

f=m(1,2,4,7,10,12)
6. Identify each of the following expression as SOP, POS and its canonical form respectively.

AB  ABD  AC D
SET – 19

1. Convert the following

a. 11110010.1110012 = __________8,5,H
b. 32134 = __________2,10,8
c. 34D.EFF = _______4,2,O
2. Perform the subtraction 64 – 31 and 99 – 7 in 1’s and 2’s complement method.
b. Simplify the following expression to a sum of two terms and then factor the result
to obtain a product of sums:
ab d f  bceg h  abd f  ac d e  bce
3. The adder-subtractor circuit of Fig. below has the following values for mode input M
and data inputs A and B:

in each case determine the values of the four SUM outputs, the carry C, and
overflow V.
4. Design a code converter to convert gray code to 2421.
5. Design and write the Verilog HDL for 4 bit parallel multiplier.
6. Draw the Mealy state diagram and state table for a serial even parity checker. The
circuit receives a word of 4-bits serially on its single input X and produces the even
parity bit after the fourth bit is received. The single output Z remains 0 except when
the final (fourth) bit is received and the total number of 1’s in the word is odd. The
machine returns to the reset initial state after the 4th input bit. Design the circuit
using T– FF and write the code using gate level and dataflow.
SET – 20

1. Write Verilog code that represents the circuit in Figure below. Use the dec2to4
module as a subcircuit in your code using case statement.

2. For the given code give the hardware equivalent circuit and convert the code
using case statement.
module setj(input logic resetn, clock,
input logic start, stop,
input logic load, serial_in,
input logic [7:0] parallel_in,
output logic parity);
logic shift_left;
logic[7:0] shift_register;
always_ff @(posedge clock or negedge resetn)
begin
if (!resetn) begin
shift_left <= 1'b0;
shift_register <= 8'd0;
end else begin
if (start) shift_left <= 1'b1;
if (stop) shift_left <= 1'b0;
if (shift_left) shift_register <= {shift_register[6:0],serial_in};
else if (load) shift_register <= parallel_in;
end
end
always_comb begin
parity = ^shift_register;
end
endmodule
3. Fig. below shows a diagram for an automobile alarm circuit used to detect certain
undesirable conditions. The three switches are used to indicate the status of the
door by the driver’s seat, the ignition, and the headlights, respectively. Design the
logic circuit with these three switches as inputs so that the alarm will be activated
 whenever either of the following conditions exists:

i. The headlights are on while the ignition is off.

ii. The door is open while the ignition is on.
4. Find the minimum product of sums and SOP for
(a) F(a, b, c, d, e) =∑ m(1, 2, 3, 4, 6,10,12,15,19, 25, 26, 27, 28, 29, 30, 31)
(b) π(0,2,3,5,6,8,10,13,14)
5. Perform the following
i. 11110011 – 1110011 using 1’s and 2’s complement subtraction
ii. 88 – 45 using 1’s complement
iii. 35 – 92 using 2’s complement
 SET – 21
1. Each of the following sentences has two possible interpretations depending on whether the
AND or OR is done first. Write an equation for each interpretation. (a) The buzzer will
sound if the key is in the ignition switch, and the car door is open, or the seat belts are not
fastened. (b) You will gain weight if you eat too much, or you do not exercise enough, and
your metabolism rate is too low. (c) The speaker will be damaged if the volume is set too
high, and loud music is played, or the stereo is too powerful. (d) The roads will be very
slippery if it snows, or it rains, and there is oil on the road.
2. Simplify the following using Boolean law with minimum literals and implement using
Universal gates ` a.
Y  A  AB  ( A  B )C  ( A  B  C )D b. prove that

A B C  A BC  AB C  ABC  A B C  A  B  C

3. Show that A  B  C  D = ∑(0,3,5,6,9,10,12,15)

4. Perform the following
i. 1001100-110011 using 1’s complement subtraction
ii. 93 – 14 using 1’s complement
iii. 87 – 6 using 2’s complement
5. Write the HDL for 4 bit Carry Look Ahead adder using dataflow.
6. For the given code give the hardware equivalent circuit and convert the code using case
statement
module problem(input logic resetn, clock,
input logic x, y, z, c1, c2,
output logic f, g);
always_ff @(posedge clock or negedge resetn)
begin
if (!resetn) begin
f <= 1'b0;
end else begin
f <= x;
if (c1) f <= y;
if (c2) f <= z;
end
end
always_comb begin
if (c2) g = z;
else if (c1) g = y;
else g = x;
end
endmodule
 SET – 22
1. Using a active low output decoder and external gates, design the combinational circuit defined by
the following three Boolean functions:
a.
𝑓 = 𝑥̅ 𝑦𝑧 + 𝑥𝑧̅
𝑓 = 𝑥̅ 𝑦𝑧̅ + 𝑥𝑦
𝑓 = 𝑥𝑦𝑧̅ + 𝑥𝑦
b. s
𝑓 = (𝑥 + 𝑦)𝑧̅
𝑓 = 𝑥𝑧 + 𝑦𝑧̅ + 𝑧𝑦
𝑓 = (𝑦 + 𝑧̅)𝑥
2. An 8x1 multiplexer has inputs A, B and C connected to the selection inputs S2, S1, and S0
respectively. The data inputs through I0 through I7 are as follows:
(a) I1 = I2 = I4 = 0; I3 = I5 = 1; I0 = I7 = D; and I6 = D0.
(b) I2 = I3 = 0; I4 = I5 = I7 = 1; I0 = I6 = D; and I1 = D0.
Determine the Boolean function that the multiplexer implements.
3. Find the SOP and POS for the following using K – map
i. A' B' C ' D' BC' D  A' C ' D  A' BC  AD'
ii. f = ∏(1,3,5,9,11,12,14)
iii. f = ∑(0,1,2,5,7,8,10,15)
4. Design a logic circuit whose output is HIGH whenever A and B are both HIGH as
long as C and D are either both LOW or both HIGH. Try to do this without using a
truth table. Then check your result by constructing a truth table from your circuit to
see if it agrees with the problem statement. Write the Dataflow HDL.
5. Design a code converter to convert 2421 to 5311 code.
6. Design a 4 bit serial adder with accumulator and write the Verilog HDL code.
 SET – 23
1. Using a case statement, write an HDL behavioral description of an eight-bit arithmetic-logic unit
(ALU). The ALU needs to implement the 10 functions listed below. The inputs are two eight-bit
numbers A and B, and select inputs S (where S has enough bits to select the ten functions). The
outputs are the eight-bit result R, a zero-bit Z, and a carry bit C. The C bit is described in the table
below. (X means Don’t Care.) The zero bit Z is 1 if all the bits of the eight-bit result are 0, and is 0
otherwise.

2. Implement the following Boolean functions with only one 4:1 multiplexer:
a. F(w, x, y, z) = m(2, 3, 5, 6, 11, 14, 15)
b. F(w, x, y, z) = M(3, 10, 11)
3. Perform the following
(i) 1001100-110011 using 1’s complement subtraction
(ii) 93 – 14 using 1’s complement
(iii) 87 – 6 using 2’s complement
4. Convert the following
i. 1111111012 = _______4,10, H
ii. 8AF2.E9 = _________2, 8, 10
5. Design a 1-bit decrementer (a circuit which subtracts 1). Give
(a) the arithmetic relationship between input and out put signals
(b) the truth table,
(c) logic diagram.
Design a logic diagram of a 1-bit increment/decrement circuit controled by an id signal
(increment when id = 1, decrement otherwise). Write the HDL.
And Design a block diagram of a 4-bit increment/decrement circuit. Use the above HDL
and concatenate.
6. Design a sequential circuit that works as a traffic light controller. The circuit does
not have any data inputs (the clock and asynchronous reset are obviously available) and it
has three data outputs: Red, Green and Yellow. After reset the circuit will activate Red for
200 clock cycles, then it will activate Green for 200 clock cycles and then it will activate
Yellow for 20 clock cycles (this sequence will repeat itself). While one output signal is
turned on the other two output signals are deactivated. Derive the data-path elements and
the FSM in the control-path. Write/simulate the Verilog code to verify the entire design.
 SET – 24
1. A computer interface to a line printer has seven data lines that control the movement of the
paper and the print head and determine which character to print. The data lines are labeled A,
B, C, D, E, F, and G, and each represents a binary 0 or 1. When the data lines are interpreted
as a 7-bit binary number with line A being the most significant bit, the data lines can represent
the numbers 0 to 12710. The number 1310 is the command to return the print head to the
beginning of a line, the number 1010 means to advance the paper by one line, and the
numbers 3210 to 12710 represent printing characters.
(a) Write an equation for the variable X which is 1 iff the data lines indicate a command
to return the print head to the beginning of the line.
(b) Write an equation for the variable Y which is 1 iff there is an advance paper command on
the data lines.
(c) Write an equation for the variable Z which is 1 iff the data lines indicate a printable
character. (Hint: Consider the binary representations of the numbers 0–31 and 32–127 and
write the equation for Z with only two terms.)

2. Design a Code converter to convert 5311 code to gray code

3. Simplify the following using Boolean algebra
i. Y  (C  D ) AC D  A BC  A BCD  AC D
ii.

iii. F = M(3,7,8,10,12,13)
4. Analyze the shift register and draw state diagram and state table for the que 1. (Please take the help of
the initiated state diagram with eight states shown below, but draw your own figure to answer).

5. Write the HDL for 4 bit Wallace tree multiplier.

6. You need to design a synchronous sequential circuit in the form of a positive edge-triggered Moore
machine using RS - FF. The input signal w is synchronized with the clock pulses C. The output signal
z should become 1 each time the value of the input signal w had not changed for two clock pulses.
This change in the output value will appear at the clock pulse following the two pulses with the
identical w values. See the example below for clarification.
w: 001100011011100111111000010110 ...
z: 001010100100100101000001000001 ...
Set up the circuit’s state table and draw the state diagram
SET – 25
1. As an example of an unstructured combinational circuit design a circuit that divides a 3-
bit positive binary number a = (a2a1a0)2 by a 2-bit positive binary number b = (b1b0)2
calculating a 3-bit quotient q = (q2q1q0)2 and a 2-bit remainder r = (r1r0)2 so that

To make the task easier, take into account the following:

a. Complete the above table.

b. Derive logic equations for q and r. Aim at minimal implementation. Use
Karnaugh maps when it makes the job easier.
c. Draw logic diagrams and write the HDL code using gate level and dataflow.
2. Design a 1-bit decrementer (a circuit which subtracts 1). Give
(a) the arithmetic relationship between input and out put signals
(b) the truth table,
(c) logic diagram.
Design a logic diagram of a 1-bit increment/decrement circuit controled by an id signal
(increment when id = 1, decrement otherwise). Write the HDL.
And Design a block diagram of a 4-bit increment/decrement circuit. Use the above HDL
and concatenate.
3. Simplify the Following using Boolean Algebra
i.
( w  x  y  z )( w  x  y  z )( w  x  y  z )( w  x  y  z )( w  x  y  z )( w  x  y  z )
ii. Q  RST ( R  S  T )
iii. Change each gate into NOR gate and simplify the Boolean algebra

4. Simplify the following using K – map to SOP and POS

i. f = M(0,3,5,6,8,10)+d(11,13,14)
 ii. F ( A, B, C , D )  A  B  D
iii. F = ∑(21,7,30,2,8,15,19,3) + d(0,18,15,6)
5. Design a Code Converter to convert 2421 code to 24-2-1 code
6. A manufacturing plant needs to have a horn sound to signal quitting time. The horn
should be activated when either of the following conditions is met:
i. It’s after 5 o’clock and all machines are shut down.
ii. It’s Friday, the production run for the day is complete, and all machines are shut
down.
Design a logic circuit that will control the horn. (Hint: Use four logic input variables
to represent the various conditions; for example, input A will be HIGH only when the
time of day is 5 o’clock or later.)
 SET – 26
1. Design a sequential circuit that works as a traffic light controller. The circuit does not
have any data inputs (the clock and asynchronous reset are obviously available) and it has
three data outputs: Red, Green and Yellow. After reset the circuit will activate Red for
200 clock cycles, then it will activate Green for 200 clock cycles and then it will activate
Yellow for 20 clock cycles (this sequence will repeat itself). While one output signal is
turned on the other two output signals are deactivated. Derive the data-path elements and
the FSM in the control-path. Write/simulate the Verilog code to verify the entire design.
2. Draw a state diagram for a Moore type state machine specified as follows:
- Denote "a" the initial state of the machine
- set the initial output to the initial input (the input is presented to the machine bit by bit)
- The output changes value only when three successive inputs have the same value and that
value is opposite to the current output. For example, if the current output is 1 and the
machine detects three consecutive 0 it changes the output to 0.
design the circuit using JK – FF and write the Verilog HDL.
3. Perform the following using 1’s and 2’s complement
i. 92 – 5
ii. 7 – 85
4. Simplify the following using Boolean Algebra
i. F = M(1,9,2, 5, 10,11,7,8)
ii. F  ( A  B  C D E )  BC D
iii. F = (BC’+A’D)(AB’+CD’)
5. Simplify using K – Map and give the SOP and POS
i. F = m(7,13,5,30,17,5,27,8,14,19)+d(0,11,12,15,21)
ii. Y = C ( A B D  D )  A BC  D
iii. Determine the minimum expression for each K map
given below

6. Fig. below shows a diagram for an automobile alarm circuit used to detect certain
undesirable conditions. The three switches are used to indicate the status of the door by
the driver’s seat, the ignition, and the headlights, respectively. Design the logic circuit
with these three switches as inputs so that the alarm will be activated whenever either of
the following conditions exists:

iii. The headlights are on while the ignition is off.

iv. The door is open while the ignition is on.
 SET – 27
1. Design a synchronous sequential circuit that will count through the sequence 0, 2, 4, 6 when its
control input x is 0, and through the sequence 6, 4, 2, 0 when x = 1. The circuit should return to the
0 state if it finds itself in an invalid state.
(a) Draw a state diagram for the circuit.
(b) Draw a state transition table for the circuit.
(c) Write a Verilog module to implement the system.
2. Design the 4 bit 2421 code to 53-1-1 code and write the Verilog HDL using case
statement.
3. Reduce the following using Boolean Algebra f = m(0,2,3,5,7,12,15)
F = a’cd+ab’+ac’e+cd’+b’d’
4. Perform the subtraction 52 – 73 and 111011 - 100101 using 1’s and 2’s complement
method.
5. simplify the following using Boolean laws a.
AB  AC  A BC ( AB  C )
b. ABCD + A’B’C’D + A’BCD + AB’CD + A’B’CD + ABCD’ (Terms 4,5, and 6 are
Don’t Care)
6. A combinational circuit has four inputs (A, B, C, D), which represent a binary coded-
decimal digit. The circuit has two groups of four outputs S, T, U, V, and W, X, Y, Z. Each
group represents a BCD digit. The output digits represent a decimal number which is five
times the input number. For example, if ABCD = 0111, the outputs are 0011 0101.
Assume that invalid BCD digits do not occur as inputs.
(a) Construct the truth table.
(b) Write down the minimum expressions for the outputs by inspection of the truth
table.
 SET – 28
1. An 8x1 multiplexer has inputs A, B and D connected to the selection inputs S2, S1, and S0
respectively. The data inputs through I0 through I7 are as follows:
(a) I1 = I2 = I4 = 0; I3 = I5 = 1; I0 = I7 = D; and I6 = D0.
(b) I2 = I3 = 0; I4 = I5 = I7 = 1; I0 = I6 = D; and I1 = D0.
Determine the Boolean function that the multiplexer implements.
2. Simplify the followin Boolean expressions using three-variable maps:
(a) F(x, y, z) = x’y’z’ + yz + x’y’z
(b) F(x, y, z) = xy + y’z’ + x’y’z
(c) F(x, y, z) = x’y + y’z + x’z’
(d) F(x, y, z) = xyz + xy’z’ + x’yz’
3. The adder-subtractor circuit of Fig. below has the following values for mode input M and
data inputs A and B:

in each case determine the values of the four SUM outputs, the carry C, and overflow V.

4. Convert the following

a. 110100100101.111012 = _________8,7,H
b. 65617 = __________10,2,8
5. Design a code converter to convert 53-1-1 to 8421 write the HDL using Behavioural
modeling
6. Write the HDL for 4 bit modified Booth Multiplier.
 SET – 29
1. An 4x1 multiplexer has inputs A, and C connected to the selection inputs S1, and S0
respectively. The data inputs through I0 through I7 are as follows:
(a) I1 = I2 = I4 = 0; I3 = I5 = 1; I0 = I7 = D; and I6 = D0.
(b) I2 = I3 = 0; I4 = I5 = I7 = 1; I0 = I6 = D; and I1 = D0.
Determine the Boolean function that the multiplexer implements.
2. Construct BCD adder circuit.
3. Draw the minimum NAND-NAND and NOR – NOR implementation for F.
F(A,B,C,D)= m(1,5,8,13-15)+d(3,10,12).
4. Perform the subtraction 52 – 73 and 111011 - 100101 using 1’s and 2’s complement
method.
5. simplify the following using Boolean laws a.
AB  AC  A BC ( AB  C )
b. ABCD + A’B’C’D + A’BCD + AB’CD + A’B’CD + ABCD’ (Terms 4,5, and 6 are
Don’t Care)
6. A combinational circuit has four inputs (A, B, C, D), which represent a binary coded-
decimal digit. The circuit has two groups of four outputs S, T, U, V, and W, X, Y, Z. Each
group represents a BCD digit. The output digits represent a decimal number which is five
times the input number. For example, if ABCD = 0111, the outputs are 0011 0101.
Assume that invalid BCD digits do not occur as inputs.
(a) Construct the truth table.
(b) Write down the minimum expressions for the outputs by inspection of the truth table
 SET – 30
1. Convert the decimal numbers +75 and +32 to 8-bit hexadecimal numbers, unsing the signed
2’s complement representation. Then perform the following operations: (a) (+75) + (−32),
(b) (−75) + (+32), (c) (−75) + (−32). Convert the answers back to decimal and verify that
they are correct.
2. Simplify the following Boolean expressions to a minumum number of operators
(a) [(a’ + bc’d’]’
(b) {(ab + c)[(ab)’ + c’]}’

3. Design the 4 bit 2421 code to 53-1-1 code and write the Verilog HDL using if else
statement.
4. A PN flip-flop has four operations: clear to 0, no change, complement, and set to 1,
when inputs P and N are 00, 01, 10, and 11, respectively.
a) Tabulate the characteristic table.
b) Derive the characteristic equation.
c) Tabulate the excitation table.
d) Show how the PN flip-flop can be converted to a D flip-flop.

5. A combinational circuit has four inputs (A, B, C, D) and three outputs (X, Y, Z). XYZ represents a
binary number whose value equals the number of 1’s at the input. For example if ABCD = 1011,
XYZ = 011.
(a) Find the minterm expansions for X, Y, and Z.
(b) Find the maxterm expansions for Y and Z.
6. Write the HDL for 4 bit Ladner Fishcer adder.
SET – 31
1. Write the HDL for 4 bit Han Calrson adder.
2. Each of three coins has two sides, heads and tails. Represent the heads or tails status of each coin
by a logical variable (A for the first coin, B for the second coin, and C for the third) where the
logical variable is 1 for heads and 0 for tails. Write a logic function F(A, B, C) which is 1 iff
exactly one of the coins is heads after a toss of the coins. Express F
a. as a minterm expansion.
b. as a maxterm expansion.
3. Draw the circuit using only NAND gate.
4. Find the complements of the following expressions:
(a) (x + y’)(x’ + y)
(b) (A’B + CD)E + E’
(c) (x’ + y’ + z)(x + y)(x + z’)

5. Given the enclosed hardware circuit, write/simulate the equivalent Verilog code.

6. A sequential circuit has an input (X) and outputs (Y and Z). YZ represents a 2-bit binary number
equal to the number of 1’s that have been received as inputs. The circuit resets when the total
number of 1’s received is 3, or when the total number of 0’s received is 3. Find a Moore state
graph and table for the circuit.
SET – 32
1. Convert the following NOR-to-OR gate network to a NAND-to-NAND gate network.
Use as minimum gates as possible.

2. Minimize the following Boolean functions.

(i) F (A,B,C,D) =Σ𝑚 (1,3,5,8,9,11,15) +d (2,13)
(ii) F (A,B,C,D) =𝜋M (1,2,3,8,9,10,11,14) +d (7,15)
3. A serial parity-bit generator is a sequential circuit that does the following: it receives
an n-bit message followed by a 0 (so there are n + 1 clock bits to send the message). At
the output, the circuit sends the original n-bit message, but replaces the 0 with a parity
bit. Design a 4-bit serial parity-bit generator which replaces the zero bit with an odd
parity bit.
(a) Draw a state diagram for the circuit.
(b) Draw a state transition table for the circuit.
(c) Show how to implement the circuit using D flip-flops.
(d) Write a Verilog program to implement the circuit.
(e) Is this a Mealy machine or a Moore machine? Why?

4. Convert the decimal numbers +75 and +32 to 8-bit hexadecimal numbers, using the
signed 2’s complement representation. Then perform the following operations: (a)
(+95) + (−32), (b) (−75) + (+42), (c) (−75) + (−32). Convert the answers back to
decimal and verify that they are correct.
5. Write the HDL for 4 bit carry Skip adder
6. A combinational circuit (using only NAND) has four inputs (A, B, C, D) and four
outputs (W, X, Y, Z). WXYZ represents an excess-3 coded number whose value equals
the number of 1’s at the input. For example, if ABCD = 1101, WXYZ = 0110.
(a) Find the minterm expansions for X, Y, and Z.
(b) Find the maxterm expansions for Y and Z.
SET – 33
1. Design a sequential circuit with two D Flip-Flops, A and B, and one input x. When x = 0,
then the state of the circuit remains the same. When x =1, the circuit goes through the state
transitions from 00 to 01 to 11 to 10 back to 00, and repeats.
2. Simplify the following Boolean functions, using 4-variable maps:
a. w’z + xz + x’y + wx’z
b. wxy + yz + xy’z + x’y

3. A BCD-to-seven-segment decoder is a combinational circuit that converts a decimal digit

in BCD to an appropriate code for the selection of segments in a display indicator used for
displaying the decimal digit in a familiar form. The seven outputs of the decoder (a, b, c, d,
e, f, g) select the corresponding segments in the display, as shown in Figure 3a. The
numeric display chosen to represent the decimal digit is shown Figure 3b. Design this
decoder using a minimum number of gates. The six invalid combinations should result in a
blank display.

4. For the following sequential circuit,

a. Write the next-state equations for flipflops A and B.
b. Using these equations, find the state table and draw the state graph.

5. Given the enclosed source code, draw the equivalent hardware circuit. Draw also
the periodic waveforms on the output signals f and g. If the reference clock is 200 MHz,
then what are the frequencies of signals f and g ?
module setm(input logic resetn, clock,
output logic f, g);
logic[9:0] counter;
always_ff @(posedge clock or negedge resetn)
if (!resetn) begin
counter <= 10'h000;
f <= 1'b0;
g <= 1'b0;
end else begin
 f <= 1'b1;
if (counter > 10'd50 && counter < 10'd250) f <= 1'b0;
g <= 1'b0;
if (counter > 10'd150 && counter < 10'd400) g <= 1'b1;
if (counter < 10'd900) counter <= counter + 10'd1;
else counter <= 10'd0;
end
endmodule
6. Design a sequential circuit using JK - FF to convert excess-3 code to BCD. This
circuit adds three to a binary-coded-decimal digit in the range 0 to 9.The input and
output will be serial with the least significant bit first.
 SET – 34
1. Design and write the Verilog HDL for code converter 2421 to 84-2-1 using case statement.
2. Draw the Moore state diagram and state table for a serial even parity checker. The circuit
receives a word of 4-bits serially on its single input X and produces the even parity bit
after the fourth bit is received. The single output Z remains 0 except when the final
(fourth) bit is received and the total number of 1’s in the word is odd. The machine returns
to the reset initial state after the 4th input bit. Design the circuit using RS – FF and write
the code using gate level and dataflow.
3. Construct a 4-to-16-line decoder with five 2-to-4 line decoders with enable.
4. Implement the following Boolean function with only one 4:1 multiplexer:
F(A, B, C, D) = (0, 1, 3, 4, 8, 9, 15)
Consider A and D as Selection lines.
5. Given the enclosed source code, draw the equivalent hardware circuit.
module setp(input logic c1, c2, c3, a, b,
output logic f, g);
always_latch
begin
if (c1) begin
f = a;
g = b;
end else if (c2) begin
f = b;
end else if (c3) begin
g = a;
end
end
endmodule
6. Design a 1-bit decrementer (a circuit which subtracts 1). Give
(a) the arithmetic relationship between input and out put signals
(b) the truth table,
(c) logic diagram.
Design a logic diagram of a 1-bit increment/decrement circuit controled by an id signal
(increment when id = 1, decrement otherwise). Write the HDL.
And Design a block diagram of a 4-bit increment/decrement circuit. Use the above HDL
and concatenate.
 SET – 35
1. An 8 x 1 multiplexer has inputs A, B, and C connected to the selection inputs S2, S1,
and S0, respectively. The data inputs I0 through I7, are as follows: I1 = I2 = I7 = 0; I3
= I5 = 1; I0 = I4 = D; and I6 = D’. Determine the Boolean function and minterms for
that the multiplexer implements.
2. From the following state diagram, create the state table, and corresponding circuit
using D flip-flops. Write the HDL using Data flow modelling.

3. Design a one input, one output serial 2’s complimenter. The circuit accepts a string of
bits from the input and generates the 2’s compliment at the output. The circuit can be
reset asynchronously to start and end the operation. Use JK FF.
4. Simplify the following Boolean functions, using Karnaugh maps:
(a) F(A,B,C,D) = m(1, 3, 6, 7, 10, 11, 13, 15)
(b) F(w, x, y, z) = m(0, 2, 4, 6, 8, 9, 10, 12, 13)
(c) F(w, x, y, z) = M(0,1, 2, 3, 8, 10, 12, 13)
5. Consider the combinational circuit in the figure below.
a. Derive the Boolean expressions for T1 through T4. Derive outputs F1 and F2 as
function of the four inputs.
b. List the truth table (4 variables). Then list T1 through T4, F1 and F2.
c. Use K-maps to simplify these expressions and show that they are equivalent to the
ones o btained in (a).

6. Write the HDL fro 4 bit Parallel Multiplier.

 NAME ASSIGNMENT
REG NO
SET
15BEC0642 A GAGAN HARSHA 1
18BEC0883 A RAAHUL 2
18BEC0971 A RIYASH CHARRAN 3
18BEC0294 AAMIR NAIYER 4
18BEC0401 ABDUL ADNAAN MOHAMMAD 5
18BEC0085 ABHYUDAY TRIPATHI 6
18BEC2037 ABIRLAL DEB 7
18BEC0590 ADITYA BAJPAI 8
18BEC0915 AGNITRA PAUL 9
18BEC0964 AISHWARYA REDDY CHINTHALAPUDI 10
18BEC0550 AKSHAT MANRAL 11
18BEC0830 AMAN AGARWAL 12
18BEC0263 ANSHIKA AGARWAL 13
18BEC0934 ANUMOLU YASWANTH 14
18BEC0965 ARUNIMA DASTIDAR 15
18BEC0209 ASHISH KUMAR 16
16BEC0113 ATLA SRIRAM SAMARA SIMHA REDDY 17
18BEC0945 ATUL WADHWA 18
17BEC0332 AVINASH KUMAR 19
17BEC0094 BADDIGAM NAVEEN KUMAR REDDY 20
18BEC0359 BAJI SUBHODH 21
18BEC0282 CHALAMALASETTI RAHUL 22
18BEC0600 CHEDE ABHISHEK MAHADEV 23
18BEC0120 DHEEKSHINN N 24
18BEC2024 EYASU YADATA DEBELE 25
18BEC0230 GAURAV BOSE 26
18BEC0653 GOGINENI TEJA KUMAR 27
18BEC0019 GOWTHAM R 28
18BEC0399 HANAH FATIMA HANEEZ MOHIDEEN 29
18BEC0129 HARISH MADHAVAN S 30
18BEC0955 HARSH DAYANAND DEEP 31
18BEC2035 HARSH VARDHAN CHAUDHARY 32
17BEC0863 HUSHEN GODHRAWALA 33
18BEC0838 KAMALANAYANA S 34
18BEC0703 KAMISETTI KUMAR VENKATA NAGESWARA RAO 35
18BEC0110 KARNATI SHARATH KUMAR 1
18BEC0079 KATIKIREDDY SIVA NAGA SAI 2
18BEC0142 KOTA KRISHNA DHEERAJ 3
18BEC0529 KOTA NAVEEN KUMAR 4
18BEC0105 KOTHAPALLI VAMSI PRASAD 5
18BEC0253 KUNDA DUSHYANTH REDDY 6
18BEC0926 LAKSHMI ANCHITHA PANCHAPARVALA 7
17BEC0386 LIKTH S V 8
18BEC0910 MADEM GURU MAHESWAR REDDY 9
17BEC0041 MANOJ GOWDA D 10
18BEC0606 MANUBOLU SRINIVAS REDDY 11
15BEC0391 MENNULU VENKATA DEVARSHA PAVAN AKHIL 12
18BEC0520 MIDDE SURYA NAGA ANIL KUMAR 13
18BEC0215 MUKUL 14
18BEC0636 NAIDU SAI VINAY 15
15BEC0814 NALLURI BHARADWAJ NAGA SAI 16
18BEC0936 NAVEENRAJ K 17
18BEC0488 NELAVELLI SAI MANOJ KUMAR 18
18BEC0841 NIDHI J PATEL 19
18BEC0276 PAGIDALA MD SUHAIL 20
18BEC0712 PAVITHRA CHOWDARY C 21
18BEC0580 POTHALA SATYA VINAY 22
18BEC0667 PRAKHAR DIXIT 23
16BEC0141 PRUDHVI MADUGULA 24
18BEC0286 PUCHAKAYALA SUJAN KUMAR 25
18BEC0984 RAHUL B R 26
18BEC0818 RAJDEEP SAMAL 27
18BEC0913 S AKASH 28
18BEC0186 SABBATHI ANUPAM DIL 29
18BEC0836 SACHIN K S 30
18BEC0525 SAI AKASH CHENNAM 31
18BEC0510 SANDIP HOTA 32
11BEC0486 SANJAY ABRAHAM 33
18BEC0090 SANKA SAI ROHITH 34
18BEC2012 SATYA VENKATA JAGADEESH KONA 35
17BEC0879 SATYAM ANURAG 1
18BEC0691 SAYYAPARAJU MEGHANA 2
15BEC0055 SEELA YESWANTH REDDY 3
18BEC0210 SEGU RITHVIK 4
17BEC0771 SHAANVI MEHTA 5
18BEC0831 SHADAAB AHMAD 6
18BEC2007 SHAIK SUHIL IRSHAD 7
18BEC0236 SHWETANSHU SHEKHAR 8
18BEC2010 SIDDHARTH MEENA 9
17BEC0462 SIDDHARTH S NYAMAGOUDA 10
18BEC0977 SIDDHARTHA HENRY SHAH 11
18BEC2032 SIMRAN SINGH 12
18BEC0576 SUBHRANSU SEKHAR BHATTACHARJEE 13
18BEC0927 SUHAS VETRI A 14
18BEC0630 TAMMINA G V V NAGA SANDEEP 15
18BEC0772 UDAY GUPTA 16
17BEC0155 UJJWAL PRAKASH 17
18BEC0098 UPPU NIKHIL VAMSI 18
18BEC0898 VAIBHAV JAIN 19
18BEC0745 VANTEDDU V SOMA SUNDARA RAO 20
16BEC0363 VIJAY SARAN 21
18BEC0322 VISHAL SINGH 22
18BEC0374 YASH KUMAR SINGH 23
18BEC2025 YINAGER MEKETE ZEWDIE 24