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12 Bit Comparator 32nm

The document discusses the design of a low-power 12-bit digital comparator using a novel multiplexer-based technique. It begins by introducing the importance of low-power circuit design and different logic styles used for comparators. It then describes the operation of a basic 2-bit comparator and reviews existing comparator designs. The document proposes a 12-bit comparator that uses three 4-bit comparator blocks implemented with multiplexers to reduce transistor count. It provides details of the novel two-stage comparator design and implementation.

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08-Phạm Gia Huy
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49 views4 pages

12 Bit Comparator 32nm

The document discusses the design of a low-power 12-bit digital comparator using a novel multiplexer-based technique. It begins by introducing the importance of low-power circuit design and different logic styles used for comparators. It then describes the operation of a basic 2-bit comparator and reviews existing comparator designs. The document proposes a 12-bit comparator that uses three 4-bit comparator blocks implemented with multiplexers to reduce transistor count. It provides details of the novel two-stage comparator design and implementation.

Uploaded by

08-Phạm Gia Huy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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1.

INTRODUCTION
The paper discusses the importance of power consumption in digital CMOS circuits and the
use of different methodologies for designing low-power circuits with small size and
high-speed interfaces. It emphasizes the impact of wiring complexity on the area of an
integrated circuit and the significance of selecting the right logic style for circuit
performance.

The paper presents the design of a 12-bit comparator with low power consumption and
improved packing densities using a multiplexer-based approach and a novel technique. The
design is implemented in 32-nanometer technology with a supply voltage of 0.7 V,
targeting applications such as Digital Signal Processing, Central Processing Unit, and
Microcontroller.

2. TWO-BIT DIGITAL COMPARATOR

In the comparison process, the comparator will check the relative magnitude of two signals
from the position of the most significant bit to the next successive bit position and so on. If
most significant bits are not equal, then it will decide that either A is greater than or less than
B.
Otherwise check for the next successive bit position and goes on till the unequal bit position
occurs [8–9]. Equations (1)–(3) are given to control the outputs of the 2-bit digital comparator
[1–3].

3. REVIEW OF EXISTING TECHNIQUES FOR DIGITAL COMPARATOR DESIGN


The paper discusses the optimization of power consumption, speed, and area in CMOS
comparators, considering the challenges posed by Moore's Law, which dictates the
doubling of transistors in a chip every 18 months. Various logic techniques, such as typical
CMOS, PLT, TG, GDI, and hybrid logic, have been used in different comparator designs with
different transistor counts to achieve low power consumption, high speed, and small
area.

The paper mentions specific examples of two-bit and one-bit comparators designed using
different logic styles, such as PTL, GDI, and CMOS, with varying power consumption, area,
and transistor counts. The proposed multiplexer-based two-bit comparator design is
highlighted as having fewer transistors compared to other comparator designs using CMOS,
PTL, and TG logic techniques.
4. TWO-BIT DIGITAL COMPARATOR USING A MULTIPLEXER

For the implementation of the design procedure using hardware, it requires two sub-block,
where the first block is used to determine the equality of each single-bit data simultaneously
of a 2-bit comparator.

- The first block is formed by using two 2:1 multiplexers.

- The second block is used to determine whether A is less than or equal to B. To


implement the second block of a 2-bit digital comparator, three numbers of 2:1
multiplexers are required.

- Finally, these two outputs A < B and A = B are used as input of an NOR gate to
determine whether A is greater than B or not.

Multiplexer-based N-bit digital comparator is shown in Figure 3. The number of transistors


required to design a N-bit digital comparator is determined by Equation (4).
Number of transistors required = (N + 1) number of IInverter + N number of 2:1 MUX for
block-1 + 2N number of MUX for block-2

5. NOVEL TECHNIQUE FOR HIGH-SPEED DIGITAL COMPARATOR


This novel technique-based 12-bit comparator has three 4-bit comparator blocks which are
operating simultaneously. After the comparison of each comparator blocks, they will
individually decide whether A is less than or equal to B. Output of these three blocks
will finally make a decision whether A is greater than, less than or equal to B by using
Equations (5–7).

6. NOVEL TECHNIQUE-BASED 12-BIT COMPARATOR DESIGN DETAILS


The paper proposes a two-stage structure for designing a 12-bit comparator, where in the
first stage, three 4-bit comparators based on multiplexers are used instead of a single 12-bit
comparator to minimize the number of transistors and gate levels. Each 4-bit comparator
produces individual outputs indicating whether "A" is less than "B" or equal to "B". The output
of a 4-bit comparator is determined using specific equations (8) and (9).

The second stage has been implemented by Equations (5–7) to compute the final outputs of
a 12-bit comparator.
7. CONVENTIONAL CMOS LOGIC-BASED 2-BIT COMPARATOR
Low power and high speed are important factors in digital VLSI circuits, and CMOS is
considered the best alternative due to its low power consumption and high speed. The
conventional CMOS logic-based inverter consists of NMOS and PMOS transistors with their
gates and drains shorted. The CMOS logic style is an extension of CMOS inverters to
multiple inputs.

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