DESIGN OF CMOS CURRENT REUSE LOW NOISE

AMPLIFIER (LNA) USING MODIFIED

Enrollment No. : 19102010,19102023

Name : Shruti Garg , Diwakar Tiwari

Submitted in partial fulfillment of the requirement for the award of Degree of

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

JAYPEE INSTITUTE OF INFORMATION TECHNOLOGY

We here by declare that this submission is our own work and that to the best of our
knowledge and belief, it contains no material previously published or written by another
person nor material which has been accepted for the award of any other degree or
diploma of the university or other institute of higher learning, except where due
acknowledgment has been made in the text.

Place:.............. Signature:.............................
Date:................... Name :..................................

Enrollment :............................

..

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 CERTIFICATE

We hereby declare that the work which is being presented titled,“ DESIGN OF
CMOS CURRENT REUSE LOW AMPLIFIER (LNA) USING MODIFIED
ACTIVE INDUCTOR" in partial fulfillment for the award of degree of Bachelor in
Technology in Electronics and Communication Engineering at Jaypee Institute of
Information Technology, is an authentic record of our own work carried out under the
supervision of Dr . Garima Kapur.

The matter embodied in this work has not been submitted for the award of any other
degree of this or any other university.

Signature of Supervisor :.....................................

Name of Supervisor: ........................................

Designation: .........................................

Date: ..........................................

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 ACKNOWLEDGEMENT

We wish to express our sincere appreciation to our supervisor, Dr. Garima Kapur for her timely,
informative feedback and support during this effort. It has been a great pleasure to learn from her
during the process of our work. She has been a generous mentor ,which also helped us in doing a lot
of research and we came to know about so many new things. We are really thankful to her. We
Would also Like to express very great appreciation to Ma’am.

Last but not least, We thank all of our friends for providing critical feedback & support whenever
necessary .There are times in such projects when the clock beats you time and you run out of energy,
you just want to finish it once and for all, Parents and Friends made us with their unfailing humor &
warm wishes to endure such times.

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 TABLE OF CONTENTS

CHAPTER Page

1. ABSTRACT……….…………….………………………..…………………………. 6

2. INTRODUCTION…………………………………………………………………… 7

3 SCHEMETIC USED………...………… ………………………………… .. 8-11

3.1 Low Noise Amplifier…………………………………………………… 8

3.2 Active Inductor………………………………………………………... 9

3.3 Schematic Diagram……………………………………….............. 10

4. LOW NOISE AMPLIFIER………………………………………………....... . 12-14

4.1 Traditional Aspects…………….………………………………………… 12

4.2.Equation used in simulation……….…………………………………… 13-14

5 ACTIVE INDUCTOR…………………………………………………………… …… 15-16

6. SIMULATION…..…………………………………………………………...…..…. 17-19

7 . CONCLUSION…………………....……………………………………………… 20

8. REFERENCE …………………………………………………………………………… 21

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 CHAPTER-1

ABSTRACT

A low power Low Noise Amplifier (LNA) is proposed using 180nm CMOS technology for the
frequency of 2.6GHz. LNA is designed using current reuse structure where two transistors share same
amount of current. Active inductor is used to replace the passive inductor using modified Gyrator-C
topology. The modified Gyrator-C topology consists of two transconductance stages realized by
common source configuration with multi-regulated cascade stages. Active inductor causes significant
reduction in chip area as compared to the passive ones. The proposed LNA is simulated using cadence
virtuoso in 180nm technology. The LNA has a flat gain at 2.6GHz frequency. The gain obtained by the
LNA is about 17.32dB, noise figure is about 2.62dB. The proposed design gives an input return loss less
than - 17.7823dB and the power consumption is about 5.856mW.

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 CHAPTER - 2

INTRODUCTION

The implementation of advanced silicon Radio Frequency (RF) Integrated Circuits (ICs) is an attractive
option for the constant development of new device designs to meet the demand of wireless systems. Among
these RF ICs, the use of CMOS technology has been shown to be trend. When observing the stages of an RF
IC, the first block of the receiver is usually composed of the low noise amplifier - LNA (Low Noise
Amplifier). Its low intrinsic noise and good gain have fundamental roles on all reception system noise. In the
literature, it is verified that the common source and common port configurations of the CMOS LNAs have the
same properties and limitations of the common emitter and common base configurations of the bipolar
amplifiers. One exception is that for typical RF polarization dimensions and currents, CMOS devices are
more linear than bipolar. . And among these configurations, the common port ends up being deprecated due to
its greater intrinsic noise than the common source (typically 2-3 dB)

. During the development phase of an LNA design, the input impedance can be matched (usually at 50Ω)
using some distinct topologies, such as parallel input resistance, feedback resistance, inductive degeneracy,
among others .The use of resistances resulting in increased noise. On the other hand, inductive degeneration
using Passive Inductors (IPs) has the disadvantage of occupying a very large area in the IC, besides
dependence on the quality factor (Q) of the inductors, which normally do not have satisfactory values.
Despite the listed disadvantages, the inductive degeneration by PIs, since it does not add significant increase
in noise, is the natural choice by most of the area's designers. Such degeneration can be accomplished by the
use of IPs or by the wire bond itself of the CI / board interconnect.. . Several papers have been presented in
the literature exploring the use of IAs in different applications such as: amplifiers, oscillators and filters. The
IAs are used in the LNAs fundamentally to couple the input or output impedances and as active load.

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 CHAPTER 3.

MAIN COMPONENTS:

3.1 LOW NOISE AMPLIFIER(LNA)

LNA is typically the first active stage of a microwave receiver system. Its noise-gain performance affects
the overall receiver's noise figure, and therefore great care must be used during the design phase to
optimize it. Ideally, the LNA's active device should be input-matched to achieve the optimum noise
condition so the amplifier exhibits its minimum noise figure.
A schematic single-stage amplifier is depicted here The typical LNA design flow is as follows: the source
termination is selected to trade off the amplifier's noise, gain, and input matching performance when the
output is considered perfectly matched. This can be accomplished by the corresponding constant noise,
constant available gain, and constant input matching family of circles in the Γ S plane. The intersection
(assuming that it exists) of those three families of circles is drawn on a Smith chart, representing the region
of source complex loads that allows the fulfilment of all the specifications. The S parameter block
represents an active device (biased FET) where some feedback may have been introduced to ease the trade-
off between otherwise contrasting goals (noise, gain, input matching). Input and output matching networks
(IMN and OMN, respectively) are the pair of passive two-port networks in charge of matching the active
device's terminals

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3.2 Active Inductor:

The active inductor is a circuit whose impedance rises with frequency across some frequency range.
Occupying much less area than a passive inductor and offering tunability, such a circuit proves useful
in broadening the bandwidth or realizing other functions that require an inductive element.

Consider the negative-feedback system shown in Figure 2(a), where the feedback network, K, returns a
current to the input. We recognize that feedback lowers the input impedance from Z1 to ( ) Z . KH s Z
1 1 in = + (1) Thus, if H(s) falls as the frequency increases, we expect Zin to rise. While appealing, this
intuition is not accurate because H(s) takes on a complex value and does not simply fall. Nevertheless,
we proceed with this view for now and conclude that a lowpass H(s) or, more generally, a lowpass
KH(s) yields an inductive input impedance. Note that the output of H(s) can be a voltage quantity or a
current quantity. Let us implement the topology of Figure 2(a) at the circuit level. As depicted in
Figure 2(b), we can realize H(s) simply by a first-order low-pass filter and K by a single MOS device.
As explained in the following, proper choice of the element values leads to an inductive Zin.

Fig 1.3 : Schematic Diagram

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3.3 BLOCK AND SCHEMATIC DIAGRAM :

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Fig 1.4 : BLOCK DIAGRAM

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 CHAPTER- 4

LOW NOISE AMPLIFIER

4.1 TRADITIONAL ASPECTS:

LNA is typically the first active stage of a microwave receiver system. Its noise-gain performance affects the
overall receiver's noise figure, and therefore great care must be used during the design phase to optimize it.
Ideally, the LNA's active device should be input-matched to achieve the optimum noise condition so the
amplifier exhibits its minimum noise figure.
A schematic single-stage amplifier is depicted in figure . The S parameter block represents an active device
(biased FET) where some feedback may have been introduced to ease the trade-off between otherwise
contrasting goals (noise, gain, input matching). Input and output matching networks (IMN and OMN,
respectively) are the pair of passive two-port networks in charge of matching the active device's terminals.

The typical LNA design flow is as follows: the source termination is selected to trade off the amplifier's
noise, gain, and input matching performance when the output is considered perfectly matched. This can be
accomplished by the corresponding constant noise, constant available gain, and constant input matching
family of circles in the ΓS plane.

The intersection (assuming that it exists) of those three families of circles is drawn on a Smith chart,
representing the region of source complex loads that allows the fulfillment of all the specifications.
Conversely, if a trade-off between the input and output matching is a target in the specification table—i.e., a
better input match although not with a perfect match at the output—a blind optimization step has to be
considered, unless more sophisticated approaches (such as those detailed in the following sections) are
known to the designer.

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4.2 Equations Used for Simulation

where,
Cgs: Gate-to-source capacitance of M1,
gm: Transconductance of M1,
Rl: Parasitic resistance of Lg and LS
R0: Sheet resistance of the gate poly silicon
η: Number of gate fingers of M1
Rg: Effective gate resistance of the NMOS transistor M1
W and L: The total gate with and length of device
μeff, εsat and Cox represent the field-limited electron mobility, the saturation electric field and the gate
oxide capacitance per unit area.
P0: Power dissipation (P0 = IdVsup ply).

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 The current reuse topology may provide the best combination of high power gain, low noise figure, and
low power consumption, making it a feasible option for use in UWB LNA designs. In an amplifier
employing current-reuse techniques, the input RF signal is amplified by two cascaded common-source
amplifier stages to provide high gain. Simultaneously, this topology also supports low noise figures. The
input matching circuitry is aided with the help of a high-pass filter to suppress noise. The basic issue with
using CMOS transistor for LNA is its inherently low transconductance and hence low gain. However, if
current reuse method is used, transconductance would be increased. The key point is that given the same
bias current the effective transconductance is gm1×gm2, while it is simply gm in other cases. Single source
results in less power dissipation.

The current reuse model can be considered as a two stage cascade amplifier, in which the first stage is the
CS amplifier and the second stage is the cascode amplifier with an additional buffer stage at output end.The
current reuse technique is well known for its use in LNAs, for its capability of achieving high performance
with power consumption that is less than conventional two-stage common-source amplifiers. The fig. shows
a current reused LNA.

The input impedance is to be matched to 50Ώ and equating real and imaginary terms in Eqn (1) to find
the values of source inductor Ls, gate inductor Lg and the capacitance Cd. The parameters Ls, Lg and Cd

adjusted to obtain the perfect input impedance matching.

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 CHAPTER -5

ACTIVE INDUCTOR :

The design of active inductor is studied using gyrator-C circuit given the figure .When one port of the
gyrator is connected to a capacitor, the network is calledthe gyrator-C network. A gyrator-C network is said
to be lossless when both theinput and output

impedances of the trans conductors of the network are infinite and the trans conductances of the
transconductors are constant. Gyrator-C networks can therefore be used to synthesize inductors.

Fig : Gyrator C Active inductor

Fig: Equivalent Gyrator C circuit

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The equation for inductance for gyrator-C circuit is given by:

The equation for quality factor is given by

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 CHAPTER 6
SIMULATION :-

Fig : Complete working model

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OUTPUT GRAPHS :

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 CHAPTER 7

CONCLUSION :

The presented LNA uses the current-reuse technique in order to improve performance The
g gate inductor of LNA is replaced by an active inductor in order to reduce the integrated are
This LNA shows a proper input matching at 2.6GHz. The gain of the proposed LNA is about
1 18.45 dB, noise figure is 2.67dB, input return loss is -17.14 dB and power consumption is a
a about 7.09 mW. It can be used for small satellite ground stations

This work can be further improved in future by scaling down to less than 180nm which
promipromises sharper gain, increase in performance and lesser integrated area. All the passive I
nductinductors in LNA can be replaced by active inductors which can further reduce the chip area
a and noise figure. The LNA can also be used in wide range of frequencies.

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 CHAPTER 8

REFERENCES

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