COA Lab Manual

JSS MAHAVIDYAPEETHA
LABORATORY MANUAL
Subject Name: Computer Organization Lab
Subject Code: KCS 352
COURSE : B.Tech SEMESTER : III SEM
Name
Roll No.
Section-Batch
Department of Computer Science and Engineering

JSS ACADEMY OF TECHNICAL EDUCATION
C-20/1, SECTOR-62, NOIDA
JSS Academy of Technical Education – NOIDA
Department of Computer Science & Engineering
VISION OF THE INSTITUTE
JSS Academy of Technical Education Noida aims to become an Institution of excellence in

imparting quality Outcome Based Education that empowers the young generation with
Knowledge, Skills,Research, Aptitude and Ethical values to solve Contemporary
Challenging Problems.
MISSION OF THE INSTITUTE
• Develop a platform for achieving globally acceptable level of intellectual acumen and
technological competence.
• Create an inspiring ambience that raises the motivation level for conducting quality
research.
• Provide an environment for acquiring ethical values and positive attitude.
VISION OF THE DEPARTMENT
To spark the imagination of the Computer Science Engineers with values, skills and
creativity to solve the real world problems.
MISSION OF THE DEPARTMENT
• To inculcate creative thinking and problem solving skills through effective teaching,
learning and research.
• To empower professionals with core competency in the field of Computer Science and
Engineering.
• To foster independent and life long learning with ethical and social responsibilities.
PROGRAM EDUCATIONAL OUTCOMES (PEOs)
PEO1: To empower students with effective computational and problem solving skills.
PEO2: To enable students with core skills for employment and entrepreneurship.
PEO3: To imbibe students with ethical values and leadership qualities.
PEO4: To foster students with research oriented ability which helps them in analyzing and
solving real life problems and motivate them for pursuing higher studies.
Computer Organization Lab (KCS-352) Manual (CS, III SEM) Page 2

PROGRAM OUTCOMES (POs)
Engineering Graduates will be able to:
PO1: Engineering knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals, and an engineering specialization to the solution of
complex engineering problems.
PO2: Problem analysis: Identify, formulate, review research literature, and

analyze complex engineering problems reaching substantiated conclusions using
first principles of mathematics, natural sciences, and engineering sciences.
PO3: Design/development of solutions: Design solutions for complex

engineering problems and design system components or processes that meet the
specified needs with appropriate consideration for the public health and safety, and
the cultural, societal, and environmental considerations.
PO4: Conduct investigations of complex problems: Use research-based

knowledge and research methods including design of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid conclusions.
PO5: Modern tool usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction and modeling to
complex engineering activities with an understanding of the limitations.
PO6: The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.
PO7: Environment and sustainability: Understand the impact of the professional

engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
PO8: Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
PO9: Individual and team work: Function effectively as an individual, and as a

member or leader in diverse teams, and in multidisciplinary settings.
PO10: Communication: Communicate effectively on complex engineering activities

with the engineering community and with society at large, such as, being able to

comprehend and write effective reports and design documentation, make effective
presentations, and give and receive clear instructions.
PO11: Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply these to
one’s own work, as a member and leader in a team, to manage projects and in
multidisciplinary environments.
PO12: Life-long learning: Recognize the need for, and have the preparation and
ability to engage in independent and life-long learning in the broadest context of
technological change.
PROGRAM SPECIFIC OUTCOMES (PSOs)
PSO1: An ability to apply foundation of Computer Science and Engineering, algorithmic

principles and theory in designing and modeling computation based systems.
PSO2: The ability to demonstrate software development skills.

COURSE OUTCOMES (COs)
C 228.1 Implementation of various combinational circuits using IC’s

C 228.2 Implementation of various code convertors, multiplexers, encoders and decoder
using IC’s
C 228.3 Designing and verification of Flip Flops
C 228.4 Designing of I/O using Registers, ALU and Control Unit and demonstrating the
usage of Register Transfer Language(RTL)
C 228.5 Implementation of Matrix Multiplication on multi -processor system and study of
scalability of multiprocessor systems.
CO-PO MAPPING
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
C 228.1 3 3 3 1 1 1 1 1 2 1 2 2
C 228.2 3 3 3 1 1 1 1 1 2 1 1 2
C 228.3 3 3 3 1 3 1 1 1 2 1 1 1
C 228.4 3 3 3 1 3 1 1 1 2 1 1 1
C 228.5 3 3 3 1 2 1 1 1 2 1 1 2
CO-PSO MAPPING
PSO1 PSO2
C 228.1 -
1
C 228.2
1 -
C 228.3 1 -
C 228.4 1 -
C 228.5 1 -

LIST OF EXPERIMENTS
Sr. Title of experiment Corresponding

No. CO
Verification of Logic Gates C 228.1
1.
Implementing HALF ADDER, FULL ADDER using basic C 228.1
2.
logic gates.
Implementing Binary -to -Gray, Gray -to -Binary code C 228.2
3.
conversions.
Implementing 3-8 line DECODER C 228.2
4.
Implementing 4x1 and 8x1 MULTIPLEXERS. C228.2
5.
Verify the excitation tables of various FLIP-FLOPS. C 228.3
6.
Design of an 8-bit Input/ Output system with four 8-bit C 228.4
7.
Internal Registers.
Design of an 8- bit ARITHEMATIC LOGIC UNIT. C 228.4
8.
Write an algorithm and program to perform matrix C228.5
9.
multiplication of two n * n matrices on the 2-D mesh SIMD
model, Hypercube SIMD Model or multiprocessor system.
Study of Scalability for Single board Multi-board, multi-core, C228.5

10.
multiprocessor using Simulator.
Content Beyond Syllabus
Implementing HALF SUBTRACTOR and FULL C 228.1
11.
SUBTRACTOR using basic logic gates
Design and Implement SISO and SIPO Shift Registers C 228.4
12.
Design and Implement PISO and PIPO Shift Registers C 228.4
13.

JSS ACADEMY OF TECHNICAL EDUCATION
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
COMPUTER ORGANIZATION LAB FILE (RCS 352)
Name
Roll No.
Section- Batch

EXPERIMENT 1
Aim: Verification of logic gates
Equipment Required & Component Required:
S.No. Equipments Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1
S.No. Components Specification Quantity

7400, 7402, 7404,
1 each
1 Digital ICs 7408, 7432, 7486.
- 6
2 Patch cords
Theory:
• Details of IC used and pin configurations.
• Working of logic gates.
1. OR GATE:
VCC
14
14 13
13 12 11
11 10
10 99 88
11 22 33 44 55 66 77
GND
PIN CONFIGURATION OF 74LS32
TRUTH TABLE OBSERVATION TABLE
INPUT A INPUT B OUTPUT Y INPUTS OUTPUT USING USING LED
0 0 0 A B VOLTMETER
- - -
0 1 1
- - -
1 0 1 - - -
1 1 1 - - -

2. AND GATE:
VCC
14
14 13
13 12
12 11
11 10
10 99 88
11 22 33 44 55 66 77

GND
INPUT A INPUT B OUTPUT Y INPUTS OUTPUT USING USING
A B VOLTMETER LED
0 0 0
0 1 0 - - -
1 0 0 - - -
1 1 1 - - -
- - -
3. NOT GATE:
VCC
14 13 12 11 10 9 8
1 2 3 4 5 6 7
GND

OUTPUT INPUTS OUTPUT USING USING LED
INPUT A
Y A B VOLTMETER
0 1 - - -
1 0 - - -

4. NOR GATE

INPUT INPUT OUTPUT INPUTS OUTPUT USING LED
A B Y USING
0 0 1 A B
VOLTMETER
0 1 0 - - -
1 0 0 - - -
1 1 0 - - -
- - -
5. NAND GATE:

INPUT INPUT OUTPUT INPUTS USING LED
OUTPUT USING
A B Y
A B VOLTMETER
0 0 1
- - -
0 1 1 - - -
1 0 1 - - -
1 1 0 - - -

6. EX-OR GATE:
PIN CONFIGURATION OF 7486

INPUT INPUT OUTPUT INPUTS OUTPUT USING LED
A B Y USING
0 0 0 A B
VOLTMETER
0 1 1 - - -
1 0 1 - - -
1 1 0 - - -
- - -
Procedure:
1. Identify the pin no’s of the given IC.
2. From the IC No. Find out the type of gate.
3. Check for the proper working of the gate.
4. Connect the circuit as per circuit diagram.
5. For all combination of input condition. Tabulate the output voltage by connecting a
voltmeter at the output end.
6. Verify it with truth Table.
7. Repeat the above procedure for all gates.
Result & Conclusion: All Logic Gates are verified.

EXPERIMENT 2
Aim: Design and implementation of HALF ADDER, FULL ADDER using basic logic
gates
Equipment & Components Required:


7400, 7402,
7404,
1 each
1 Digital ICs 7408, 7432,
7486.
- 6
2 Patch cords
Theory:
a) To design and implement half adder using logic gates
HALF ADDER
OUTPUTS
INPUT A INPUT B
S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
CIRCUIT DIAGRAM TRUTH TABLE

b) To design and implement full adder using logic gates
FULL ADDER
CIRCUIT DIAGRAM
TRUTH TABLE
Procedure:
• Identify the pins.

• Connect the circuit as per circuit diagram.

• Obtain outputs with various input combinations.
• Verify it with the Boolean function using truth table
Result & Conclusion: All logical circuits have been implemented & verified through truth
table.

EXPERIMENT 3
Aim: Design and implementation of Binary to Gray, Gray to Binary Code conversions


7400, 7402,
7404,
1 each
7486.
- 6
2 Patch cords
Theory:
a) To design and implement Binary to Gray Code conversions
Pin diagram of Binary to gray code converter using 7486 Ic(Exor Gate)

INPUTS OUTPUTS
A B C D G4 G3 G2 G1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
Circuit Diagram of
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
Binary to Gray Code Converter 1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Truth Table
b) To design and implement Binary to Gray Code conversions
Pin diagram of Gray to Binary code converter using 7486 Ic(Exor Gate)

INPUTS OUTPUTS
A B C D B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
Circuit Diagram for Gray to Binary Code
1 0 1 0 1 1 0 0
Converter
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
T Truth Table
Procedure:
• Collect the components necessary to accomplish this experiment.
• Plug the IC chip into the breadboard.
• Connect the supply voltage and ground lines to the chips. PIN7 = Ground and PIN14
= +5V.
• Make connections as shown in the respective circuit diagram.
• Connect the inputs of the gate to the input switches of the LED.
• Connect the output of the gate to the output LEDs.
• Once all connections have been done, turn on the power switch of the breadboard
• Operate the switches and fill in the truth table (Write "1" if LED is ON and "0" if L1
is OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.
Result & Conclusion: Binary to gray and gray to binary code converter has been designed
using EXOR gate and its truth table verified.

EXPERIMENT 4
Aim: Design and implementation of 3-8 line DECODER

Equipment’s & Components Required:
S.No. Equipment’s Specification Quantity


7400, 7402,
7404,
1 Digital ICs 1 each
7408, 7432,
7486.
2 Patch cords - 6
Theory:
a) 4 to 2 encoder using logic gates:
Truth Table Logic Diagram:
I3 I2 I1 I0 O1 O0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
b) 3 to 8 decoder using logic gates:
Symbol: Truth table:

Logic Diagram of 3 to 8 decoder
Procedure:
• Connect the supply voltage and ground lines to the chips. PIN7 = Ground
• and PIN14 = +5V.
• Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if L1
is OFF Apply the various combination of inputs according to the truth tabe and obseve
the condition of Output LEDs.
Result & Conclusion: 3-8 line decoder has been implemented & verified through truth table.

EXPERIMENT 5
Aim: Design & implement a 4x1 MUX and 8x1 MULTIPLEXERS


7400, 7402, 7404,
7408, 7432, 7486.
2 Patch cords - 6
Theory:
a) 4 to 1 Multiplexer:
Symbol: Truth table:
Addressing
Input
Selected
b a
0 0 A
0 1 B
1 0 C
1 1 D

Logic Diagram:
b) 8x1 Multiplexer
Pin diagram of 8:1 Mux using two 4:1 Mux

Circuit of 8:1 Mux using dual 4:1 Mux
Truth Table of 8:1 Mux Using Dual 4:1 Mux
Select Lines Inputs Output

Ea S0 S1 Io I1 I2 I3 I4 I5 I6 I7 Za Zb Y
0 0 0 0 × × × × × × × 0 × 0
0 0 0 1 × × × × × × × 1 × 1
0 0 1 × 0 × × × × × × 0 × 0
0 0 1 × 1 × × × × × × 1 × 1
0 1 0 × × 0 × × × × × 0 × 0
0 1 0 × × 1 × × × × × 1 × 1
0 1 1 × × × 0 × × × × 0 × 0
0 1 1 × × × 1 × × × × 1 × 1
1 0 0 × × × 0 × × × × 0 0
1 0 0 × × × × 1 × × × × 1 1
1 0 1 × × × × × 0 × × × 0 0
1 0 1 × × × × × 1 × × × 1 1
1 1 0 × × × × × × 0 × × 0 0
1 1 0 × × × × × × 1 × × 1 1
1 1 1 × × × × × × × 0 × 0 0
1 1 1 × × × × × × × 1 × 1 1

Procedure:
• and PIN14 = +5V.
is OFF Apply the various combination of inputs according to the truth tabe and obseve
the condition of Output LEDs.
Result & Conclusion: 4 to 1 & 8 to 1 multiplexer has been implemented & verified through
truth table.

EXPERIMENT 6
Aim: Verify the excitation table of various FLIP-FLOPS
Equipments & Components Required:

3. Components Required:
7400, 7402, 7404,
7408, 7432, 7486.
2 Patch cords - 6
Theory:
Flip-flops are synchronous bistable devices. The term synchronous means the output changes
state only when the clock input is triggered. That is, changes in the output occur in
synchronization with the clock. A flip-flop circuit has two outputs, one for the normal value
and one for the complement value of the stored bit. Since memory elements in sequential
circuits are usually flip-flops, it is worth summarizing the behavior of various flip-flop types
before proceeding further. All flip -flops can be divided into four basic types: SR, JK, D and
T. They differ in the number of inputs and in the response invoked by different value of input
signals. The four types of flip -flops are defined in the Table below.
Circuit Diagram


Procedure:
• and PIN14 = +5V.
is OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.
Result & Conclusion: Verified excitation table of various flip flops.

EXPERIMENT 7
Aim: Design and implement 8-bit Input/Output System with four 8-bit internal registers

1 Logic Simulator - 1
S.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 15
Theory:
A register is capable of shifting its binary information in one or both directions is known as
shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common
clock pulses which causes the shift in the output of the flip flop.The simplest possible shift
register is one that uses only flip flop. The output of a given flip flop is connected to the input
of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.
LOGIC DIAGRAM:
8-bit Input/Output System with four 8-bit internal register

Procedure:
• Connections are given as per circuit diagram.
• Logical inputs are given as per circuit diagram.
• Observe the output and verify the truth table.
Result & Conclusion: Verified 8-bit Input/Output System with four 8-bit internal registers
on simulator.

EXPERIMENT 8
Aim: Design of an 8- bit ARITHMETIC LOGIC UNIT.

Theory:
ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition,
subtraction, division, multiplication and logical operations like and, or, xor, nand, nor etc. A
simple block diagram of a 4 bit ALU for operations and, or, xor and Add is shown in the
Logic diagram.
LOGIC DIAGRAM:
Block diagram of a 4 bit ALU

Design Issues :
The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal S1
and S0 the circuit operates as follows:
for Control signal S1 = 0 , S0 = 0, the output is A And B,
for Control signal S1 = 0 , S0 = 1, the output is A Or B,
for Control signal S1 = 1 , S0 = 0, the output is A Xor B,
for Control signal S1 = 1 , S0 = 1, the output is A Add B.
The truth table for 16-bit ALU with capabilities similar to 74181 is shown here:
Required functionality of ALU (inputs and outputs are active high)

Mode Select Fn for active HIGH operands
Inputs Logic Arithmetic (note 2)
S3 S2 S1 S0 (M = H) (M = L) (Cn=L)
L L L L A' A
L L L H A'+B' A+B
L L H L A'B A+B'
L L H H Logic 0 minus 1
L H L L (AB)' A plus AB'
L H L H B' (A + B) plus AB'
L H H L A⊕B A minus B minus 1
L H H H AB' AB minus 1
H L L L A'+B A plus AB
H L L H (A ⊕ B)' A plus B
H L H L B (A + B') plus AB
H L H H AB AB minus 1
H H L L Logic 1 A plus A (Note 1)
H H L H A+B' (A + B) plus A
H H H L A+B (A + B') plus A
H H H H A A minus 1
L denotes the logic low and H denotes logic high.
Procedure:
Result & Conclusion: Verified the design of an 8 bit ALU.

EXPERIMENT 9
Aim: To write an algorithm and program to perform matrix multiplication of two n * n

matrices on the 2-D mesh SIMD model, Hypercube SIMD Model or multiprocessor
system.

Theory:
Mesh Network: A set of nodes arranged in the form of a p dimensional lattice is called a mesh
network. In a mesh network only neighboring nodes can communicate with each other.
Therefore, interior nodes can communicate with 2p other nodes.
ALGORITHM:
Algorithm
Procedure MATRIXMULT
begin
for k = 1 to n-1 step 1do
begin
for all Pi,j where i and j ranges from 1 to n do
if i is greater than k then
rotate a in the east direction
end if
if j is greater than k then
rotate b in the south direction
end if
end
for all Pi,j where i and j lies between 1 and n do
compute the product of a and b and store it in c
for k= 1 to n-1 step 1 do

for all Pi,j where i and j ranges from 1 to n do rotate a in the east rotate b in the south
c=c+aXb end
HYPERCUBE ALGORITHM
Procedure:
• Write an algorithm on Mesh networks
Result & Conclusion: Designed an algorithm and program to perform matrix multiplication of
two n * n matrices on the 2-D mesh SIMD model, Hypercube SIMD Model or multiprocessor
system

EXPERIMENT 10
Aim: To study the Scalability for Single board, Multi-board, multi-core, multiprocessor
using Simulator
SL.No. Equipments Specification Quantity

Theory:
A multi-core processor is a single computing component with two or more
independent processing units called cores, which read and execute program instructions. The
instructions are ordinary CPU instructions (such as add, move data, and branch) but the single
processor can run multiple instructions on separate cores at the same time, increasing overall
speed for programs amenable to parallel computing. Manufacturers typically integrate the
cores onto a single integrated circuit die (known as a chip multiprocessor or CMP) or onto
multiple dies in a single chip package.
Diagram of a generic dual-core processor with CPU-local :-
A multi-core processor implements multiprocessing in a single physical package. Designers

may couple cores in a multi-core device tightly or loosely. For example, cores may or may
not share caches, and they may implement message passing or shared-memory inter-core

communication methods. Common network topologies to interconnect cores

include bus, ring, two-dimensional mesh, and crossbar. Homogeneous multi-core systems
include only identical cores; heterogeneous multi-core systems have cores that are not
identical (e.g. big.LITTLE have heterogeneous cores that share the same instruction set,
while AMD Accelerated Processing Units have cores that don't even share the same
instruction set). Just as with single-processor systems, cores in multi-core systems may
implement architectures such as VLIW, superscalar, vector, or multithreading.
Multiprocessor :-
A multiprocessor is a computer system with two or more central processing units (CPUs),
with each one sharing the common main memory as well as the peripherals. This helps in
simultaneous processing of programs.
The key objective of using a multiprocessor is to boost the system’s execution speed, with
other objectives being fault tolerance and application matching.
A good illustration of a multiprocessor is a single central tower attached to two computer
systems. A multiprocessor is regarded as a means to improve computing speeds, performance
and cost-effectiveness, as well as to provide enhanced availability and reliability.
Scalibilty :-
Flynns Classification of multiprocessor machines:

1. SISD = Single Instruction Single Data

2. SIMD = Single Instruction Multiple Data ( Array Processors or Data Parallel machines)
3. MISD does not exist.
4. MIMD = Multiple Instruction Multiple Data Control
Procedure:
• Study various case study related to multi processors.
Result & Conclusion: Study of case study of Multi processors.

EXPERIMENT 11
Aim: Design and implementation of HALF SUBTRACTOR, FULL SUBTRACTOR

using basic logic gates.


7400, 7402,
7404,
1 each
7486.
- 6
2 Patch cords
Theory:
a) To design and implement half Subtractor using logic gates
HALF SUBTRACTOR
INPUTS OUTPUTS
A B BIN D BOUT
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
b) To design and implement full subtractor using logic gates

FULL SUBTRACTOR
OUTPUTS
INPUT X INPUT Y
D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Procedure:
• Identify the pins.
• Connect the circuit as per circuit diagram.
• Obtain outputs with various input combinations.
• Verify it with the Boolean function using truth table
Result & Conclusion: All logical circuits have been implemented & verified through truth
table.

EXPERIMENT 12
Aim: Design and implementation of SISO and SIPO shift registers

SL.No. Equipments Specification Quantity

1 Logic Simulator -
Sl.No. COMPONENT SPECIFICATION QTY.

4. PATCH CORDS - 15
Theory:
clock pulses which causes the shift in the output of the flip flop. The simplest possible shift
to right.
LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:
TRUTH TABLE:
Serial in Serial out
CLK
1 1 0

2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
SERIAL IN PARALLEL OUT:
TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
Procedure:
Result: All Shift registers have been implemented & verified through truth table.

EXPERIMENT 13
Aim: Design and implementation of PISO and PIPO shift registers

1 Logic Simulator -
S.No. COMPONENT SPECIFICATION QTY.

4. PATCH CORDS - 15
Theory:
clock pulses which causes the shift in the output of the flip flop.The simplest possible shift
to right.
LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:

TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
PARALLEL IN PARALLEL OUT:
TRUTH TABLE:
DATA INPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
Procedure:
Result & Conclusion: All shift registers have been implemented & verified through truth
table.

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JSS MAHAVIDYAPEETHA

Subject Name: Computer Organization Lab

Subject Code: KCS 352

COURSE : B.Tech SEMESTER : III SEM

Department of Computer Science and Engineering

VISION OF THE INSTITUTE

JSS Academy of Technical Education Noida aims to become an Institution of excellence in

MISSION OF THE INSTITUTE

• Provide an environment for acquiring ethical values and positive attitude.

VISION OF THE DEPARTMENT

MISSION OF THE DEPARTMENT

PROGRAM EDUCATIONAL OUTCOMES (PEOs)

Computer Organization Lab (KCS-352) Manual (CS, III SEM) Page 2

PROGRAM OUTCOMES (POs)

Engineering Graduates will be able to:

PO1: Engineering knowledge: Apply the knowledge of mathematics, science,

PO2: Problem analysis: Identify, formulate, review research literature, and

PO3: Design/development of solutions: Design solutions for complex

PO4: Conduct investigations of complex problems: Use research-based

PO7: Environment and sustainability: Understand the impact of the professional

PO9: Individual and team work: Function effectively as an individual, and as a

PO10: Communication: Communicate effectively on complex engineering activities

Computer Organization Lab (KCS-352) Manual (CS, III SEM) Page 3

PROGRAM SPECIFIC OUTCOMES (PSOs)

PSO1: An ability to apply foundation of Computer Science and Engineering, algorithmic

PSO2: The ability to demonstrate software development skills.

Computer Organization Lab (KCS-352) Manual (CS, III SEM) Page 4

COURSE OUTCOMES (COs)

C 228.1 Implementation of various combinational circuits using IC’s

Computer Organization Lab (KCS-352) Manual (CS, III SEM) Page 5

Sr. Title of experiment Corresponding

Study of Scalability for Single board Multi-board, multi-core, C228.5

Computer Organization Lab (KCS-352) Manual (CS, III SEM) Page 6

JSS ACADEMY OF TECHNICAL EDUCATION

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

COMPUTER ORGANIZATION LAB FILE (RCS 352)

Computer Organization Lab (KCS-352) Manual (CS, III SEM) Page 7

Aim: Verification of logic gates

Equipment Required & Component Required:

S.No. Equipments Specification Quantity

S.No. Components Specification Quantity

Computer Organization Lab (KCS-352) Manual (CS, III SEM) Page 8

PIN CONFIGURATION OF 74LS08

TRUTH TABLE OBSERVATION TABLE

Computer Organization Lab (KCS-352) Manual (CS, III SEM) Page 9

TRUTH TABLE OBSERVATION TABLE

PIN CONFIGURATION OF 74LS00

TRUTH TABLE OBSERVATION TABLE

Computer Organization Lab (KCS-352) Manual (CS, III SEM) Page 10

PIN CONFIGURATION OF 7486

TRUTH TABLE OBSERVATION TABLE

Result & Conclusion: All Logic Gates are verified.

Computer Organization Lab (KCS-352) Manual (CS, III SEM) Page 11

Equipment & Components Required:

S.No. Equipments Specification Quantity

S.No. Components Specification Quantity

a) To design and implement half adder using logic gates

CIRCUIT DIAGRAM TRUTH TABLE

Computer Organization Lab (KCS-352) Manual (CS, III SEM) Page 12