80 86 Avchitectuve

Memoyy
Inteaface
Bus

B
U.
ES
CS
SS Intssuchon Byte
DS
ueue2
IP

Decodes
ConoL
Unit
Bus

AH AL AX
E. BH eL Bx
U. CH CL Cx
DH DL

SP
DX
ALUCI6)/
BP
SI
OpecGnds
FLAGS (16)

Features_of 8o86 Micwprocessor

) 3 t isa 16 bit up with 40 pin ducl in pocKage
) 9 t has 16 bit mutiplexed data bus ADo- ADIS
cohich acess
9t hos 20 bit gddreSS bus ( A o ~A19) can

220 memoTy location ( LMB memoTH).

)8o86 Can support 64k (2l6) I/o posts.
*)9+ has 14 Megistes of 16 bit Sige.
fsommemorH)
*)9+ hos 6 byte in shsuchon Sue ue C Psefete hed
speed uP exe ufm
o r d e n to
Mazimum and minimum made)
) 9t opesates 1o 2 mod es (
) 9t requives +sv Supply. Unit 4Execuhaunjt.
sructure 1s divjded Bus lntnface
)Interal
Ihe 8o86 Micsoprocessos aschite cture is divided 1oto two pais
)Bus Intesface Unit (BIU) 9t contoins tollooing component s

Cs,DS,ES SS Sgment Hegisters of 16 bit

4
P * ) 1 Instouchon poIntej dcgis of 16bit
)Addes to geneafe 20 blt addhess
)6byte 1isuchion ueye
)Data, address and Cenldl buses

The BIU perfoums f|louding tosks -

)Fetches Insruchon om memosy

*)Reads dats fs om memoTY TO
funchons of BiU
W t s datg som memory to .

)seneafe 2obit emory addresS

unit contoins follouoing pavs
funchnal
) Execution Unit (EU) - This

k)4 Genesal puspose sHeqk lps16 bi

CAx, Bx CX and Ox)
)16 bit Flag egicte>
*) Contsdl Cincuit wih 1srucie)
decode
) pointe (sP 9 BP) and Index (Si,DI)
16 bit
HegistesS of
.

) Asithmetic and logical Unit (ALu)

¥) sysl&m byses
The executin uojt þeatosms tollowing tasks
9 + tel|s 8IU that som when Coele dek
funchions of EU hasto ae fttchad
execuhm
Decoding ot 1Östsuchcn and
Pipeling in 8o86 -
to give he 8o&6 on

66 Both BIU a d EU operates asynchronouslpomechan01Sm cohich is

execuhon
19ssuehon fetch and
oveslppi
non as Pipelining
Non pipe line 1 8o8S -
)10 4clock ycls
Fetch1 Exe.L Fetch 2 Exec2 2 1suc
eiecuted
TL T2 Ts Tt
Fetch4 Exec 1
Fetch 2 Exec 2 3 10sbychens
Fetch 3 &xec.3| e e cuted

Pipelined 1&o&6
This fe tching is perfomed 1 810 oh1le ijsub
*) Hhis Codo bytë k Stored
Isgethig execufed
s chm yeue C1)
 Register Organisation of 80g86
genesal Puspose Registers- C Al are 16 bit negistes)
( A L l Can be used as 8 bit registers)
Ax-
)16 bit Accumulator egistes
prefessed registea to use in aath metic, logical ond
data tronsfes IHStSucHon
*) Must be used tn Multipliation ond division opea tin
Default SHegi'ste tos zlo Telated opeaation S.

Bx- H8bit BL]

8bit
Bx C16 bit)

*) Base regrstes ( Bx) Con be used as genesol puspose vegiste.

) t is also used to hold offset address i Some qddressi
modes
Cx- CH Cx ( 16 bit)
8bit 8bit
* Count Hegisfes
counte> 1o Case of sing ond loop InSsucHns
) . 9 t is us ed as

Dx- DH DL Dx (16 bir)

8 bit 8bit

*Datg e s t e 1s generaL puspose registe.

a

Used In multiplicathon ond divisic) operahms

more than 16 bit gre here)
AlsO used i0 Ilo operahons ( {
bit
Sgmet registers of
16
8086 has 4
Segment Reaistes -X a
9t s Uscd to addresS memosH
Code Segment (cs) Registes- of the
location i the code segment
ohese e x e c u t g b l e progoms
memoH,
are sfored
-8 9t points The data Segment postion of
Data Segment (Ds) Registe the memosH ,ohele general
data is

StoredL
qddress of q
This egistes Phovides
Segment (ES) Regístes- 1n the e x t
memorH l o c a n preSent
Exhra
extsa
he
segment of the memosy
Contqins eneal dats
Segment memoTy
Ths registes. is used point
to a memory
stack sgment( ss) Reqishel-
locaton in the stock Spgment of
memoYy
Helated to Subroutrhg
which holds Hhe datq

staThhg address of Hheih

)The Segment negisters povide only Hhe
hespech ve sogments.
ExP he code Segment 1s of 64 KB so

t has 26 Locat ms
Let C.S regSteL = 234 H
cS (64KB)
Then Stastng add-ress ef Code ss ment
ill be
123 40 H starhn9 et
this nibble (4bits) Code segmet
Contoins O OoDo
cohich must be added cohie cal culathng address
oF any segment are
*Eoch will bits
segment
qddress
tegiste
4 ZeroS must
hove
be added at
l6 cohile calulathng 20bi
lowe nibble to ma ke the
adedresS 20 bit.

Pointe and Index RegistesS-

contoins 16 bit offset address
Tnstruehon Pointe (IP) 9t glways -

of code segment area

et Cs 1234 H
Code segment CGG KB
FFFFH
These a r e 26 ocahins (
Cohose address will be
ven by josyeHm poo k
are knoLwN ag3
hese
PHSt addresS "
OooOH J12340oH S The storh9
odo Seqmet
f I P 0120 H addre SS of
addrese i l l be
The memory
CS fo 2 34 OH
H
IP O 2O ohich is
Actuol addsess ofoihió the o de Segment.
memoTY
o H
1 24 6 IP
pointed by
Base Pointes
Base and stack
Pointes CBP 4 SP) -2 1)

Contains offset address fos Stock Segment.

)Bose pointes
)BP can also
holds oH'et address fus ohe Segments C DS, 6s)
BP is o 16 bit
) contains ofet address fr stock
PointeL - 9t always
Stack Segrmet memory artqa.

4 DI)-
ndex Regicteh (3I gddress of Datq segment during
S1)-8 *) S1 holds ofset
Source Index (
string op esanon
Data segment octs 9 s
*) Duain9 stsing operathm
Source ot data
Durin9 strng opeation Exrq Segment (ES)
Destinaton Tncex CDT) DI
gct os destinati) of data , so the
provides offset address forr ES
Code Seg ment Tepreetahm -% added loweh
nibole(OH)
et CsReg 348A H
2/4 H
IP Rag= 4 A 8
3 4
Memo CS
IP 42 4
Physica 38A B 4
adaress (0 blh) End of 2 0 b i t adds-
Code S e g m e n t
Code byle

38AB4 H Code PTe

IP 4214H

Stort ot Hhe Code Segonent

address)
348AOH
CS= 348A H(Stas
hng

and Computah'c
20 bit address fosmaha) diagsam
Ha8-
also
Explain OTher Segsments
simloy we Con

Stack Segment representachn-3

physita
Hhe ctack
afdress (obit) Top of

SFFEO H- Data

SP FFEOoH

start of S s
added lowe 5 0000 H -V
hibble (oH) SS 5o00H

SS: 5 0 oolol H
SP FFFE H
5FFFE H physial add ress Sats
 The Segment Re9iste
To
oHfset Registes. will funchon togeTh e
generote 20 bit addre sS.
CS IP Psogom Code
DS Bx
General Data
SI
SOurce for stoing opeatims
ES B? DI Destinotion for stsing opeation
SS BP/SP stock Helated opehatonsS

Flag Registe - 9t is an16 bit egistes ohich holds

Information ef last aih metic , logical etc
opeation
)some flag bits contsol he operaion of cPU

Calculahion,of 20 bit address &p4

Let segment addre ss LoosH =

Ofset address= 4211 H

Segment address o o01 000 Oo0o oLOL
Shkt tt by 4 bit = ( it is also deotës by Segment adds x 1OH
gnd add o000 I O segment add x i6D
LSB
00OL

off set addr OLOO o o10 o 0 ooo|

(4211 H)
OoOL ol oo OOO

2 6

so the 20 bit memoty address oill be = 1426LH

exp 2 et CS 2411H
IP 1001H

CSX ioH = 2 4 L 1o H
oo 1 H
P
25 L 11 H (20 bit)
address CS

This location ooiH(32769) CS 24110

the stanhng
ootion t a fsom The tanhng of cs addre s of
memonN
Code Segment memosy
openation of FLAG_Rgistel
15 14 13 12 16 5 2 O

C
xxxx o D T zx AcPxc
Casry Flag- C 1 It there is a
Carty out of MS8In addition
Casry In to MS8 th Subtsoch)
Pority Flag (P) - Pi if no of 15 (one's) 1n the lowes byte is EVEN
otheswise it is o.
Auxilliory Comy(Ac)-2 AC= i if Hhere is a corry from Lotsest nibble (Dto D4)
O
borro to Lowes nibble (D teDg
Zero Flag (z) - Zi it all Hhe bits of 1esult ase zeso (o)

Sign Flag ( s) - S=i If hesult of any computation is negative.

for Signed numbes ope^ah)

S MSsB
Trop Flaga (T) -: i-T= L 8086 l l enter l sirgle step execuhon mode
that means, psocesso will aenerate iñteupt
aktes 1 shuchm and TSR sill 8et execae
ecch

Do not
T O perfosm Single stcppi
Interrupt Flag()- if I=1 then 8o&86 oill 1ecognigethe extesnol
0tempts (th means hen I=1, then
all Hhe extena 1otessupts will beactivated)
All totevrupts coill be disabled
I=O
Direchen Flea (D) - s Used by staig manipulation iishruchans
*) if DO hen he sting will be proce ssec
rom locwa adds to highe address(auto
Cenent mode)
*) D=1 ,the smng coill be psocessed fsom

highe to loude addess ( auto decverngo

-

mode).
Flag (o) Hhese s oveshloo hen OF:i
-

Ovestlo
1 Cose of 8 bit signed opelah) qHeslt
IS of ore Thon 7 bits then OF = 1) |

(1 Cose of 16 blt Stgned operahon

94lt s morelhay |5 bits Hen oF =L
 Memory Segmentatlon
-X -

*) In 8o86 Hhe Complete physical memoT4 C1M8) is divided

,
1oto a numbe
of logical segments. SR E
)Esch segment 64K byte In S1ge and is addessed by one of Hhe segment
MegisteS.
)To address q speifie location oe oeed l6 bit offeet addess
l6 bitsag ment addvess x to t offset add =
ActuaL, address o memory
Why Segmentation Let
(20bit
us
ezplain it coiH an exomple of houng colony
oith 1oo houses
it we have to find house no 67 ,we Can do t
by 2
ays

1,2,3,- --.- 67 w e shart oith house no 1 and Hhen nd he

no 67
olumn
2
houses in loxlo
we have divided the loo
(vox cColumn) pa taLn
Ro
to get hwe ro 6t
6
) firet Select Colym) no OA ToLÐ no
e oe choe mw nO- 5
(sDu 6 Contaiis no om 61 too)
*Then 8o to Columo ne
Lwe i l l get house ro 67,

The 2nd methodd 1 this exomp)e s anglogous to segme0ted memory

Scheme cohere ) now 1dicates segment addes
Column tndicaly qkset address

ovelapped and Non Ovelapped seqments -

X
FFFFN
(4 0000H 4FFFF H) g2
-

Segment2 F F F F
DO00H 4000H (Starhng add) FFFEH.
overlappe
Tegon Segment
Segment1
FFFFH CS2,1P o00oH
/25000H oO0OH 2Soo (starhng addr:) 1ADIH

34FFFH *1css, IP

IS
.MB is divided 1nto 16 Segments s o m LAoL H to FfFPH
each f 64 KB oveapped areq which can eiheel
with ulized by seg ar ceg2
be
Segment address Combi0
offset addhess( oo00H FFFF
H) to *) let 6gment useSThi ola
ana Thon itS adda. angt eny be
prm 20 bit address
*) Fach segment nOn-ovelap
uitá (1 Ao1H &FFF H)
e t adds.
othon sgment
Advontoge_ot_Memary Segmenfaho
*)Allows the 8o86 to complete 20 bit address aauinement ysI n
6 bi+ Sseament and s e t ugusta |
Allows placing t Code genera dal9 Gnd stock dáta of same
Progoam 1 di Fferent segments ot memory for data code protecthm-
R e l o cation ot dafa IS Possjble. C 9t 1s not ne Cessory to stote he
Program and/oT its datg into same area of memoy)

i v ing system Bus

x

74LS3733
LATCH
A-A1g
A16 S3-Ai9/ss
74LS373
8086 LATH
ADADs VAD- AIS Ag-AIs

ALE 74LS373
LATCM
ADo-AD7, Ae-A7

Fia a) Latching 20 bt Address of 8oR6

74LS 24S
8086 Bute
DT/R
ADg-ADISDIR Dg-Dis
OEN EN
ADo
ADIs 74LS 24s|
Do-D
DIR
EN
hb) ByHleaung eats bus o s&o R6
8086 PIN DISCRIPT1ON
Minimum mocle Maximum mode

Vss (GND) Vec

ADI5
ADI4
ADI3 ADI6 Sz
ADI2 37ADI7/ S
ADI 36 ADI8 / 5s
5
ADIo AD19/ Sg
6
ADg BHES7
AD8 MNMx
32 RD
AD7 8086 3 Ra/GTO CHOLD)
ADG
ADS 30 Ral GT11 CHLDA)
AD4 12 LoCK AR)
AD3 CM/TO)
AD2
13

4
a COTR
ADi 15 6 So DEN)
ADo 6 2 &So CALE)
NMI 2.4 S1 CINTA)
tNTR18 23 TEST
LA 9 22 READY

Vss (GND)- 21 RE SET

The 8026 S1gnals Cin be categonsed into 3 Gups

qroup- -S19als havi1n9 Common tunehion n minimum as wcl| as i

max imum mode
When Pin33 MN MX =1 then So8G opeatts o siogle
MN/M PTOcessov mode , meGns con sol of
the. buses oil bc gt 8086.

if MN/MX «° then 8086 opejates in multipyoccssOY mode ,mear

multiple proce ssoTS wil) share tbe Conhsol of byses .

(o7 pins) repre sent l6 uddress lata lines

ADA5 These 16 lines

cwill Cary addre ss

DuAing Ti state, AD-Ais
Duaing T2, T3, T and Ta slalc, ADADIs i l C vy clata

*) Ti,T2,Ts, T4 ad Tu(wait cycle) are the clock cycles of a machine

clc
 AislS AIg/Ss,A/s+Aal-
A l 6 to Aig w | | provide addscsS fos memory Telated
*)Dusing Ti cycde opohahims
fhese lines wil be low , if 8 og6 pcafoTms Tlo operG hn
*)Dusing T2, Ts,Tw and Ta state, these lines oill ach like status
SignaL
53,S4 Indicates cohich sgment 9reguses is presenty beig u Sec
Sh S3
O es CExha Segmen)
ss
CS OA None
DS
act os intemupt engble flag bit that medos status of Hhe
inteaupt enoble flog (IF) s 1à dicated by this p dusing T2,Ts, TH T
S 6 is Rept al waHs loLJ W Us Wt4teRAR:AZA zRA

SHCIS-Bus High Enable is usecd to indicate the tansfes of dato

OVe highes Ohde clats bus. it acts along oith Ao

BHE AO
O ALU will psocess 16 bit datq
O Odd memory bank coill beGchivc (AIs -As will Caryy bits)
(UPpe byte from/to odd muney banK)
O Even memory bgnk will be achve

Idle Coo wOsK)

*)BHE= O ton T duig Aecd, wutc and 1oterupt Gckootilecdge Cycles.

S 1 currently rot used.
RD- RD =0 , Then Sos6 pesfos ns eading opeaahon rom memoTyTO
REAPY When READY = , 1hen the Memosy o IO device ls Aeady to
exchange dat
)Hhis signal is noTmally used by the sloo peaipheLals/ memos1ies to idicate
the psccessos thct mo0 they ahc heady to petom next opesGhm

INTR This is active high signal

8086 checks the status of his pin du109 he Last clock eycle of
each nptauchion It INTR=1 then 3o86 peaforms inteysupt acknowledg

TEST this Pn is exami ned by" NAIT" 1OSTHuchm.

TeST =0 , execution oill Continue. ( 808G cill Contnue shateve.
it is doi09)

fTES7=1L, he 8086 emans in iDLE state and

Reeps on wa1 ing
fonthe pio to become logic O.
Non- uskable intevupt ( Edge f>iyge^ccl)
tany devicc mukcs NMI 1 , the 8og6 wi1 stop the Cusient process
n d SeLve Hhis
nteLypt
RESET itRESET 1 ,
the 8a86 temingte thc CuNent
activity und
stat executing som FFFFO H
X) to pesfovm cset cpe scten , RESET = 1 must be fon. 4
atte 91eset opelane Clodk ycleS
AI) Flag bits it) get cleaied
CS FFFF H
IP O ooc HH
,Ds,ES ss O0OC H
CLR Bo86 Cao
opcate at 3MHz, SMH2 oMHz egucny
Vcc +5v Supply ton.the oposation otintesnalL
CiAtuuts.
Group-2 Minimum mode epesahon C MN/M= ]
O if MTO 1 , cPu opoates oith memo7y
CPU OpeLates h LO devi ce

INTA IfINTA =O , This psoce sso has accepted the intey¥upt.

meon
*9tis active loo
dusio9 T2,B 4Tw of intessuph acknoulecdge
cyele
ALE When ALE = L multiple Xed ous will provide addc SS Ao Ag.
9 t is uctlve high signal und it is neves taistatecl .

HaTa thons mit Receivc through bidihcchonaL butferss.

f D T R= 4 , PTecessC sencls data to mcm. TO device.

DT/R 0 , processOA. heceive data om mem. TO deVice

SEN )9t is used to seper.crte data from multiplexecl bus ADo-ADIS

w
)9+ is active om middle of T2 to micldle of T4
*) 9t is active loo Signa

HoLD, HLDA When HCLD 1 , i t incicates -that qnothe>. device is

equesting the bus aCCe ss.

It8036 pesmits the acce sSS ihen it nases HLDA pin to HIGH". So HLDA - |
meuns 808% iS eady to aive the Lon hcL of bu ses
 Group-33 Mazímum mode L MN M o]
S2 ,3 ,So These aTe He status Signals to ndi care the typc o
opesa hon

Interupt AcrotwlegC
Read
Wute | o
Halt
Ccde ucce ss

1 Rcad MemoYy
rToikc Mencry
1 Passive

These signals should be Gctive dusing Ta. cf prevlous macb1ne yelc and remain
active dusing Ti cand T2 of Cusent bus cycle ( machine cycle) .

LocK When LoCK O ofhes psocesso> Conoecrecl ro S08G oill notgct

Con sol ot buseS
This PID Is Used ühen 8o86 pesforms a Chhcal cpeatin

QS1,so ueue Status

No opeanon
6ueue
Finst oy te of epcode rom
Empty Gueue

Subsequ ent byres m &ueue

These Pins ahe uSecd by othen bus mastes's C othes

R/4To, Ral 4T prOcessons) to force the 8o86 to nelease 1he ControL
of local bus
ut the end of Cunhent muchinc Cyele C Tnst>.ucHm Cycle)

RQ-Request Gnant
*)R6|GTo have highe pichity "than R GTi
K)These pins ae bidínechionaL

T+T T2
SLAULr
CuTreot cycdeic NEzt Cycle >loweed by 8o&G
the (o0 sol
HOLD naised by Bo$6 atTes gethng

R/GTo
RLquest tron anothe qnothe devi ce want to give back he.
CcnoLof buses
derice to go86

KaGT
Grant Frem Bog36
tto aohej devjce
 Addre ssing Medes of 8086
Addressing mode de scribes he type of opeand and he way Hhey
ase qccessed om memoy IO
for executing Hhe incthychon.
) Lmmediate addesS nq mode - In his gddressing mode Immediafe
lato IS a pat of 1óstruchion
Exp MOV AX, SoooH
MoV CL, 81 H
*) The mediate dato Con be of 8 bit as 16 bit.
2) Diaec Addessin9 mode- In his mode 16 bit otfset oddress
IS diecFly Speafied in Hhe
instruehian
Exp MOV Ax ,L5o00H1
I1idicates address
)So0 H offset oddress. as we oYe
accessiÒg daf, So oato segment u )
be used
Complete memoTy address = DS * 10H + So00H

3) Registe addre ssing modes - In this hode,the data is stored in

1egistes and he aegistea will be
spei fied In Hhe instauctjon.
MOV Ax, Bx Transfes l6 bit data of Bx into Ax
MOV DL, BH Transfn 8 bits of BH oto lowes Bbits of
1egistea D
w e can net vse IP as a egiste in this mode

4) Registe iodinect addressing mode -

In this addressi0g mode , egístes holds the offset
address C Bx, 6T OA DI Tegistes.). this offset
addess Is used along with segment e g i s t e to
Calculare exact memory address
MOV Ax,L BX a s Bx has detaut segment of Data Seqment
So Memory addresS = oH DS + Bx

Bx So0OH ond DS= 4203

Let
lO*DS 2030 H
BX 5OoO H
470 30 H

k4403o 1he Complete addesS , cohere data

S stored
) Instruetion alcoays indicates offset addve ss ( By negistes Bx,
SI O DI)
S. Indexed In his mede, offset addess IS
AcddressIn9 Mode always stored in Index Hegistens
(eithes SI OA DI)

Mov AX, L sT] fos SI (non-stming opesatim) The default

Segment a Data seamen , so
Memory addresS loH *DSR +[sIJ
=

In Hhis mede
6 Based AddresE 9 mode (Registes helotive)-
he address of he cato 1s for med by
coith he
adduing 8/16 bit displacement+
pointe Hegistes ( BX, BP, SI Os o1).
) MOV AX, So CBx Memosy addre SS

1oH * DS + Bx +SoH 8 bit

) MoV DX, 5270H CSLJ Memory addreSS displaco Met

10% DS + SI + 527oH
L 16 bit displacement

) Based Index addresSIn9 Mde

X

Hhe effective address S fosmed by add ing Hhe content

nhis mode,
Bx Os BP) coith
he content of index Tegise
of bose hegise ( cojll be ES On DS
S I oa DI). he default Segment

Exp MOV OX, CBx] [S1]

Let Bx= 500obH for x and s I default segment is Data Seg
SI: 2 100H
DS 1 000H
lOH DS =

Memory addye ss BX
SI = 21 0 O
1 7 LOO
20 bit address
otdata
8) Relative Bas ed Index addye SSIQ9 Made-
The 20 bit qddess of memory fosmsd lby addng 8/16
is
Io his mode, and Index reg.
coith Sum of Base eg1ste (Bx os BP)
bit displacement
(SI O DI).
MOV Ax, 2700 L8x1[sT]
Exp Bx and s i , s
as DS the default segment reg ister of
* DS 6 o o o o
Let OS = 60o0 H lo H L6 0 O H
16 00 H
Bx: 1 oO O H
10 00 H
6 o
6 2

16 bit displace nment 27o O

64 D
oo 20 bit addres
 rOg Tam Memey Addressi9 ModesL contro thansfeà Lnstuctions]
his tyPe of addvessing modes are
kequiAd fos 19stuchens that Cause.
branch
(jump, cALL ete) the program.
B-anch
Tntaa seqment
*) Branch
w m
Tntesegment
ithió he same
Segment *)Bronch a differentsegment
*)Value of ofset egiste oill Value of ofset hsgiswll change
change Valye of Seg. hegica wllchange
¥Value ef segment egiste col MemosY
Aema tò bome. Seament1

Memory
Seg ment 1

Memery Segmet 2
ntraseament AddressIg MedeS
X-

qddsessig modes- Relative addresEO9

TntsegnentDihec
addsess appears dihectly
in Hhe 1 sthucthon. Hhe
In his ,the
mode
Content of IP egisTe
elative to the
dispace ment is computed
CS
JMP 0052H4
Exp 1052 H
Let IPe LoooH
addness = Looo H LP
New ofsef
OO52 H displace ment
1os2 H 1ooOH
displacement con be of 8 bit os 16 bit.

segmentndinecaddressi8 mode-
2) Lofra
Address specified Indineetly
s through q MegiaTes.
BX, BP, SI,DTT
) h e hegiste con be displqcement e n also be used.
glong coith
hegis
C8x+ o6S2 H ;Bx+ 00s2H will get loaded
JMP 1IP regikla
JMP LSI +BK
 Let Bx 2 Soo H and IP= 1000 H
displace mentz otS
OOS2H
Bx 2 o0
p o2
2S2 IPne = 1000+ 25s2 H 3s52 H
oddress willbe 3s2H
Sothe new off-cet
m to 3ss2H withis
progsam conke ill3et ranSfes 1000H
Code Segsment.

hterseemen Addsessing Mode

-X-

1 Inte.segmeot Direct addressin9 snode

Code segment t o anohe
he program Con rol tronstevTed som one

Code segment
Content of CS and IP Oi get cha nge

Exp Let cs= 2000H CS1 1oo0 H

IP 1oooH
2000H
CALL o 8OH 2800H

Neuo IP New CS

after erecute 1o 80H

CS2
CSe 28ooH , IP 1o8OH 2.800H

2) Tntesegment Indinect addressing mode

address Segment address sil be peVíde d by any
The effset
IndisecF addresSI09 mode
ot the memoTry
CSI + disp:]
Memory
C Bx + ST diaeF Cs (mse)- OS3
los2
CBxdisp] a dda Cs (LSB)e
OSL
modes LPCMSB)<-
C Bxt s I +disp] IP CLS8)<
10So

C Bx]
DS = 2 oooH, Bx= 100O H
Exp Let Data segmen
CALL C8x+OsH] h e neo locaion
gddh 1 stored in DS
coith oHset Bx tosH

CoIll acce SS 4 memo lo cansms

Bx+0S 1o SoH ,
So psoce s s o v
oD H to lo3H) to tind ne addre
lo20H
afteL exeud er Csz 20 CoH
P o 20H CS20SSo