Lecture : Binary ADD-SHIFT Multipliers

Presented by:

Dr. Vikramkumar Pudi

Assistant Professor
Electrical Engineering Department
IIT Tirupati
 Binary Serial Adder

𝑏3 𝑎3 𝑏2 𝑎2 𝑏1 𝑎1 𝑏0 𝑎0
Critical Path = ?
Area = ?

𝑐3 𝑐2 𝑐1
𝑐4 FA-3 FA-2 FA-1 FA-0 𝑐0
(𝑆4 )

𝑆3 𝑆2 𝑆1 𝑆0

2
Binary Serial Adder

Critical Path = ?
Area = ?

FA-0

𝑆0

3
Binary Serial Adder

4
 Binary Unsigned ADD-SHIFT Multiplier Design

𝑵 × 𝑴 Binary signed Multiplier will multiply two binary numbers A and B of size 𝑵-bits and 𝑀-bits
respectively, and produce the output S of size 𝑁 + 𝑀-bits

𝐴 = 𝑎3 𝑎2 𝑎1 𝑎0 𝐵 = 𝑏3 𝑏2 𝑏1 𝑏0

𝑌 = 𝐴 × 𝐵 = 𝑦7 𝑦6 𝑦5 𝑦4 𝑦3 𝑦2 𝑦1 𝑦0

𝑌 = 𝐴𝑏3 23 + 𝐴𝑏2 22 + 𝐴𝑏1 21 + 𝐴𝑏0 20 = 𝐴𝑏3 2−1 + 𝐴𝑏2 2−2 + 𝐴𝑏1 2−3 + 𝐴𝑏1 2−4 24
𝑌 = [𝐴𝑏3 + 𝐴𝑏2 + 𝐴𝑏1 + 𝐴𝑏0 2−1 2−1 2−1 ]2−1 24

𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 )2−1

Y = 𝑌𝑀 2𝑀

5
 Binary Unsigned ADD-SHIFT Multiplier Design

𝑵 × 𝑴 Binary signed Multiplier will multiply two binary numbers A and B of size 𝑵-bits and 𝑀-bits
respectively, and produce the output S of size 𝑁 + 𝑀-bits

𝐴 = 𝑎3 𝑎2 𝑎1 𝑎0 𝐵 = 𝑏3 𝑏2 𝑏1 𝑏0

𝑌 = 𝐴 × 𝐵 = 𝑦7 𝑦6 𝑦5 𝑦4 𝑦3 𝑦2 𝑦1 𝑦0

𝑌 = [𝐴𝑏3 + 𝐴𝑏2 + 𝐴𝑏1 + 𝐴𝑏0 2−1 2−1 2−1 ]2−1 24 𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 )2−1

Modified Equation

𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1

Y = 𝑌𝑀

6
 Binary Unsigned ADD-SHIFT Multiplier Design (Left
Shift)
𝑵 × 𝑴 Binary signed Multiplier will multiply two binary numbers A and B of size 𝑵-bits and 𝑀-bits
respectively, and produce the output S of size 𝑁 + 𝑀-bits

𝐴 = 𝑎3 𝑎2 𝑎1 𝑎0 𝐵 = 𝑏3 𝑏2 𝑏1 𝑏0
𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1
S = 𝐴 × 𝐵 = 𝑠7 𝑠6 𝑠5 𝑠4 𝑠3 𝑠2 𝑠1 𝑠0

B[i] Value Add/Sub Shift Count for(Count =0: Count<M; Count+1)

{
0 0 No if(B[count]=1)
Acc = Acc + A
Acc >> 1 Count + 1 Acc = Acc >> ‘1;
1 1 Acc = Acc + A
}

7
 Binary Unsigned ADD-SHIFT Multiplier Design (Left
Shift)
𝑵 × 𝑴 Binary signed Multiplier will multiply two binary numbers A and B of size 𝑵-bits and 𝑀-bits
respectively, and produce the output S of size 𝑁 + 𝑀-bits

𝐴 = 𝑎3 𝑎2 𝑎1 𝑎0 𝐵 = 𝑏3 𝑏2 𝑏1 𝑏0
𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1
S = 𝐴 × 𝐵 = 𝑠7 𝑠6 𝑠5 𝑠4 𝑠3 𝑠2 𝑠1 𝑠0

Acc[N+M:0] = 0; //(N+M-1-bits)
Acc = 0; for(Count =0: Count<M; Count+1)
for(Count =0: Count<M; Count+1) {
{ if(B[count]=1)
if(B[count]=1) { Acc[N+M:M] = Acc[N+M:M] + {1’b0,A};
{ Acc = Acc + A*𝟐𝑴 }
} Acc = Acc >> 1
Acc = Acc >> 1 }
} Y = Acc;
Y = Acc;
Adder size is N+1-bits

8
 Binary Unsigned ADD-SHIFT Multiplier Design

Start No Yes No
Acc[0] == 1 Count = M

A1  A
Acc  0 Yes
Acc[M-1:0]  B Acc[ ] = Acc[ ] + A;
Count  0
Y = Acc [ ]

ACC > 1

Stop

Count + 1

9
 Binary Unsigned ADD-SHIFT Multiplier Design (Right
Shift)
Example1: 0110(6) x 0101(5) 𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1

10
 Binary Unsigned ADD-SHIFT Multiplier Design (Right
Shift)
Example1: 0110(6) x 0101(5) 𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1
Count Check bit ADD Shift
(i) B[i] 𝑌𝑖+1 = 𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 𝑌𝑖+1 = 𝑌𝑖+1 ≫ 1
0 1 Y1 = Y0 + 6 * 16 Y1 = 96 >> 1 = 48
Y1 = 0 + 6 * 16 = 96

1 0 Y2 = Y1 + 0 * 16 Y2 = 48 >> 1 = 24
Y2 = 48 + 0 = 48
2 1 Y3 = Y2 + 6 * 16 Y3 = 120 >> 1 = 60
Y3 = 24 + 96 = 120

3 0 Y4 = Y3 + 0 Y3 = 60 >> 1 = 30
Y4 = 60 + 0 = 60

4
Y = Y4

11
 Binary Unsigned ADD-SHIFT Multiplier Design (Right
Shift)
Example 2: 1001(9) x 1101(13) 𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1
Count Check bit ADD Shift
(i) B[i] 𝑌𝑖+1 = 𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 𝑌𝑖+1 = 𝑌𝑖+1 ≫ 1
0 1 Y1 = Y0 + 9 * 16 Y1 = 144 >> 1 = 72
Y1 = 0 + 9 * 16 = 144

1 0 Y2 = Y1 + 0 * 16 Y2 = 72 >> 1 = 36
Y2 = 72 + 0 = 72
2 1 Y3 = Y2 + 9 * 16 Y3 = 180 >> 1 = 90
Y3 = 36 + 144 = 180

3 1 Y4 = Y3 + 9* 16 Y3 = 234 >> 1 = 117

Y4 = 90 + 144 = 234

4
Y = Y4 = 30

12
 Binary Unsigned ADD-SHIFT Multiplier Design (Right
Shift)
Example 3: 1111(15) x 1111(15) 𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1
Count Check bit ADD Shift
(i) B[i] 𝑌𝑖+1 = 𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 𝑌𝑖+1 = 𝑌𝑖+1 ≫ 1
0 1 Y1 = Y0 + 15 * 16 Y1 = 240 >> 1 = 120
Y1 = 0 + 15 * 16 = 240

1 1 Y2 = Y1 + 15 * 16 Y2 = 360 >> 1 = 180

Y2 = 120 + 240 = 360
2 1 Y3 = Y2 + 15 * 16 Y3 = 420 >> 1 = 210
Y3 = 180 + 240 = 420

3 1 Y4 = Y3 + 15* 16 Y3 = 450 >> 1 = 225

Y4 = 210 + 240 = 450

4
Y = Y4 = 225

13
 Binary Signed ADD-SHIFT Multiplier Design (Right
Shift)
Example 1: 1001(-7) x 1101(-3) 𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1
Count Check bit ADD\SUB Shift
(i) B[i] 𝑌𝑖+1 = 𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 𝑌𝑖+1 = 𝑌𝑖+1 ≫ 1
0 1
𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1

1 0
𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1

2 1
𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1

3 1
(Subtract) 𝑌𝑖+1 = (𝑌𝑖 − 𝐴𝑏𝑖 2𝑀 )2−1

4
Y = Y4 = 21

14
 Binary Signed ADD-SHIFT Multiplier Design (Right
Shift)
Example 1: 1001(-7) x 1101(-3) 𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1
Count Check bit ADD\SUB Shift
(i) B[i] 𝑌𝑖+1 = 𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 𝑌𝑖+1 = 𝑌𝑖+1 ≫ 1
0 1 Y1 = Y0 + (-7) * 16 Y1 = -112 >> 1 = -56
𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1
Y1 = 0 + (-7) * 16 = -112

1 0 Y2 = Y1 + 0 * 16 Y2 = -56 >> 1 = -28 𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1

Y2 = -56 + 0 = - 56
2 1 Y3 = Y2 + (-7) * 16 Y3 = -140 >> 1 = -70
Y3 = -28 - 112 = -140 𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1

3 1 Y4 = Y3 - (-7) * 16 Y3 = 42 >> 1 = 21
(Subtract) Y4 = -70 + 112 = 42 𝑌𝑖+1 = (𝑌𝑖 − 𝐴𝑏𝑖 2𝑀 )2−1

4
Y = Y4 = 21

15
 Binary Signed ADD-SHIFT Multiplier Design (Right Shift)

Example 3: 0111(7) x 1111(-1) 𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1

Count Check bit ADD\SUB Shift
(i) B[i] 𝑌𝑖+1 = 𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 𝑌𝑖+1 = 𝑌𝑖+1 ≫ 1
0 1 Y1 = Y0 + 7 * 16 Y1 = 112 >> 1 = 56
𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1
Y1 = 0 + 7 * 16 = 112

1 1 Y2 = Y1 + 7 * 16 Y2 = 168 >> 1 = 84 𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1

Y2 = 56 + 112 = 168
2 1 Y3 = Y2 + 7 * 16 Y3 = 196 >> 1 = 98
Y3 = 84 + 112 = 196 𝑌𝑖+1 = (𝑌𝑖 + 𝐴𝑏𝑖 2𝑀 )2−1

3 1 Y4 = Y3 - 7 * 16 Y3 = -14 >> 1 = -7
Y4 = 98 - 112 = -14 𝑌𝑖+1 = (𝑌𝑖 − 𝐴𝑏𝑖 2𝑀 )2−1

4
Y = Y4 = -7

16
 Binary unsigned ADD-SHIFT Multiplication
Example1: 0110(6) x 0101(5)
Initialization ACC[M+N:0] =000000000 Conditions
ACC[M-1 :0] =B
ACC[8:0] =000000101
Count Check bit ADD (ACC+A) Shift ACC >> 1 Done/ Operation
ACC[0] ACC[7:4]+A count
0 000000101 000000101 001100101>>1 0/1 ACC[0]=1
0110 000110010 Add ACC+A and right
001100101 shift by 1 bit
1 000110010 No addition 000110010>>1 0/2 ACC[0]=0
000011001 No addition only shifting
2 000011001 001111001 001111001>>1 0/3 ACC[0]=1
000111100 Add ACC+A and right
shift by 1 bit

3 000111100 No addition 000111100>>1 1/4(M) ACC[0]=0

000011110 No addition only shifting

4 Count arrived to maximum size of the multiplier, stop the process and collect the result from ACC.
Y = ACC[M+N-1:0] = 00011110 = 30

17
 Binary unsigned ADD-SHIFT Multiplication
Example2: 0101(5) x 0011(3)
Initialization ACC[M+N:0] =000000000 Conditions
ACC[M-1 :0] =B
ACC[8:0] =000000011
Count Check bit ADD (ACC+A) Shift ACC >> 1 Done/ Operation
ACC[0] ACC[7:4]+A count
0 000000011 001010011 000101001 0/1 ACC[0]=1
Add ACC+A and right
shift by 1 bit
1 000101001 001111001 000111100 0/2 ACC[0]=1
Add ACC+A and right
shift by 1 bit
2 000111100 No addition 000011110 0/3 ACC[0]=0
No addition only shifting

3 000011110 No addition 000001111 1/4(M) ACC[0]=0

No addition only shifting
4 Count arrived to maximum size of the multiplier, stop the process and collect the result from ACC.
Y = ACC[M+N-1:0] = 00001111 = 15

18
 Binary unsigned ADD-SHIFT Multiplication
Example3: 0111(7) x 0111(7)
Initialization ACC[M+N:0] =000000000 Conditions
ACC[M-1 :0] =B
ACC[8:0] =000000111
Count Check bit ADD (ACC+A) Shift ACC >> 1 Done/ Operation
ACC[0] ACC[7:4]+A count
0 000000111 001110111 000111011 0/1 ACC[0]=1
Add ACC+A and right
shift by 1 bit
1 000111011 010101011 001010101 0/2 ACC[0]=1
Add ACC+A and right
shift by 1 bit
2 001010101 011000101 001100010 0/3 ACC[0]=1
Add ACC+A and right
shift by 1 bit

3 001100010 No addition 000110001 1/4(M) ACC[0]=0

No addition only shifting
4 Count arrived to maximum size of the multiplier, stop the process and collect the result from ACC.
Y = ACC[M+N-1:0] = 00110001 = 49

19
 Binary unsigned ADD-SHIFT Multiplication
Example4: 1001(9) x 1011(11)
Initialization ACC[M+N:0] =000000000 Conditions
ACC[M-1 :0] =B
ACC[8:0] =000001011
Count Check bit ADD (ACC+A) Shift ACC >> 1 Done/ Operation
ACC[0] ACC[7:4]+A count
0 000001011 010011011 001001101 0/1 ACC[0]=1
Add ACC+A and right
shift by 1 bit
1 001001101 011011101 001101110 0/2 ACC[0]=1
Add ACC+A and right
shift by 1 bit
2 001101110 No addition 000110111 0/3 ACC[0]=0
No addition only shifting

3 000110111 011000111 001100011 1/4(M) ACC[0]=1

Add ACC+A and right
shift by 1 bit
4 Count arrived to maximum size of the multiplier, stop the process and collect the result from ACC.
Y = ACC[M+N-1:0] = 01100011 = 99

20
 Binary Signed ADD-SHIFT Multiplier Design
(Left Shift)
𝐴 = 𝑎3 𝑎2 𝑎1 𝑎0 𝐵 = 𝑏3 𝑏2 𝑏1 𝑏0
𝑵 × 𝑴 Binary signed Multiplier will multiply two binary numbers A and B of size 𝑵-bits and 𝑀-bits
respectively, and produce the output S of size 𝑁 + 𝑀-bits
S = 𝐴 × 𝐵 = 𝑠7 𝑠6 𝑠5 𝑠4 𝑠3 𝑠2 𝑠1 𝑠0

B[i] Value Add/Sub Shift Count

0 0 No

1 1 if (Count < M) Acc >> 1 Count + 1

Acc = Acc + A
Else
Acc = Acc - A

Initial values Acc[N+M:M] = 0, Acc[M-1:0] = B, Count = 0

21
Binary Signed ADD-SHIFT Multiplier Design
𝐴 = 𝑎3 𝑎2 𝑎1 𝑎0 𝐵 = 𝑏3 𝑏2 𝑏1 𝑏0
𝑵 × 𝑴 Binary signed Multiplier will multiply two binary numbers A and B of size 𝑵-bits and 𝑀-bits
respectively, and produce the output S of size 𝑁 + 𝑀-bits
S = 𝐴 × 𝐵 = 𝑠7 𝑠6 𝑠5 𝑠4 𝑠3 𝑠2 𝑠1 𝑠0

Load 8 7 6 5 4 3 2 1 0
Sh

Add
𝑏3 𝑏2 𝑏1 𝑏0 Acc
Controller

+
done 𝑎3 𝑎2 𝑎1 𝑎0 A
Start

Acc [8:?] = Acc [8:?] +A

22
 Binary Signed ADD-SHIFT Multiplier Design

Start No Yes No
Acc[0] == 1 Count = M-1

A1  A
Acc  0
Acc[M-1:0]  B Acc[ ] = Acc[ ] + A;
Count  0 If Acc[0] =1
Acc[ ] = Acc[ ] - A;

ACC >> 1 Yes

ACC >> 1
Y = Acc [ ]
Count + 1
Stop

23
 Binary Signed ADD-SHIFT Multiplier Design
𝐴 = 𝑎3 𝑎2 𝑎1 𝑎0 𝐵 = 𝑏3 𝑏2 𝑏1 𝑏0
𝑵 × 𝑴 Binary signed Multiplier will multiply two binary numbers A and B of size 𝑵-bits and 𝑀-bits
respectively, and produce the output S of size 𝑁 + 𝑀-bits
S = 𝐴 × 𝐵 = 𝑠7 𝑠6 𝑠5 𝑠4 𝑠3 𝑠2 𝑠1 𝑠0

If B[i] is MSB Load 8 7 6 5 4 3 2 1 0

Sh

Add
𝑏3 𝑏2 𝑏1 𝑏0 Acc
Controller

+
done 𝑎3 𝑎3 𝑎2 𝑎1 𝑎0 A
Start

Acc [8:?] = Acc [8:?] ± A

24
 Binary signed ADD-SHIFT Multiplication
Example4: 1001(-7) x 1011(-5)
Initialization ACC[M+N:0] =000000000 Conditions
ACC[M-1 :0] =B
ACC[8:0] =000001011
A1 = {A[N-1],A}=11001
Count Check bit ADD (ACC+A1) Shift ACC >>> 1 Done/ Operation
ACC[0] ACC[8:4]+A1 (Arithmetic Shift) count
0 000001011 000001011 111001101 0/1 ACC[0]=1
11001 (+) Add ACC+A1 and
110011011 Arithmetic right shift by 1
bit
1 111001101 111001101 110101110 0/2 ACC[0]=1
11001 (+) Add ACC+A1 and
1101011101 Arithmetic right shift by 1
1---discard bit
2 110101110 No addition 111010111 0/3 ACC[0]=0
No addition only shifting

3 111010111 111010111 000100011 1/4(M) ACC[0]=1

11001 (-) Subtract ACC-A1 and
001000111 right shift by 1 bit
4 Count arrived to maximum size of the multiplier, stop the process and collect the result from ACC.
Y = ACC[M+N-1:0] = 00100011 = 35 25
 Binary signed ADD-SHIFT Multiplication
Example4: 1011(-5) x 1100(-4)
Initialization ACC[M+N:0] =000000000 Conditions
ACC[M-1 :0] =B
ACC[8:0] =000001100
A1 = {A[N-1],A}=11011
Count Check bit ADD (ACC+A1) Shift ACC >>> 1 Done/ Operation
ACC[0] ACC[8:4]+A1 (Arithmetic Shift) count
0 000001100 No Addition 000000110 0/1 ACC[0]=0
No addition only shifting
1 000000110 No Addition 000000011 0/2 ACC[0]=0
No addition only shifting
2 000000011 110110011 111011001 0/3 ACC[0]=1
Subtract ACC-A1 and
right shift by 1 bit
3 111011001 000101001 000010100 1/4(M) ACC[0]=1
Subtract ACC-A1 and
right shift by 1 bit
4 Count arrived to maximum size of the multiplier, stop the process and collect the result from ACC.
Y = ACC[M+N-1:0] = 00010100= 20

26
 Radix-4 ADD-SHIFT Multiplier Design
𝐴 = 𝑎3 𝑎2 𝑎1 𝑎0 𝐵 = 𝑏3 𝑏2 𝑏1 𝑏0
𝑵 × 𝑴 Binary signed Multiplier will multiply two binary numbers A and B of size 𝑵-bits and 𝑀-bits
respectively, and produce the output S of size 𝑁 + 𝑀-bits
S = 𝐴 × 𝐵 = 𝑠7 𝑠6 𝑠5 𝑠4 𝑠3 𝑠2 𝑠1 𝑠0

If B[i] is MSB Load 8 7 6 5 4 3 2 1 0

Sh

Add
𝑏3 𝑏2 𝑏1 𝑏0 Acc
Controller

+
done 𝑎3 𝑎3 𝑎2 𝑎1 𝑎0 A
Start

Acc [8:?] = Acc [8:?] ± A

27
Binary Radix-2 Booth’s ADD-SHIFT Multiplier Design

𝑵 × 𝑴 Binary signed Multiplier will multiply two binary numbers A and B of size 𝑵-bits and 𝑀-bits
respectively, and produce the output S of size 𝑁 + 𝑀-bits

𝐴 = 𝑎3 𝑎2 𝑎1 𝑎0 𝐵 = 𝑏3 𝑏2 𝑏1 𝑏0

S = 𝐴 × 𝐵 = 𝑠7 𝑠6 𝑠5 𝑠4 𝑠3 𝑠2 𝑠1 𝑠0

28
Binary Radix-2 Booth’s ADD-SHIFT Multiplier Design

𝑵 × 𝑴 Binary signed Multiplier will multiply two binary numbers A and B of size 𝑵-bits and 𝑀-bits
respectively, and produce the output S of size 𝑁 + 𝑀-bits

𝐴 = 𝑎3 𝑎2 𝑎1 𝑎0 𝐵 = 𝑏3 𝑏2 𝑏1 𝑏0

S = 𝐴 × 𝐵 = 𝑠7 𝑠6 𝑠5 𝑠4 𝑠3 𝑠2 𝑠1 𝑠0

B[i+1:i] Value Add/Sub Shift

00 0 No Acc >> 1

01 1 Acc = Acc + A Acc >> 1

10 -1 Acc = Acc - A Acc >> 1

11 0 No Acc >> 1

29
Binary Radix-4 Booth’s ADD-SHIFT Multiplier Design

𝑵 × 𝑴 Binary signed Multiplier will multiply two binary numbers A and B of size 𝑵-bits and 𝑀-bits
respectively, and produce the output S of size 𝑁 + 𝑀-bits

𝐴 = 𝑎3 𝑎2 𝑎1 𝑎0 𝐵 = 𝑏3 𝑏2 𝑏1 𝑏0

S = 𝐴 × 𝐵 = 𝑠7 𝑠6 𝑠5 𝑠4 𝑠3 𝑠2 𝑠1 𝑠0

30
Binary Radix-4 Booth’s ADD-SHIFT Multiplier Design

B[i+2:i] Value Add/Sub Shift

000 0 No

001 1 Acc = Acc + A

010 1 Acc = Acc + A

011 2 Acc = Acc + ( A < 1 )

Acc >> 2
100 -2 Acc = Acc – (A < 1)

101 -1 Acc = Acc – A

110 -1 Acc = Acc – A

111 0 No

10101 = 101010 = 10 010 010

0101 = 01010 = 010 010
10101 = 1101010 = 110 010 010
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 Radix-4 ADD-SHIFT Multiplier Flow Chart

Case( Acc[count+2:count] )
Start 000 : Acc <= Acc No
001 : Acc[ ] <= Acc[ ] + A Count = N
010 : Acc[ ] <= Acc[ ] + A
011 : Acc[ ] <= Acc[ ] + 2A
100 : Acc[ ] <= Acc[ ] - 2A
B1 {B,0} 101 : Acc[ ] <= Acc[ ] - A
Acc[N+M+2:M+1]  0 110 : Acc[ ] <= Acc[ ] - A Yes
Acc[M:0]  B1 111 : Acc <= Acc
Count  0 Default: Acc <= Acc
Y = Acc[ ? ]

ACC >> 2

Stop
M is even
Count + 2

32
 Binary Radix-4 Booth’s ADD-SHIFT Multiplier Design

Acc[i+2:i] Algorithm Verilog

001 Acc[ ] <= Acc[ ] + A Acc[N+M+2:M+1] <= Acc[N+M+2:M+1] + {A[N-1],A[N-1],A}

010

011 Acc[ ] <= Acc[ ] + 2A Acc[N+M+2:M+1] <= Acc[N+M+2:M+1] + {A[N-1],A,1’b0}

100 Acc[ ] <= Acc[ ] - 2A Acc[N+M+2:M+1] <= Acc[N+M+2:M+1] + ~{A[N-1],A,1’b0} + 1

101

110 Acc[ ] <= Acc[ ] - 1A Acc[N+M+2:M+1] <= Acc[N+M+2:M+1] + ~{A[N-1], A[N-1],A} + 1

001 : Acc[ ] <= Acc[ ] + A

010 : Acc[ ] <= Acc[ ] + A
011 : Acc[ ] <= Acc[ ] + 2A
100 : Acc[ ] <= Acc[ ] - 2A
101 : Acc[ ] <= Acc[ ] - A
110 : Acc[ ] <= Acc[ ] - A 33
Binary Radix-4 Booth’s ADD-SHIFT Multiplier Design

B[i+2:i] Value Add/Sub 2’s 1’s

000 0 000 0

001 1 001 0

010 1 001 0

011 2 010 1

100 -2 110 1

101 -1 111 0

110 -1 111 0

111 0 000 0

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 Radix-4 Signed ADD-SHIFT Multiplier Design

Example 1: 1001(-7) x 1101(-3)

Count Check bit ADD\SUB Shift
(i) B[i+2:i] 𝑌𝑖+1 = 𝑌𝑖+1 ≪ 2 B = 111010

0 010 = 1 Y = 1*A = -7 Y = -7
Count = Count +2

2 110 = -1 Y = Y -1*A = -7 +(-1*-7<<2) Y = 21

4
Y = Y4 = 21

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 Radix-4 Signed ADD-SHIFT Multiplier Design

Example 1: 1111(-1) x 1111(-1)

Count Check bit ADD\SUB Shift
(i) B[i+2:i] 𝑌𝑖+1 = 𝑌𝑖+1 ≪ 2 B = 111110

0 110 = -1 Y = 1*A = +1 Y = +1
Count = Count +2

2 111 = 0 Y = Y +(0*A2<<2) =1 Y=1

3
Y =1

36
 ADD-SHIFT Multipliers Design
Unsigned Signed
Multiplier Multiplier

Size of ‘Acc’

Initialize and Load

ADD and SHIFT

37