VISVESVARAYA TECHNOLOGICAL UNIVERSITY

BELAGAVI-590018

A Seminar report on
“INTELLIGENT RAM”

Submitted in partial fulfillment of the award of the

Degree of Bachelor of Engineering
in
ELECTRONICS & COMMUNICATION ENGINEERING
By

Mehak H Shaikh
2JI19EC064

Under the Guidance of

Prof. B I Kattimani

Department of Electronics & Communication Engineering

Jain College of Engineering
Belgaum– 590 014

2022-23
 Jain College Of Engineering, Belagavi
T.S.Nagar, Machhe-590014

Department of Electronics & Communication Engineering

CERTIFICATE

Certified that the seminar entitled “Intelligent RAN(iRAM)”, is carried out by Ms. Mehak H

Shaikh, USN:2JI19EC064, a bonafide student of Department of Electronics & Communication

Engineering, Jain College of Engineering, Belagavi, in partial fulfillment for the award of Bachelor of

Engineering in Electronics & Communication of the Visvesvaraya Technological University, Belagavi,

during the academic year 2022-23. It is certified that all corrections/suggestions indicated for Continuous

Internal Evaluation have been incorporated in the report deposited in the department library. The seminar

report has been approved as it satisfies the academic requirements in respect of prescribed for the said

degree.

Guide HOD Principal & Director

Prof. Dr. Krupa.R.Rasane Dr. J Shivakumar

Name of the examiners Signature with date

1. _________________________ __________________

2. __________________________ __________________
 DECLARATION

I hereby declare that the Seminar work embodied in this report entitled “INTELLIGENT RAM
(iRAM),” has been carried out by us at the Department of Electronics and Communication Engineering,
Jain College of Engineering, Belagavi, under the supervision of Prof. B I Kattimani. The report has not
been submitted in part or full for the award of any degree of this or any other university.

To the best of our knowledge the above statement made by the student Mehak H Shaikh (2JI19EC064)
can be accepted for partial fulfillment of the requirements for the Degree of BACHELOR OF
ENGINEERING.

Signature of the student

Ms. Mehak H Shaikh
2JI19EC064

Date:
Place:
 Vision of Department
“To achieve excellence in education and research for developing globally
competent, ethically sound Electronics and Communication Engineers.”

Mission of Department
• To provide a conducive environment through a structured student centric,
teaching-learning process.
• To nurture needs of society by infusing scientific temper in students and to
grow as a center of excellence with effective industry-institute interaction.
• To inculcate self learning skills, entrepreneurial ability and professional
ethics.

Program Educational Objectives (PEOs)

Graduates will be able to:
PEO1: Contemplate real-time social problems and deliver efficient
solutions.
PEO2: Lead and succeed in professional careers.
PEO3: Contribute through research and entrepreneurship.

Program Specific Outcomes (PSOs)

Graduates in the UG program in Electronics and communication engineering

will be able to:
● Design, verify and develop analog and digital systems by using state of
art technology to contribute to societal needs.
● Apply the knowledge in various domains of IoT, real time systems,
communication systems, VLSI and embedded systems, image and signal
processing using hardware and software tools.
 Vision of Institute
"To be a university as a resource of solutions to diverse challenges of society
by nurturing innovation, research & entrepreneurship through value based
education."

Mission of Institute
● To provide work culture that facilitates effective teaching-
learning process and lifelong learning skills.

● To promote innovation, collaboration and leadership through

best practices.

● To foster industry-institute interaction resulting in

entrepreneurship skills and employment opportunities.
 Program Outcomes as defined by NBA (PO) Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an
engineering specialization to the solution of complex engineering problems.

2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems
reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering
sciences.

3. Design/development of solutions: Design solutions for complex engineering problems and design system
components or processes that meet the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.

4. Conduct investigations of complex problems: Use research-based knowledge and research methods including
design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid
conclusions.

5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and
IT tools including prediction and modeling to complex engineering activities with an understanding of the
limitations.

6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health,
safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering
practice.

7. Environment and sustainability: Understand the impact of the professional engineering solutions in societal
and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.

8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.

9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams,
and in multidisciplinary settings.

10. Communication: Communicate effectively on complex engineering activities with the engineering community
and with society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions.

11. Project management and finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.

12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent and
life-long learning in the broadest context of technological change.
 Jain College of Engineering, Belagavi
Department of Electronics & Communication Engineering

Subject: Seminar Subject code: 18ECS84

CO-PO/PSO Mapping:
L1:Remembering L2:Understanding L3:Applying L4:Analysing L5:Evaluating L6:Creating
Course outcomes Description Bloom's Cognitive level

18ECS84.1 The students will be able to analyze a current L2

topic of professional interest and present it

18ECS84.2 The student will be able to identify an

engineering problem, analyze it. L2

18ECS84.3 The students will be able to understand

professional engineering solutions, health and L2
safety issues.
 ABSTRACT
By incorporating processing power into a memory device, instead of the conventional
processor chips that house a portion of the memory hierarchy on-chip, a "intelligent" RAM aims
to construct a cost-effective computer. This merging provides a more flexible choice of memory
size and structure, as well as a reduction in memory latency, an increase in memory bandwidth,
and an improvement in energy efficiency. The most significant aspects of existing techniques are
reviewed in this document, along with their prospects and difficulties.
 CONTENTS

CHAPTER TITLE PAGE NO.

CHAPTER-1 Introduction 1
Fig 1.1 Definition of iRAM
Fig 1.2 iRAM

CHAPTER-2 Literature Survey 3

CHAPTER-3 WHY WE NEED iRAM? 4

Fig 3.1 Processor-Memory Performance Gap

CHAPTER-4 iRAM as Potential Solution 6

Fig 4.1 DRAM bus

CHAPTER-5 iRAM Architecture 8

Fig 5.1 Vector Processing model

CHAPTER-6 Generations of iRAM 10

CHAPTER-7 Applications, Advantages and Disadvantages 11

Fig 7.1 Block diagram of smart pole

CHAPTER-8 Conclusion 14

CHAPTER-9 References 15
 Intelligent RAM (iRAM)

CHAPTER-1

INTRODUCTION

Intelligent RAM (iRAM) is a form of memory that combines regular Random Access
Memory (RAM) features with a central processor unit's computational power (CPU). Another
name for it is "processor-in-memory" (PIM). Data processing is sped up in iRAM thanks to the
close integration of the memory and processor units. This is due to the fact that the CPU can
access memory data considerably faster than it can with conventional memory designs.

iRAM = Unifying the logic and DRAM on a single chip.

Fig 1.0 Definition of iRAM

Data analytics, running algorithms, and putting machine learning models into action are just
a few of the activities that can be carried out with the processing power of iRAM. Applications
that demand real-time processing or fast data access can benefit most from this. The availability
of iRAM is still limited as it is a relatively new technology. Yet, it has the ability to
fundamentally alter how computers process data, enhancing their speed, effectiveness, and
capacity to handle challenging workloads. Intelligent RAM, also known as iRAM, is a
revolutionary technology that combines the capabilities of traditional RAM with advanced
artificial intelligence. This innovative technology has the potential to transform the way we
interact with computers and other electronic devices.

One of the key features of iRAM is its self-learning capability. It can analyze the data it
stores and identify patterns and trends that can be used to improve its performance. In addition,
iRAM is also adaptable, meaning that it can adjust its operations based on the data it receives.

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 Intelligent RAM (iRAM)

This makes it an ideal technology for applications that require real-time data processing and
analysis.

Fig 1.2 iRAM

iRAM has the potential to revolutionize various industries and fields. For example, in the
healthcare industry, iRAM can be used to analyze patient data and identify potential health risks
before they become serious. In the financial industry, iRAM can be used to detect fraudulent
activity and prevent financial crimes. In the manufacturing industry, iRAM can be used to
monitor production lines and optimize efficiency.In conclusion, intelligent RAM (iRAM) is a
groundbreaking technology that has the potential to transform the way we interact with computers
and other electronic devices. Its self-learning and adaptable capabilities make it an ideal
technology for various industries and fields. As iRAM continues to evolve, we can expect to see
even more innovative applications and benefits in the future.

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 Intelligent RAM (iRAM)

CHAPTER-2
LITERATURE SURVEY
Computer memory solutions that integrate processing power right into the memory are
referred to as intelligent RAM (iRAM). This makes data processing and access quicker and may
eliminate the need for separate CPUs and GPUs. Following are some important studies and
articles on the subject.

"Intelligent DRAM: Exploring the Design Space," written by Hasan Hassan and Saugata
Ghose, was printed in the 2019 Proceedings of the 52nd Annual IEEE/ACM International
Symposium on Microarchitecture. The design space for intelligent DRAM systems is examined
in this study, which also provides an overview of recent iRAM research. Published in the
Proceedings of the 2019 ACM/SIGDA International Conference on Field-Programmable Gate
Arrays,"MaPU: A Hardware Accelerator for Matrix Computations Utilizing Processing-in-
Memory" by Xiaowei Jiang et al. This study introduces MaPU, a hardware accelerator for matrix
computations based on the PIM, and gives experimental findings illustrating its performance.

In 2020, Weijian Zhang and colleagues published "A Study of Processing-in-Memory

Methods" in ACM Computing Surveys. This review analyzes the benefits, drawbacks, and
prospective uses of PIM approaches, including iRAM, and offers a thorough explanation of each.
Presented at the 2019 25th IEEE International Conference on High-Performance Computer
Architecture was Saugata Ghose's paper, "HPCA-25 Tutorial: Near-Data Processing with
Processing-in-Memory (PIM)". This course covers a variety of design factors and implementation
strategies while introducing PIM technologies, including iRAM.

Overall, these papers and publications show that the field of iRAM research is active and
has the potential to dramatically enhance memory performance and open up new fields of
computer applications.

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 Intelligent RAM (iRAM)

CHAPTER-3

WHY WE NEED iRAM?

Problems Description
3.1 Processor-Memory Performance Gap
Development of processor and memory devices has proceeded independently. Advances in
process Technology, circuit design, and processor architecture have led to a near-exponential
increase in processor speed and memory capacity.

Fig 3.1 Processor-Memory Performance Gap

However, from Fig 2.1 memory latencies have not improved as dramatically. Technological
trends have produced a large and growing gap between CPU and DRAM.The Intelligent RAM
(iRAM) approach is to use the on-chip real-estate for dynamic RAM(DRAM) memory instead of
SRAM caches. It is based on the fact that DRAM can accommodate 30 to 50 times more data
than the same chip area devoted to caches. This on-chip memory can be treated as main memory
instead of a redundant copy, and in many cases the entire application will fit into the on-chip
storage. Having the entire memory on the chip, coupled to the processor through a high
bandwidth and low-latency interface, al-lows for processor designs that demand fast memory
systems.

3.2 Off-chip memory bandwidth limitation

Pin bandwidth will be a critical consideration for future microprocessors. Many of the
techniques used to tolerate growing memory latency do so at the expense of increased bandwidth

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 Intelligent RAM (iRAM)

requirements. Reduction of memory latency overhead aggravated bandwidth requirement for two
reasons:
1. Many of the techniques that reduce latency related stalls increase the total traffic between
main memory and the processor.
2. Reduction of memory latency overhead increases the processor bandwidth the rate or at
which the processor consumes and produces by reducing total execution time.
To understand where the time is spent in a complex processor, we divide execution time into 3
categories:
1. Processor time: is the time in which the processor is either fully utilized or is only partially
utilized or stalled.
2. Latin sea time: is the number of lost cycles due to untolerated, Instinct memory latencies.
3. Bandwidth time: is the number of lost CPU cycles due both to connection in the memory
system and insufficient bandwidth between levels of hierarchy.

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 Intelligent RAM (iRAM)

CHAPTER-4

iRAM AS POTENTIAL SOLUTION

We think it's time to think about combining logic and DRAM on a single chip due to the
widening performance gap between processors and memories and the difficulty of high-capacity
DRAM devices. Since memory will occupy the majority of the combined device's transistors, we
refer to such a chip as an iRAM, or intelligent RAM. DRAM is really 25 to 50 times denser than
cache memory in a microprocessor, which is why it should be used instead of boosting the
on-processor SRAM.Thus, iRAM would enable a much larger amount of on-chip memory than is
possible in a conventional architecture.Although others have examined this issue in the past,
iRAM is attractive today for several reasons.

Fig 4.1 (a) 4-bit-wide version of the 16-Mbit DRAM requires 16 chips for a 64-bit bus, providing 32 Mbytes of
storage. (b) 4-bit wide version of the 64-Mbit DRAM with the same bus also requires 16 chips, but yields 128
Mbytes.(c) With the 16-bit-wide version of the 64-Mbit DRAM, the minimum memory increment returns to 32
Mbytes, because we need just four chips for the 64-bit bus.

First, during the past ten years, the performance gap between CPUs and DRAMs has grown
by 50% annually. So, memory speed restricts more programmes now than it did in the past,
despite the valiant efforts of architects, compiler authors, and application developers.

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 Intelligent RAM (iRAM)

Second, the future Gbit DRAM will have enough capacity to accommodate whole
programmes and data sets on a single chip because the current CPU only takes up around one
third of the die (Table 3). iRAMs were formerly thought of as primarily being the building blocks
for multiprocessors because there could be so little memory on board with the CPU.

Third, DRAM devices have increased in size by around 50% with each generation, and they
are now constructed with extra metal layers to speed up the longer lines that come with the
greater size. In order to make their technology more appealing for iRAM applications, DRAM
producers are now starting to offer quick transistors and a lot of metal layers. Logic in iRAM can
be just as quick and dense as a traditional logic method for, say, 20% more money per DRAM
wafer.

An on-chip CPU might use a Memory's exceptional internal bandwidth, which

automatically fetches the square root of its capacity per DRAM clock cycle. Even more than its
logical arrangement suggests, the Gbit DRAM has a higher theoretical bandwidth. The standard
approach is to restrict the length of the Bit lines, often with 256 to 512 bits per sense amplifiers,
because it is crucial to keep the Storage cell short. As a result, there are four times as many sense
amplifiers. Each block has a limited amount of I/O lines to conserve die space, which lowers the
internal bandwidth by a factor of 5 to 10 while still satisfying external demand. iRAM wants to
use more of the possible on-chip bandwidth.

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 Intelligent RAM (iRAM)

CHAPTER-5

iRAM ARCHITECTURE

The Key Technologies behind the iRAM technology are,

1. Vector Processing
2. Embedded DRAM
3. Serial I/OVector Processing
5.1 Vector Processing
Instruction level parallelism (ILP), which is a programming technique used by high-speed
microprocessors, allows for the hardware to execute small instruction sequences concurrently. As
was already noted, these high-speed microprocessors depend on cache hits to deliver instructions
and operands at a rate that keeps the processors active. Vector processing is an alternative ILP
exploitation approach that does not rely on caches. It is a far more established architecture and
compiler paradigm than superscalar, popularized by supercomputers. High-level operations on
linear number arrays are performed by vector processors.

Fig 5.1 Vector processing model

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 Intelligent RAM (iRAM)

The "vector processing model," Fig 5.1 is executed simultaneously. Thus, scalar processing
is slower than parallel processing.
Since vector architecture deals with vector processing it represents only the processor
architecture of iRAM. It helps to study instruction level parallelism or parallel processing of
iRAM.
Advantages of Vector Processing
1. High performance on demand for multimedia processing.
2. Low power for issue of control logic.
3. Because of less complexity in design it’s cheap and very easy in implementation
5.2 Embedded DRAM
The embedded DRAM technology used in iRAM is by means of embedded technology. It is
the technology by which a chip is embedded into a device for the control and well execution of
the operations of that particular device. Usually chip embedding is done in devices handled by
common people where they don’t need to interact with the chip directly, but by means of
embedded chip he executes and controls the device. During the fabrication the memory chip is
embedded into the microprocessor to produce iRAM. Thus iRAM becomes a single chip into
which both memory and processor are integrated for high quality performance due to their
coexistence.
Advantages of Embedded DRAM
1. High Bandwidth
2. low latency
3. Memory Access frequency low
4. Memory Flexibility
5.3 Serial I/O
Due to the poor performance of parallel I/O both in the case of band width and scaling
processes the I/O system of iRAM is using a much more efficient and cost effective technology
the ‘Serial I/O system’. It enhances the performance of iRAM without hindering the memory and
processor performances by offering a smooth and faster path for data transfer.
Advantages of serial I/O
1. Offer very high bandwidth in terms of GB/sec which is greater than both.
2. Pin count is less.

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 Intelligent RAM (iRAM)

CHAPTER-6

GENERATIONS OF iRAM

6.1 Second Generation iRAM

The second generation iRAM, GC-RAMDISK, was on display at computex 2006. Rather
than using a PCI slot for powering the drive, Gigabyte had implemented the GC-RAMDUSK as
a 5.25’’ drive unit Powered from a four pin molex connectorThere are often several layers of
memory cells and processing components used in second generation iRAM architectures. The
lower layers of memory cells are used to store data, while the higher levels are utilized for
processing activities like data compression or decompression, encryption or decryption.

Multimedia applications, network processing, digital signal processing, and other areas have
all found uses for second generation iRAM. As compared to conventional memory architectures,
the combining of memory and processing components on a single chip can result in lower power
consumption, faster speeds, and lower latency.

However, iRAM technology has not been widely adopted due to its relatively high cost and
complexity compared to traditional memory architectures.

6.2 3T I-RAM
The name “3T I-RAM” comes from the three transistor cell design plus the letter ‘i’,the
engineering symbol for electric current to represent the current-sensing technology employed.
The dramatic speed of 3T I-RAM was achieved by re-designing the DRAM read mechanism to
react to changes in current rather than changes in voltage. 3T I-RAM chips incorporate another
speed advantage. 3T I-RAM chips require no idle time at all on turnaround; this contributes to
their speed.

3T I-RAM provides twice the capacity of standard SRAM in exactly the same footprint. The
reason for this is a simple standard SRAM technology requires six transistors for each memory

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 Intelligent RAM (iRAM)

cell, but each 3T I-RAM cell needs only three transistors. 3R I-RAM is built on DRAM
technology, it shares DRAMs reliability; DRAM is more resistant to soft error than SRAM.

CHAPTER-7

APPLICATION, ADVANTAGES AND DISADVANTAGES

7.1 Smart Pole Management by iRAM

iRAM technology Drinks the next generation wireless mesh Technology to the streets to
save energy, improve efficiency and reduce the cost. iRAM Smart Pole is a specially designed
high strength pole of 9-25 meters height with a camouflage cage to conceal the various telecom,
IT and IoT (Internet of Things) components and an underground chamber for various control
devices, gateways and UPS etc. The camouflage cage or nacelle is made of special material that
provides good RF transparency.

Fig 7.1 Block diagram of Smart pole

The iRAM unified IoT gateway is designed to host multiple devices like smart LED light,
small cell cellular antennas, IoT and other network gateways, digital billboards, surveillance
cameras, environment sensors, Wi-Fi access points, public address system, electronic call box or
panic button, electronic vehicle charging points. It provides high flexibility in placement of the
equipment on it and in the over the ground or underground enclosure, making it easy and cheaper
to setup and maintain these devices from the command center.

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 Intelligent RAM (iRAM)

The top portion of the pole houses smart LED lights, telecom antennas, Wi-Fi access points,
smart lighting controllers and associated equipment, while the mid-section houses variable
messaging boards, public addressing system and environmental sensors. Depending on the area,
surveillance cameras can be housed on the light arm or mid-section. The pole has multiple
cut-outs to draw the wires of these components only at the place of requirement.
Key Benefits
● Designed from ground up in India for Indian roads and climate conditions.
● Highly secured system that prevents and alerts thefts.
● Light harvesting.
● Real time energy consumption, cost, CO2 release, saving, projected cost.
● Remote control and monitoring through the internet.
● Event notification in case of power failure.
● Automatic temperature management within the enclosure.

7.1 Additional Applications

1. Scientific Computing
2. Cryptography (RSA, DES/IDEA)
3. Operating system/Networking
4. Language runtime support(stdlib, garbage collection)
5. Databases(data mining, image/video serving)
6. Speech and handwriting recognition
7. Lossy Compression(JPEG, MPEG)
7.2 Advantages
1. Higher Bandwidth
RAM and processor are on a single chip so less BUS length and due to that Higher data
transfer.
2. Lower Latency
Decrease time delay due to multiplexing addresses and less BUS length. Also doesn’t have
parallel DRAMs and less number of pins.
3. Energy Efficiency

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 Intelligent RAM (iRAM)

Energy per memory access = AEL1 + MRL1 * AEL2 + MRL2 * AEoff-chip

where, AE = access energy
MR = miss rate
4. Cost of Production
Fabrication of RAM and Processor is done in a single fabrication line.
5. Board Area
Integrate several chips into ‘One Chip’. So, a SMALL board area is required.
6. Memory Flexibility
Over conventional designs is the ability to adjust both the size and width of the on-chip
DRAM
7.3 Disadvantages
1. Completely new Architecture
For the acceptance of this new technology we have to discard our current products and
technologies.
2. High cost of testing
Adding a processor would significantly increase the test time
3. Non Upgradability of memory
DRAM chips are embedded in the iRAM chip. So, we will not be able to upgrade the
memory further.
4. Overheating
Even though the heat produced is less compared to current processors it may overheat due
to the small area.

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 Intelligent RAM (iRAM)

CHAPTER-9

CONCLUSION

In terms of performance, energy efficiency, and cost, combining a microprocessor and

DRAM on one chip offers the following benefits: a factor of 5 to 10 reduction in latency, a factor
of 50 to 100 increase in bandwidth, a factor of 2 to 4 advantage in energy efficiency, and an
unquantifiable cost savings by removing unnecessary memory and by shrinking the size of the
circuit board. The surprising thing is that these statements are based on an existing technology
that has been in use for the previous ten years, not some strange, untested technology. The only
thing limiting iRAM's popularity is the amount of memory on-chip, which should increase by
around 60% annually.

The ideal situation for iRAM would be to extend its beachhead in graphics, which requires
around 10 Mbits of storage, to the gaming, embedded, and personal digital assistant businesses,
which need about 32 Mbits of storage. The development of a technique that is friendlier to iRAM
and uses somewhat larger DRAM cells than those used in DRAM manufacturing but is
considerably more compatible with logic and SRAM might be justified by such high volume
applications. The network computer and portable PC industry may embrace iRAM when it
increases in storage capacity to 128 to 256 Mbits. After seeing such success, chip makers of
processors or DRAM may decide to integrate significant amounts of DRAM into their products.

iRAM therefore offers a chance to alter the semiconductor industry's makeup. A more
uniform industry might result from the existing split between logic and memory camps, with
historical microprocessor makers shipping significant quantities of DRAM, much as they do now,
or historical DRAM manufacturers shipping significant quantities of microprocessors. Both
possibilities may potentially come true, with one group of producers focused on great
performance and the other on cheap cost. Moreover, iRAM has the potential to develop a new
generation of portable, small, and power-efficient computers without sacrificing performance or
efficiency.

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 Intelligent RAM (iRAM)

CHAPTER-10

REFERENCE

[1] “CIS-RAM 2019 Front Matter,” 2019 IEEE International Conference on Cybernetics and
Intelligent Systems (CIS) and IEEE Conference on Robotics, Automation and
Mechatronics (RAM), Nov. 2019, doi: 10.1109/cis-ram47153.2019.9095827.
[2] C.-S. Seo and A. Chatterjee, “Optically Interconnected Intelligent RAM Multiprocessors
(OPTO-iRAM),” Oct. 2004, doi: 10.21236/ada428066.
[3] D. Patterson et al., “Intelligent RAM (iRAM): chips that remember and compute,” 1997
IEEE International Solids-State Circuits Conference. Digest of Technical Papers, doi:
10.1109/isscc.1997.585348.
[4] K. S. Gehlot and S. Ram, “To Improve Power Transfer Capacity Using TCSC FACTS
Controller,” Intelligent Energy Management Technologies, pp. 409–424, Dec. 2020, doi:
10.1007/978-981-15-8820-4_36.
[5] D. T. Wang, “RAM: a Petri net based expert system with memory,” 2022 IEEE
International Conference on Systems, Man and Cybernetics. Intelligent Systems for the
21st Century, doi: 10.1109/icsmc.2022.538148.
[6] gurwinder singh, M. Rattan, and G. K. Walia, “Power optimization using intelligent Clock
gating dedicated for block RAM cascading technique in FPGA design.,” Sep. 2021, doi:
10.21203/rs.3.rs-878601/v1.
[7] J. Austin, “Uncertain Reasoning with RAM Neural Networks,” Journal of Intelligent
Systems, vol. 2, no. 1–4, Jan. 1992, doi: 10.1515/jisys.1992.2.1-4.121.
[8] D. Patterson et al., “Intelligent RAM (iRAM): the industrial setting, applications, and
architectures,” Proceedings International Conference on Computer Design VLSI in
Computers and Processors, doi: 10.1109/iccd.1997.628842.
[9] S. Ram, “Intelligent Agents and the World Wide Web,” Intelligent Support Systems, pp.
1–3, 2002, doi: 10.4018/978-1-931777-00-1.ch001.
[10] “2017 IEEE International Conference on Cybernetics and Intelligent Systems (CIS)
and IEEE Conference on Robotics, Automation and Mechatronics (RAM),” Nov. 2017,
doi: 10.1109/cis-ram42180.2017.

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