CS33CS1301CS1301 (SM5) PDF
CS33CS1301CS1301 (SM5) PDF
INTRODUCTION
ENCODER
DECODER
MULTIPLEXER
DE-MULTIPLEXER
COMPARATOR
PARITY GENERATOR AND CHECKER
INTRODUCTION
Combinational Circuit:
A1 = Y3 + Y2
EQUATIONS:
A0 = Y3 + Y1
CIRCUIT-DIAGRAM
8 : 3 (Octal-To-Binary) Encoder
n
m <= 2
BINARY DECODER
Binary Decoders are another type of digital logic device that has inputs
of 2-bit, 3-bit or 4-bit codes depending upon the number of data input
lines.
A decoder that has a set of two or more bits will be defined as having
an n-bit code, and therefore it will be possible to represent 2n possible
values.
A decoder generally decodes a binary value into a non-binary one by
setting exactly one of its n outputs to logic “1”
2-TO-4 BINARY DECODER
Out0 Q0
S0 I0 Out1 Q1
S1 I1 Out2 Q2
Out3 Q3
CIRCUIT DIAGRAM
TRUTH TABLE
INPUT OUTPUT
S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Q0 = S1'.S0'
Q1= S1’.S0
Q2 = S1.S0’
Q3= S1.S0
TYPES of DECODER
Parallel:
Tree
Balanced
Applications of DECODER
Used in microcomputer for generating chip select signals for
selecting a particular bank.
•It is a combinational circuit which have many data inputs and single
output depending on control or select inputs.
• For N input lines, log n (base2) selection lines, or we can say that for
2n input lines, n selection lines are required.
A>B : AB'
A<B : A'B
A=B : A'B' + AB
Circuit Diagram
PARITY GENERATOR
AND CHECKER
What is Parity ?
The parity generating technique is one of the most widely used error
detection techniques for the data transmission. In digital systems, when
binary data is transmitted and processed , data may be subjected to
noise so that such noise can alter 0s (of data bits) to 1s and 1s to 0s.
Hence, parity bit is added to the word containing data in order to make
number of 1s either even or odd.
Parity Generator
It is combinational circuit that accepts an n-1 bit stream data and
generates the additional bit that is to be transmitted with the bit
stream. This additional or extra bit is termed as a parity bit.
In even parity bit scheme, the parity bit is ‘0’ if there are even number
of 1s in the data stream and the parity bit is ‘1’ if there are odd number
of 1s in the data stream.
In odd parity bit scheme, the parity bit is ‘1’ if there are even number
of 1s in the data stream and the parity bit is ‘0’ if there are odd number
of 1s in the data stream. Let us discuss both even and odd parity
generators.
Parity Checker
It is a logic circuit that checks for possible errors in the transmission.
This circuit can be an even parity checker or odd parity checker
depending on the type of parity generated at the transmission end.
When this circuit is used as even parity checker, the number of input
bits must always be even.
When a parity error occurs, the ‘sum even’ output goes low and ‘sum
odd’ output goes high. If this logic circuit is used as an odd parity
checker, the number of input bits should be odd, but if an error occurs
the ‘sum odd’ output goes low and ‘sum even’ output goes high.