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CS33CS1301CS1301 (SM5) PDF

The document provides an overview of several types of combinational logic circuits including encoders, decoders, multiplexers, demultiplexers, comparators, and parity generators and checkers. It describes what each circuit type is, provides examples of their structure and function, and discusses their applications. The key information covered includes how encoders and decoders convert between binary and non-binary codes, how multiplexers and demultiplexers select single outputs from multiple inputs, and how comparators and parity circuits are used for error detection.

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0% found this document useful (0 votes)
69 views42 pages

CS33CS1301CS1301 (SM5) PDF

The document provides an overview of several types of combinational logic circuits including encoders, decoders, multiplexers, demultiplexers, comparators, and parity generators and checkers. It describes what each circuit type is, provides examples of their structure and function, and discusses their applications. The key information covered includes how encoders and decoders convert between binary and non-binary codes, how multiplexers and demultiplexers select single outputs from multiple inputs, and how comparators and parity circuits are used for error detection.

Uploaded by

Mohitraj
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CONTENTS:-

INTRODUCTION
ENCODER
DECODER
MULTIPLEXER
DE-MULTIPLEXER
COMPARATOR
PARITY GENERATOR AND CHECKER
INTRODUCTION
Combinational Circuit:

The output of the combinational


circuit depends on the values at the input at
any given time.
The circuits do not make use of any memory or
storage device.
A combinational circuit can have an n number
of inputs and m number of outputs
INTRODUCTION
Combinational Circuit Blok Diagram:
ENCODER

ENCODER- a digital circuit that produces a binary output code


depending on which of its inputs are activated.
4 : 2 Encoder
The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 & Y0 and two
outputs A1 & A0. At any time, only one of these 4 inputs can be ‘1’ in
order to get the respective binary code at the output.
TRUTH-TABLE

A1 = Y3 + Y2
EQUATIONS:
A0 = Y3 + Y1
CIRCUIT-DIAGRAM
8 : 3 (Octal-To-Binary) Encoder

The 8 to 3 Encoder consists of …………. inputs …………… and ……….


outputs ……… & ………. At any time, only one of these ……….. inputs can
be ‘1’ in order to get the respective binary code at the output.
USES:-
Encoders are very common electronic circuits used in all digital systems.

It is used in 8:3 hexa-decimal to binary encoder.

It is used in decimal to BCD encoder.

Other applications especially for Priority Encoders may include


detecting interrupts in microprocessor applications
(Assignment)

1. What is the major disadvantage of combinational circuit?


2. What is the function of Encoder?
3. What is Keyboard Encoder?
DECODERS
DECODER
 A decoder has
 N inputs
 2N outputs

 A decoder selects one of 2N outputs by decoding the binary value on


the N inputs.
 The decoder generates all of the minterms of the N input variables.
 Exactly one output will be active for each combination of the
inputs.
BLOCK DIAGRAM

n
m <= 2
BINARY DECODER
Binary Decoders are another type of digital logic device that has inputs
of 2-bit, 3-bit or 4-bit codes depending upon the number of data input
lines.
A decoder that has a set of two or more bits will be defined as having
an n-bit code, and therefore it will be possible to represent 2n possible
values.
A decoder generally decodes a binary value into a non-binary one by
setting exactly one of its n outputs to logic “1”
2-TO-4 BINARY DECODER

 The 2 binary inputs labeled S0 and S1 are decoded into one


of 4 outputs, hence the description of 2-to-4 binary decoder.

 Each output represents one of the minterms of the 2 input


variables
BLOCK DIAGRAM

Out0 Q0
S0 I0 Out1 Q1

S1 I1 Out2 Q2

Out3 Q3
CIRCUIT DIAGRAM
TRUTH TABLE
INPUT OUTPUT

S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

Q0 = S1'.S0'
Q1= S1’.S0
Q2 = S1.S0’
Q3= S1.S0
TYPES of DECODER
 Parallel:
 Tree
 Balanced
Applications of DECODER
Used in microcomputer for generating chip select signals for
selecting a particular bank.

Used in a microprocessor for instruction decoding purpose.


Assignment
Why decoder circuit called minterm indicator?.

Draw and explain the principle operation of BCD to decimal


decoder.
MULTIPLEXER

•It is a combinational circuit which have many data inputs and single
output depending on control or select inputs.

•​ For N input lines, log n (base2) selection lines, or we can say that for
2n input lines, n selection lines are required.

•Multiplexers are also known as “Data n selector, parallel to serial


convertor, many to one circuit, universal logic circuit​”
Implementation of 4:1 MUX
TRUTH TABLE
CIRCUIT DIAGRAM
Implementation of NOT gate using 2 : 1 MUX
Implementation of AND gate using 2 : 1
MUX
Implementation of OR gate using 2 : 1 MUX
Cascading of Multiplexers
 Cascading refers to a process where large Multiplexers can be
designed and implemented using smaller Multiplexers.
Demux
 The demultiplexer is a combinational logic circuit designed to switch
one common input line to one of several separate output line.
COMPARATOR
Comparator
A magnitude digital Comparator is a combinational circuit
that compares two digital or binary numbers in order to find out
whether one binary number is equal, less than or greater than the other
binary number.
We logically design a circuit for which we will have two inputs one for A
and other for B and have three output terminals, one for A > B
condition, one for A = B condition and one for A < B condition.
Block Diagram
1 Bit Comparator
A comparator used to compare two bits is called a
single bit comparator.
It consists of two inputs each for two single bit
numbers and three outputs to generate less than,
equal to and greater than between two binary
numbers.
Truth Table

A>B : AB'
A<B : A'B
A=B : A'B' + AB
Circuit Diagram
PARITY GENERATOR
AND CHECKER
What is Parity ?
The parity generating technique is one of the most widely used error
detection techniques for the data transmission. In digital systems, when
binary data is transmitted and processed , data may be subjected to
noise so that such noise can alter 0s (of data bits) to 1s and 1s to 0s.

Hence, parity bit is added to the word containing data in order to make
number of 1s either even or odd.
Parity Generator
It is combinational circuit that accepts an n-1 bit stream data and
generates the additional bit that is to be transmitted with the bit
stream. This additional or extra bit is termed as a parity bit.
In even parity bit scheme, the parity bit is ‘0’ if there are even number
of 1s in the data stream and the parity bit is ‘1’ if there are odd number
of 1s in the data stream.
In odd parity bit scheme, the parity bit is ‘1’ if there are even number
of 1s in the data stream and the parity bit is ‘0’ if there are odd number
of 1s in the data stream. Let us discuss both even and odd parity
generators.
Parity Checker
It is a logic circuit that checks for possible errors in the transmission.
This circuit can be an even parity checker or odd parity checker
depending on the type of parity generated at the transmission end.
When this circuit is used as even parity checker, the number of input
bits must always be even.
When a parity error occurs, the ‘sum even’ output goes low and ‘sum
odd’ output goes high. If this logic circuit is used as an odd parity
checker, the number of input bits should be odd, but if an error occurs
the ‘sum odd’ output goes low and ‘sum even’ output goes high.

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