Scribd
Upload
77 views4 pages

19-Data Flow Modeling and Test Bench-10-02-2023 PDF

A test bench is used to simulate and test a circuit design. It contains a signal generator that applies different inputs to the circuit over time and monitors the outputs. The test bench is defined as a separate module that instantiates the design being tested. It has no input or output ports as it does not interact with an external environment. The test benches provided simulate half adders and full adders by applying different input patterns and checking the outputs.

Uploaded by

Back up
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
77 views4 pages

19-Data Flow Modeling and Test Bench-10-02-2023 PDF

A test bench is used to simulate and test a circuit design. It contains a signal generator that applies different inputs to the circuit over time and monitors the outputs. The test bench is defined as a separate module that instantiates the design being tested. It has no input or output ports as it does not interact with an external environment. The test benches provided simulate half adders and full adders by applying different input patterns and checking the outputs.

Uploaded by

Back up
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Test Bench

• To simulate a circuit with an HDL, it is necessary to apply inputs to the circuit so


that the simulator will generate an output response.

• An HDL provides the stimulus to a design is called a test bench.

• A test bench is a module containing a signal generator and an instantiation of the


model that is to be verified.

• The test bench has no input or output ports, because it does not interact with its
environment.

• Within the test bench, the inputs to the circuit are declared with keyword “reg”
and the outputs are declared with the keyword “wire”.
Test Bench for Half adder
Test Bench Code:
• Code: module tb_HA ();
module half_adder (S, C, A, B); reg a, b;
wire s, c;
input A, B; half_adder h1 (s, c, a, b);
output S, C; Initial
xor g1 (S, A, B); begin
a = 1’b0; b=1’b0;
and g2 (C, A, B); #100
endmodule a = 1’b0; b=1’b1;
#100
a = 1’b1; b=1’b0;
#100
a = 1’b1; b=1’b1;
end
endmodule
Test Bench for Full Adder
Test bench code:
• Code: module tb_fa ();
reg a,b,cin;
module full_adder (S,Co,A,B,Ci); wire s, co;
full_adder f1 (s,co,a,b,ci);
input A, B, Ci;
output S, Co; Initial
begin
wire w1, w2,w3;
a = 1’b0; b=1’b0; c=1’b0;
half_adder h1 (w1,w2,A,B); #100
half_adder h2 (S,w3,w1,Ci); a = 1’b0; b=1’b0; c=1’b1;
#100
or g3(Co, w2,w3); a = 1’b0; b=1’b1; c=1’b0;
endmodule #100
a = 1’b1; b=1’b0; c=1’b0;
#100
a = 1’b1; 1=1’b0; c=1’b0;
#100
end
endmodule

You might also like