Gate Level Modeling
• The module is implemented in terms of logic gates and interconnections between these
gates. Design at this level is similar to describing a design in terms of a gate-level logic
diagram.
• Features:
• Hardware design is described using instantiations of both primitives as well as
modules.
• Logic independent of the ordering of instantiations of both primitives and modules.
• Concurrent execution of both primitives and modules.
• Instance name is mandatory for modules but optional for primitives.
Gate Level Modeling
• A logic circuit can be designed using logic gates.
• Verilog supports basic logic gates as predefined primitives.
• These primitives are instantiated like modules
• Types:
• and/or gates
• buf/not gates buf not
• Tristate bufif0 bufif1 notif0 notif1
Verilog Primitive - And/or gates
Primitive gates
Features:
• 1-output, multiple inputs.
• Output transitions (0, 1, x).
• and i1 (output, input_1, input_2, …, input_n);
• nand i2 (output, input_1, input_2, …, input_n);
• or i3 (output, input_1, input_2, …, input_n);
• nor i4 (output, input_1, input_2, …, input_n);
• xor i5 (output, input_1, input_2, …, input_n);
• xnor i6 (output, input_1, input_2, …, input_n);
And/or Truth Table
Buf /Not gates
Tri-state Primitives
• Features:
• Has only 3 terminals.
• Output transitions (0, 1, x, z).
•bufif0 i1 (output, data input, control input);
• bufif1 i2 (output, data input, control input);
• notif0 i3 (output, data input, control input);
• notif1 i4 (output, data input, control input);
• Gate delay: signal propagation delay from any gate input to the gate output.
• Rise delay: refers to the transition to the ‘1’ value from any other value.
• Fall delay: refers to the transition to the ‘0’ value from any other value.
• Turn-off delay: refers to the transition to the high-impedance value (z), from any
other value.
• If the value changes to x, the minimum of the three delays is taken.
• One delay specification: If specified, it is used for all transitions.
and #(delay time) a1 (out, i1, i2);
and #(4) a1 (out, i1, i2);
• Two delay specification: If specified, they refer to rise and fall times.
or #(rise_del, fall_del) o1 (out, i1, i2);
or #(5, 6) o1 (out, i1, i2);
• Three delay specification: If specified, they refer to rise, fall and turn-off times.
bufif1 #(rise_del, fall_del, turn_off_del) b1 (out, in, crtl);
bufif1 #(2, 3, 5) b1 (out, in, crtl);
• Primitive gate delays allow three values each for the rise, fall and turn-off delays.
• The three values are minimum, typical and maximum, and the three are separated
by colons.
• Either of the three values can be selected at the start of the simulation (run time).
If no value is selected, typical value is the default.
• One delay specification with min:typ:max values.
and #(2:4:5) a1 (out, i1, i2);
risemin, fallmin = 2, risetyp, falltyp = 4, risemax, fallmax = 5.
• Two delay specification with min:typ:max values.
or #(1:5:3, 2:6:4) o1 (out, i1, i2);
risemin=1, risetyp=5, risemax=3, fallmin=2, falltyp=6, fallmax=4.
• Three delay specification with min:typ:max values.
bufif1 #(1:2:4, 1:3:5, 3:5:6) b1 (out, i1, i2);
risemin=1, risetyp=2, risemax=4, fallmin=1, falltyp=3, fallmax=5, turn-offmin=3, turn-offtyp=5, turn-
offmax=6.
Connecting Ports to External Signals
• There are two methods of making connections between signals specified in the
module instantiation and the ports in a module definition. These two methods
cannot be mixed.
• Connecting by ordered list
• Connecting ports by name
Connecting by ordered list
• Connecting by ordered list is the most intuitive method for most beginners.
• The signals to be connected must appear in the module instantiation in the same
order as the ports in the port list in the module definition
Connecting Ports by name
• For large designs where modules have, say, 50 ports, remembering the order of
the ports in the module definition is impractical and error-prone.
• Verilog provides the capability to connect external signals to ports by the port
names, rather than by position.
