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33-Design of Synchronous Sequential Circuits-21!03!2023

The document describes the steps to design a clocked sequential circuit from a given state diagram or specifications. The key steps are: 1) Derive the state table from the state diagram or specifications. 2) Apply state reduction techniques if possible to reduce the number of states. 3) Assign binary codes to each state. 4) Determine the number of flip-flops needed and derive the circuit excitation table from the state table. 5) Derive the flip-flop input equations and output equations. 6) Draw the logic diagram of the circuit. An example of applying these steps to design a sequential circuit from a given state diagram is also provided.

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85 views12 pages

33-Design of Synchronous Sequential Circuits-21!03!2023

The document describes the steps to design a clocked sequential circuit from a given state diagram or specifications. The key steps are: 1) Derive the state table from the state diagram or specifications. 2) Apply state reduction techniques if possible to reduce the number of states. 3) Assign binary codes to each state. 4) Determine the number of flip-flops needed and derive the circuit excitation table from the state table. 5) Derive the flip-flop input equations and output equations. 6) Draw the logic diagram of the circuit. An example of applying these steps to design a sequential circuit from a given state diagram is also provided.

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Dr.

Sathya P
Associate Professor
SENSE
State Reduction and Assignment
• The reduction in the number of flip flops in a sequential circuit is referred to as
the state –reduction problem.

• State reduction algorithms are concerned with procedures for reducing the
number of states in a state table while keeping the external input-output
requirements unchanged.

• Since m flip flops produce 2m states, reduction in the number of states result in
reduced number of flip flops.

• In order to design a sequential circuit with physical components, it is necessary to


assign unique coded binary values to the states.
Rule: If next state and output of two present states are same then we
can eliminate one state.
• Present state e = g, one can be eliminated.

• Present state d = f, one can be eliminated.


• No further reduction is possible.
Design of Clocked Sequential Circuit
• Steps:
1. From the word description and specifications of the desired operation, derive a state diagram
for the circuit. (State diagram or timing diagram usually given)
2. Obtain the state table.
3. Reduce the number of states if necessary using state reduction method.
4. Assign binary values to the states.
5. Determine the number of flip flops required and assign letter symbols.
6. Decide the type of flip flops to be used.
7. Derive the circuit excitation table from state table.
8. Derive the simplified flip flop input equations and output equations.
9. Draw the logic diagram.
• Example: Assume the state diagram is given for which the logic diagram is to be
designed.
0/0
• Step 1: State diagram
00
1/1
1/0
0/1
10
01

1/0
0/0
0/0
11

1/0
• Step 2: State Table

Present State Next state Output Y


x=0 x=1
+ + + +
QA QB QA QB QA QB X=0 X =1
0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
1 0 1 0 0 0 1 1
1 1 1 0 1 1 0 0

• Step 3: No two states are same, so state reduction is not possible.


• Step 4: State assignments
• a = 00
• b = 01
• c = 10
• d = 11
• Step 5: We have four states, hence two flip flops are required. Let the FFs be A
and B.
• Step 6: Let us choose T FF.
• Step 7: Circuit Excitation table from state table.

Q(t) Q(t+1) T
0 0 0
0 1 1 T = Q(t) Ꚛ Q(t+1)
1 0 1
1 1 0

• TA = QA Ꚛ QA+
• TB = QB Ꚛ QB+
• Circuit Excitation table:

Present State Input Next state FF inputs Output


QA QB X Q+
A Q+
B TA TB Y

0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 1 1 0 0
0 1 1 0 1 0 0 0
1 0 0 1 0 0 0 1
1 0 1 0 0 1 0 1
1 1 0 1 0 0 1 0
1 1 1 1 1 0 0 0
• Step 8: To derive FF input equation and output equation.
• TA = QA’QB X’ + QAQB’X
• TB = QA’QB’ X + QAQB X’

• Y = QA QB’X’ + QAQB’X
• Y = QA QB’(X’ + X)
• Y = QA QB’.1
• Y = QA QB’

• Step 9: Draw the logic circuit.

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