MP&MC 2m PDF
MP&MC 2m PDF
QUESTION BANK
UNIT-I
A stack pointer is a small register that stores the address of the last program request in
a stack. A stack is a specialized buffer which stores data from the top down. As new requests
come in, they "push down" the older ones.
Maximum mode
Minimum mode
A number of instructions appearing again & again in the main program can be
assigned as a macro definition (i.e.) a label is assigned to the repeatedly appearing string of
instructions. The process of assigning a label or macro name to the string is called defining a
macro. A macro within a macro is called a nested macro.
Stack register is also called as stack pointer and it is a register which holds the 16 bit offset
from the start of the segment to the top of the stack.
B1 B1 B1 B1 B1 B1 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
5 4 3 2 1 0
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
U U U U OF DF IF TF SF ZF U AF U PF U CF
PF: Parity flag- set if result has even parity; AF : Auxiliary carry flag - used for BCD
operation; ZF : Zero flag - set if result = 0; SF : Sign flag - set if result is –ve.
TF : Trap flag - set to enable single step execution mode. IF: Interrupt flag- set to enable
interrupt ;DF : Direction flag - set to enable auto decrement mode for string operation ;OF:
Overflow flag - used for signed arithmetic operation
A stack pointer is a small register that stores the address of the last program request in
a stack. A stack is a specialized buffer which stores data from the top down. As new requests
come in, they "push down" the older ones.
The assembler is a program used to convert an assembly language program into the
equivalent machine code modules that may be further converted to executable codes.
Therefore the hints given to the assembler to complete all these tasks in some predefined
alphabetical strings is called an assembler directive. E.g.: DB------define byte, END----end of
program, EQU-----equate
The parity flag is set, if the result of the byte operation or lower byte of the word
operation contains an even number of ones.
19. Which interrupt has got the highest priority among all the external interrupts?
The Non-Maskable Interrupt pin of 8086 has got the highest priority among the
external Interrupts.
While the execution unit executes the previously decoded instruction, the Bus
Interface Unit fetches the next instruction and places it in the pre fetched instruction byte
queue. This forms a pipeline.
21. What is the use of the Trap flag in the flag register of 8086?
When the Trap flag is set, the processor enters the single step execution mode. A trap
interrupt is generated after execution of each instruction. The processor executes the current
instruction and the control is transferred to the Trap interrupt service routine.
23. Give the operation of CBW and TEST instructions of 8086? (Nov 2013)
CBW instruction converts the byte in AL to word value in AX by extending the sign of
AL throughout the register AH. TEST instruction performs logical AND operation of the two
operands updating the flag registers without saving the result
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
The addressing modes clearly specify the location of the operand and also how its
location may be determined.
25. How is the physical address generated in 8086? (or) How 16 bit address is converted
into 20 bit address in 8086? (Nov 2013) (Apr/May 2017)
The content of the segment register called as segment address is shifted Left bit-wise four
times and to this result, content of an offset register also called as offset address is added, to
produce a 20-bit physical address.
eg: segment address 1005H
Offset address 5555H
Segment address 0001 0000 0000 0101
Shifted by 4 bit positions 0001 0000 0000 0101 0000
+
Offset address 0101 0101 0101 0101
Physical address 0001 0101 0101 1010 0101
1 5 5 A 5
For control transfer instructions, if the location to which the control is transferred lies in a
different segment other than the current one, the mode is called intersegment mode.
If the destination location lies in the same segment, the mode is called intra segment mode.
The XLAT (Translate) instruction replaces a byte in the AL register with a byte
from a 256-byte, user coded translation table.
XLAT is useful for translating characters from one code to another like ASCII to EBCDIC
and ASCII to HEX etc.
This input is examined by a “WAIT” instruction. When the processor executes WAIT
instruction, it enters into wait state (Idle state). If the TEST pin goes low, the processor will
come out from the idle state and continues the execution; otherwise it remains in an idle
state.
There is an interrupt vector table which stores the information regarding the location
of interrupt service routine (ISR) of various interrupt. Whenever an interrupt occurs the
memory location of ISR is determined using the vector table and the program control
branches to ISR after saving the flags and the program location.
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
31. What are the advantages of the segmented memory scheme in 8086?
PART-B
1. Draw and explain the architecture of 8086 with neat diagram. (April/May-
2018)(Nov/Dec-2017)
2. Explain in detail about interrupt and interrupt service routine s in 8086. (April/May-
2018)(Nov/Dec-2017)
4. Explain the various addressing modes of 8086 microprocessor with suitable diagram.
(Nov/Dec-2016).
5. Explain the data transfer , arithmetic and branch instructions with examples. (April/May-
2016)
9. Explain the memory concepts of Intel 8086 and explain how data transfer takes place.
10. i) Write an 8086 ALP to sort out any given ten numbers in ascending and descending
order. (Nov 2013)
ii) Give the functions of NMI, BHE and TEST pins of 8086. (4) (Nov 2013)
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
UNIT-II
PART-A
1. List two difference between maximum mode and minimum mode configuration of
8086 (April/May-2018)
In maximum mode 8086 generates QS1, In minimum mode 8086 generates INTA (bar),
QS0, S0 (bar), S1 (bar), S2 (bar), LOCK ALE, DEN (bar), DT/R (bar), M/IO (bar),
(bar), RQ (bar), GT1, RQ (bar)/GT0 HLDA, HOLD and WR (bar), control signals.
control signals.
So clearly there are multiple processes in There is only one processor in the system
the system. minimum mode.
Multitasking has the same meaning of multiprogramming but in a more general sense, as it
refers to having multiple (programs, processes, tasks, threads) running at the same time. This
term is used in modern operating systems when multiple tasks share a common processing
resource (e.g., CPU and Memory). Multiprogramming is a rudimentary form of parallel
processing in which several programs are run at the same time on a uniprocessor. Since there
is only one processor, there can be no true simultaneous execution of different programs.
It indicates to another system bus master, not to gain control of the system bus while LOCK
is active Low. The LOCK signal is activated by the "LOCK" prefix instruction and remains
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
active until the completion of the instruction. This signal is active Low and floats to tri-state
OFF during 'hold acknowledge.
ARM Processor
AMD Processor
SHARC processor.
In a loosely coupled multiprocessor system each CPU has its own bus control logic
and bus arbitration is resolved by extending this logic and adding external logic that is
common to all the modules.
The floating point coprocessor uses real data types or floating point types of the
following format: Real data X=±2exp×mantissa, which may vary from extremely small to
extremely large values.
The 8086/8088 must be supplemented with co-processors that extend the instruction
set to allow the necessary special computations to be accomplished more efficiently. Eg:
8087 Numeric Data Processor.
The system bus is a pathway composed of cables and connectors used to carry data
between a computer microprocessor and the main memory. The busprovides a
communication path for the data and control signals moving between the major components
of the computer system.
The internal data bus is the one responsible for transferring the data between the data
registers and each other or between the data registers and the CPU. The external data bus
transfers the data between the internal registers and the external memory or directly to the
output.
11. Define bus. Why bus request and cycle stealing are required? (April/May-2015)
Bus is a group of parallel conductors which carries data, address and control signals
from one unit to another unit. Bus request and Cycle stealing are required to access the RAM
without interfering with the CPU. It is similar to DMA for allowing I/O controllers to read or
write RAM without CPU intervention.
12. Draw the read cycle timing diagram for minimum mode. (April/May-2015)
The system bus is a pathway composed of cables and connectors used to carry data
between a computer microprocessor and the main memory. The bus provides a
communication path for the data and control signals moving between the major components
of the computer system.
If the processor supporting processor, clock generator, bus control logic, memory and I/O
System, communicate shared memory then it is called closely coupled system.
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
If the TC Stop bit is set the channel is disabled after the TC output goes high, thus
automatically preventing further DMA Operation on that channel.
PART-B
1. Discuss the maximum mode configurations of 8086 with neat diagram. Mention the
functions of each signals. (April/May-2018)
3. Explain the system bus structure of 8086. Draw the timing diagram for interrupt
acknowledgement cycle. (Nov/Dec-2017)
8. Write and ALP to check whether the given string I palindrome or not. (April/May-2015)
PART-C
1. Develop 8086 based system with 128 RAM and 4K ROM, to display the word HAPPY for
every 2ms in the common anode seven segment LED display. Explain the delay timings.
(Nov/Dec-2017).
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
UNIT-III
I/O INTERFACING
PART-A
1. Name the Command word to set bit PC, using BSR mode.
0 D6 D5 D4 D3 D2 D1 D0
2. Why the 8255A is designed so that only the bits in PORT C can be set/reset?
Since the pins are designed to activate for selecting Port A and Port B.
When a key is pressed the contact bounce back and forth and settle down only after a small
time delay (about 20ms). Even though a key is actuated once, it will appear to have been
actuated several times. This problem is called Key Bouncing
For transferring data between computers, laptops two methods are used, namely, Serial
Transmission and Parallel Transmission. There are some similarities and dissimilarities
between them. One of the primary differences is that; in Serial Transmission data is sent bit
by bit whereas, in Parallel Transmission a byte (8 bits) or character is sent.
6. How many I/O devices with a word length of 1 bit can be connected to 8255 PPI
7. How does 8255 PPI discriminate between the memory section data and I/O section
data
The 8255 PPI discriminate between memory section data and I/O Section by use of the
Address lines and by use of the decoder.
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
8. What is the function of STB and OBF signal in the 8255 when programmed for mode
–1 operation?
The input device activates this signal to indicate CPU that the data to be read is already sent
on the port lines of 8255 port.
1. Fully Nested Mode, 2.Special Fully Mode, 3.Rotating Priority Mode, 4.Special masked
Mode, 5.Polled Mode.
11. What is the maximum number of devices that can be connected to interrupt mode
With the help of SP/EN signal it can either be operated in Master mode and Salve Mode
CAS2-CAs0 is used for selecting one of the possible slaves that can be connected.
14. What is the use of address enable (AEN) pin of 8257 DMA Controller?
15. What is the use of the READY input of the DMA controller?
When the READY PIN is high the data connected to the external devices can be activated.
IC 8257 is used for transferring the data from memory to the CPU
TC is used for denoting that Terminal count of the data has been reached.
18. List the four possible modes of operation in 8237 DMA controller.
1.Rotating Priority Mode, 2.Fixed Priority Mode, 3.Extended Write Mode, 4.TC Stop Mode
Universal Synchronous and asynchronous Receiver and Transmitter is used for transmitting
and Receiving data
The device registers can be accessed and manipulated with any instruction or
addressing mode.
The maximum number of available memory locations is reduced.
During DMA data transfer, the I/O component connected to the system bus is given control
of the system bus for a bus cycle. This is called bus stealing or cycle stealing.
23. What are the advantages of Programmable Interval Timer/Counter IC? (May/Jun
2014)
24. Give the Various modes and Applications of 8254. (May/Jun 2015)(Apr/May 2018)
0 0 1 0 0 Write Counter 0
0 1 1 0 0 Write Counter 1
1 0 1 0 0 Write Counter 2
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
0 0 0 1 0 Read Counter 0
0 1 0 1 0 Read Counter 1
1 0 0 1 0 Read Counter 2
1 1 0 1 0 No operation
X X 1 1 0 No operation
X X X X 1 No operation
Direct Memory Access (DMA) is a capability provided by some computer bus architectures
that allows data to be sent directly from an attached device (such as a disk drive) to the
memory on the allows data to be sent directly from an attached device (such as a disk drive)
to the memory on the computer's motherboard. The microprocessor is freed from
involvement with the data transfer, thus speeding up the overall computer.
A control register is a processor register which changes or controls the general behavior of
a CPU or other digital device. Common tasks performed by control registers include
interrupt control, switching the addressing mode, paging control, and coprocessor control.
28. What are the differences between LED display and LCD display?(Nov/Dec 2018)
LED LED
PN-Junction device which discharge visible PN-Junction device which discharge visible
lights when an electrical charge passes lights when an electrical charge passes
through it. through it.
No backlight No backlight
NOP
DEC BP
JNZ LOOP1
DEC DI
JNZ LOOP
30. What are the handshake signals used in Mode – 2 configuration of 8255? (Nov/Dec
2017)
Only port A can be initialized in this mode. Port A can be used for bidirectional
handshake data transfer. This means that data can be input or output on the same eight lines
(PA0 - PA7). Pins PC3 - PC7 are used as handshake lines for port A. The remaining pins of
port C (PC0 - PC2) can be used as input/output lines if group B is initialized in mode 0 or as
handshaking for port B if group B is initialized in mode 1. In this mode, the 8255 may be
used to extend the system bus to a slave microprocessor or to transfer data bytes to and from
a floppy disk controller. Acknowledgement and handshaking signals are provided to maintain
proper data flow and synchronization between the data transmitter and receiver.
PART-B
1. Draw the block diagram and explain the concepts of USART. (April/May-2018)
4. Draw and explain the functional diagram of keyboard and display controller. (Nov/Dec-
2017)
5. Draw and explain the functional diagram of parallel communication interfacing chip.
(April/May-2017)
6. Explain the procedure of interfacing D/A and A/D converter circuit. (Nov/Dec-2016)
8. (i) Draw the block diagram of traffic light control system using 8086. (April/My-2015)
(ii). Write the algorithm and assembly language program for traffic light control system.
PART-C
1. Draw the block diagram of traffic light control system using 8086 Write the algorithm and
ALP for traffic control system.
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
UNIT-IV
PART-A
There are mainly four ports available in this 8051 micro controller. They are
Port0: serve as inputs, outputs, or, when used together, as a bi-directional low
order address and as data bus for external memory.
Port2: may be used as an input / output port similar in operation to port 1. The
alternate use of port2 is to supply a high-order address byte in conjunction with the Port0
low-order byte to address external memory.
Port3: is an input / output pin similar to the Port 1. In this case each and every pin has
an additional function.
RS0 and RS1 are the D3 and D4 bits present in the 8-bit register of the PSW
7. What is the difference between microprocessor and microcontroller? (May 2014)(Nov/Dec 2018)
It has only CPU It has CPU, memory, timers, parallel and serial I/O
port on single chip
It has few bit manipulating instructions It has large number of bit manipulating instructions
It has more number of instructions for transferring It has only few instructions for transferring data
data from external memory. from external memory.
No special function registers are available Special functions registers are available
The data pointer (DPTR) is the 16-bit address register that can be used to fetch any 8 bit data
from the data memory space. When it is not being used for this purpose, it can be used as two
eight bit registers, DPH and DPL
13. What is the difference between MOVX and MOV ? (Nov/Dec 2013)
The MOV instruction is used to access code space of on-chip ROM and MOVX instruction is
used to access data space or external memory.
8051 can access up to 64kb of program memory and 64kb of external data memory and
internal data RAM locations.
15. What are the different ways of operand addressing in 8051? (Apr/May 2016)
Different ways of addressing modes are1) Immediate addressing mode 2) Direct addressing
mode 3) Register direct addressing mode 4) Register indirect addressing mode 5) Indexed
addressing mode.
16. Write an 8051 ALP to toggle P1 a total of 200 times. Use RAM location 32H to hold
your counter value instead of registers R0-R7. (Apr/May 2016)
ACALL DELAY
ACC: Accumulator, B: B-Register, PSW: Program Status Word, SP: Stack Pointer, DPTR:
Data Pointer, IE: Interrupt Enable, SCON: Serial Control, PCON: Power Control.
8051 internal clock circuit. In this crystal of proper frequency can be connected to these two
pins. XTAL 1 is connected to GND and oscillator signal is connected to XTAL 2
19. Write an ALP to add the values ABH and 47H. Store the result in R1.
MOV A, #AB H
ADD A, #47 H
MOV R1, A
L1: SJMP L1
SETB PSW.4
SETB PSW.3
The ACALL instruction calls a subroutine located at the specified address. The PC is
incremented twice to obtain the address of the following instruction. The 16-bit PC is then
stored on the stack (low-order byte first) and the stack pointer is incremented twice. No flags
are affected. The LCALL instruction calls a subroutine located at the specified address. This
instruction first adds 3 to the PC to generate the address of the next instruction. This result is
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
pushed onto the stack low-byte first and the stack pointer is incremented by 2. The high-order
and low-order bytes of the PC are loaded from the second and third bytes of the instruction
respectively. Program execution is transferred to the subroutine at this address. No flags are
affected by this instruction.
25. What is the operation of the given 8051 microcontroller instruction XRL A?
The XRL instruction performs a logical exclusive OR operation between the specified
operands. The result is stored in the destination operand.
MOV A, #data1
MOV B, #data2
MUL AB
MOVX @ DPTR, A
INC DPTR
MOV A,B
MOVX @ DPTR, A
27. Write a program to perform 2’s complement of a given number using 8051?
MOVX A, @ DPTR
CPL A
ADD A,#01H
INC DPTR
28. Which port used as multifunction port? List the signals. (Apr/May 2017)
Port 3 has multifunction port. Each pin of port 3 has i/o or as of one of the alternate
function.
Signals are:
P3.0– RXD
P3.1– TXD
P3.4– T0
P3.5- T1
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
32. What are the manipulation instructions? Give two examples.(Apr/May 2018)
Bit Handling (Bit Manipulation) is the act of algorithmically manipulating bits or
other pieces of data shorter than a word. 8051 microcontroller supports bit manipulation.
The following are the bit handling instructions supported by 8051.
CLR bit. Zero the specified bit.
SETB bit. Putting a specified bit.
CPL bit. Complement the bit indicated.
ANL C. AND (Y) between the carry logic and the bit indicated.
ORL C. OR (O) and carry logic between the specified bit.
33. What are the Addressing Modes for a Micro Controller?(Nov/Dec 2018)
In 8051 There are six types of addressing modes.
PART-B
1. Draw & explain the pin configuration of 8051 in detail (May 2014)(Nov/Dec 2018)
2. Explain in detail the different addressing modes supported by 8051.(Apr/May 2018)
3. Draw the architecture of 8051 and explain.(16) Apr/May 2016)(Nov/Dec 2017)(Apr/May 2018)
4. Write an 8051ALP to create a square wave of 66% duty cycle on bit 3 of port1.(Apr/May 2016)
5. Explain the instruction set of 8051? (May 2015)
6. Explain the I/O structure of 8051 (8) (Nov 2013) (May 2014)
7. List the special function registers of 8051 TMOD, SMOD and explain their functions.
(May 2015)(Nov/Dec 2018)
8. Explain the significance of SFR’s in 8051.
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
UNIT-V
INTERFACING MICROCONTROLLER
PART-A
1. What is the difference between watch dog timer and ordinary timer? (Nov 2013)
The watch dog timer is provided for the system to check itself and reset if it is not
functioning properly. It is a 16 bit-counter which is incremented every state time. watchdog
timer is based on a counter that counts down from some initial value to zero.
2. What is the relation between RPM and steps per second in stepper motor interfacing?
6. What is the basic difference between a timer and a counter? (May 2015)
The only difference between a timer and a counter is the source of clock pulses to the
counters. When used as a timer, the clock pulses are sourced from the oscillator through the
divide-by-12d circuit. When used as a counter, pin T0 (P3.4) supplies pulses to counter 0, and
pin T1(P3.5) to counter 1.
TMOD (Timer mode) register is used to set the various timer operation modes. TMOD is
dedicated solely to the two timers (T0 & T1) and can be considered to be two duplicate 4-bit
registers, each of which controls the action of the timers
When D7 pin=1 and RS pin=0 the BUSY flag is set which means that LCD is busy taking
care of internal operations and will not accept any new information. Therefore we have to
check BUSY flag before writing data to LCD.
WR is an active low input and when it undergoes low to high transition the Start of
conversion signal is given. INTR is an active low output pin. It is normally high when the A
to D conversion is finished. It goes low to signal EOC.
MOV A.#00H
MOV P1,A
BACK: INC A
SJMP BACK
EC 8691 – Microprocessors and Microcontrollers Department of ECE 2021-2022
PSEN (Program Store Enable) is an output signal for the 8051 microcontroller, which is
connected to the OE pin of external ROM containing the program code. This is used when
external ROM has to be accessed.
SBUF stands for SERIAL BUFFER. SBUF is physically two registers. One is write only and
is used to hold the data to be transmitted out of the 8051 via TXD. The other one is read only
and holds the received data from external sources via RXD.
Mode 0, Mode 1, Mode 2, Mode 3 is the serial communication modes available in 8051.
SM0 - Serial port mode bit 0, SM1 - Serial port mode bit 1, SM2 - Serial port mode 2 bit
multiprocessor communication enable bit; REN - Reception Enable bit.
TB8 - Transmitter bit 8. RB8 - Receiver bit 8 or the 9th bit received in modes 2 and 3, TI - Transmit
Interrupt flag & RI - Receive Interrupt flag.
7 6 5 4 3 2 1 0
19. What are the various baud rates possible in 8051 and how are they set?
9600 -3 FD
4800 -6 FA
2400 -12 F4
1200 -24 E8
20. What are the various types of sensors that can be interfaced with 8051? (Apr/ May
2018)
a flag to indicate that each timer has overflowed. Some non-timer related bits are located in
the TCON SFR. These bits are used to configure the way in which the external interrupts are
activated.
In serial communication the data is rate known as the baud rate, which simply means the
number of bits transmitted per second. In the serial port modes that allow variable baud rates,
this baud rate is set by timer 1. The 8051 serial port is full duplex.
Interrupt is a signal to the microprocessor from a device that requires attention. The
microprocessor will respond by setting aside execution of its current task and deal with the
interrupting device. When the interrupting device has been dealt with, the microprocessor
continues with its original task as if it had never been interrupted.
In Polling the processor continuously polls or tests every device in turn as to whether it
requires attention (e.g. has data to be transferred). The polling is carried out by a polling
program that shares processing time with the currently running task
MOV TH0,#0FCH
MOV TL0,#018H
SETB TR0
HERE: JNB TF0,HERE
CLR TR0
CLR TF0
RET
27. List the 8051 interrupts with its priority (Apr/May 2018)(Nov/Dec 2017)
Types of Interrupts in 8051 Microcontroller
The 8051 microcontroller can recognize five different events that cause the main program to
interrupt from the normal execution. These five sources of interrupts in 8051are:
Industrial Machines – Stepper motors are used in automotive gauges and machine tooling
automated production equipment’s. Security – new surveillance products for the security
industry. Medical – Stepper motors are used inside medical scanners, samplers, and also
found inside digital dental photography, fluid pumps, respirators and blood analysis
machinery. Consumer Electronics Stepper motors in cameras for digital camera focus and
zooming
Polling is mostly used for time delay generation and interrupt method is more useful
when waveforms are to be generated or some action has to be repeated in fixed delays.
PART-B
1. Draw the block diagram of Intel 8051 timer/counter and explain its different modes of
operations. (May 2015)(Apr/May 2018)
2. What are the different timer mode operations of 8051? Explain them in detail.
3. Explain how to interface ADC and DAC with 8051 in detail with neat diagram.(Nov/Dec
2017)
6. With necessary hardware & software details explain how to interface LCD’S with 8051
(May 2015)
7. Explain the different modes of operation of serial port in 8051, indicating various registers
associated with it./ Illustrate the serial communication of 8051, SCON (Apr/May
2016)(Nov/Dec 2017)(Nov/Dec 2018)
9. (i) Vin=2.25V, Vref=5V, NO. of data lines are 5. Convert the given analog quantity to its
equivalent digital output quantity. (May 2014)
(ii) Explain the different techniques to convert digital quantity to its equivalent analog
quantity.
10. Explain in detail the procedure to interface stepper motor with 8051 and write an ALP to
run the stepper motor in both forward and reverse direction with delay. (May
2015)(Apr/May 2018).
11. Write a program for generation of unipolar square waveform of 1KHZ frequency using
Timer 0 of 8051 in mode 0. Consider the system frequency as 12 MHZ. (Apr/May
2017)(Nov/Dec 2017)
12. How Microprocessor and Microcontrollers are different from computer based
controllers?(Nov/Dec 2018)
13. How Microprocessor and Microcontrollers can help to Control a Process or a Machine
tool?(Nov/Dec 2018)
VSB ENGINEERING COLLEGE KARUR
Department of Electronics and Communication Engineering
Question Bank
EC8095 – VLSI DESIGN
UNIT I
INTRODUCTION TO MOS TRANSISTOR
1. What is Moore’s law?
Moore’s law states that the number of transistor would double every 18 months.
2. What is CMOS technology?
Complementary Metal Oxide Semiconductor (CMOS) in which both n-channel MOS and
p-channel MOS are fabricated in the same IC.
3. What are the advantages of CMOS over NMOS technology?
In CMOS technology the aluminum gates of the transistor are replaced by poly
silicon gate.
The main advantage of CMOS over NMOS is low power consumption.
In CMOS technology the device sizes can be easily scalable than NMOS.
4. What are the advantages of CMOS technology?
Low power consumption.
High performance.
Scalable threshold voltage.
High noise margin.
Low output drive current.
5. What are the disadvantages of CMOS technology?
Low resistance to produce deviations and temperature changes.
Low switching speed at large values of capacitive loads.
6. What is design rule? (Nov/Dec 2016)
Design rules are the communication link between the designer specifying
requirements and the fabricator who materializes them. The design rule conform to a set
of geometric constraints or rule specify the minimum allowable line widths for physical
objects on-chip such as metal and poly silicon interconnects or diffusion area, minimum
feature dimensions and minimum allowable separations between two layers.
7. What is stick diagram? (Nov/Dec 2017)
Stick diagram are the key element of designing a circuit used to convey layer
information through the use of a color code .
8. What is micron design rule?
Micron rules specify the layout constraints such as minimum feature sizes and
minimum allowable feature separations are stated in terms of absolute dimensions in
micrometers.
9. What is Lambda design rule? (Nov/Dec 2015)
Lambda rule specify the layout constraints such as minimum feature sizes and
minimum allowable feature separations are stated in terms of a single parameter (λ)
and thus allow linear, proportional scaling of all geometrical constraints.
10. What is DRC?
Design Rule Check program looks for design rule violations in the layout. It
checks for minimum spacing and minimum size and ensures that combinations of
layers from legal components.
1
11. Mention MOS transistor characteristics?
o Metal Oxide Semiconductor is a three terminal device having source, drain and gate.
o The resistance path between the drain and the source is controlled by applying a
voltage to the gate.
o The Normal conduction characteristics of an MOS transistor can be categorized as
cut-off region Non saturated region and saturated region.
12. Compare NMOS and PMOS?
NMOS PMOS
The majority carriers are electron The majority carriers are holes
Positive voltage is applied at the gate Negative voltage is applied at the gate
terminal terminal
NMOS conducts at logic 1 PMOS conducts at logic 0
Mobility of electron is high Mobility of electron is low
Switching speed is high Switching speed is low
3
The threshold voltage VT is not a constant with respect to the voltage difference
between the substrate and the source of the MOS transistor. This effect is called the body
effect or substrate bias effect.
5
46. What are the different color codes used for single poly silicon nMOS
technology?
n-diffusion (n-diff.) and other thinoxide regions -green
Polysilicon (poly.) - red
Metal 1 (metal) - blue
Implant - yellow
Contacts - black or brown (buried)
47. What are design rules?
Design rules are the communication link between the designer specifying
requirements and the fabricator who materializes them. Design rules are used to produce
workable mask layouts from which the various layers in silicon will be formed or
patterned.
48. Define a superbuffer.
A superbuffer is a symmetric inverting or noninverting gate that can supply or
remove large currents and switch large capacitive loads faster than a standard inverter.
50. Draw the stick diagram of static 2-input NAND gate.(Nov/Dec 2018).
6
UNIT II
COMBINATIONAL MOS LOGIC CIRCUITS
1. Draw the circuit of a nMOS inverter.
.
2. Give the expression for pull-up to pull-down ratio ( Zpu/Zpd) for an nMOS
inverter driven by another nMOS inverter.
.
3. Draw the circuit of a CMOS inverter.
7
6. What is Channel-length modulation?(Apr/May 2017)
The current between drain and source terminals is constant and independent of the
applied voltage over the terminals. This is not entirely correct. The effective length of the
conductive channel is actually modulated by the applied VDS, increasing VDS causes the
depletion region at the drain junction to grow, reducing the length of the effective
channel.
7. Define Rise time
Rise time, tr is the time taken for a waveform to rise from 10% to 90% of its steady-state
value.
8. Define Fall time
Fall time, tf is the time taken for a waveform to fall from 90% to 10% of its steady-state
value.
9. Define Delay time
Delay time, td is the time difference between input transition (50%) and the 50% output
level. This is the time taken for a logic transition to pass from input to output.
10. Give some of the important CAD tools.
Some of the important CAD tools are:
i) Layout editors
ii) Design Rule checkers (DRC)
iii) Circuit extraction
11. What are two components of Power dissipation.
There are two components that establish the amount of power dissipated in a
CMOS circuit. These are:
i) Static dissipation due to leakage current or other current drawn continuously from the
power supply.
ii) Dynamic dissipation due to
- Switching transient current
- Charging and discharging of load capacitances.
12. Define Elmore delay model?
It is an analytical method used to estimate the RC delay in a network. Elmore
delay model estimates the delay of a RC ladder as the sum over each node in the ladder
of the resistance Rn-1 between that node and a supply multiplied by the capacitor on
the nodes.
13. What are the general properties of Elmore delay model?
General property of Elmore delay model network has
i) Single input node.
ii) All the capacitors are between a node and ground.
iii) Network does not contain any resistive loop.
14. What are the types of power dissipation? (Apr/May 2019)(Apr/May 2018)
i) Static power dissipation (due to leakage current when the circuit is idle).
ii) Dynamic power dissipation(when the circuit is switching) and
iii) Short –circuit power dissipation during switching of transistors.
15. What is static power dissipation?
Power dissipation due to leakage current when the idle is called the static
power dissipation. Static power due to
i) Sub – threshold conduction through OFF transistors
ii) Tunneling current through gate oxide
iii) Leakage through reverse biased diodes
8
iv) Contention current in radioed circuits.
16. What is Dynamic power dissipation ?
Power dissipation is due to circuit switching to charge and discharge the
output load capacitance at a particular node at operating frequency is called Dynamic
power dissipation.
The Dynamic power dissipation at a particular output node is given by
Pd=CL Vdd^2 Fclk . a
Where, CL = load capacitance ; a = activity factor ;Vdd =power supply ;
Fclk= operating frequency
17. What are the methods to reduce dynamic power dissipation ?
1. Reducing the product of capacitance and its switching frequency .
2. Eliminate logic switching that is not necessary for computation.
3. Reduce activity factor Reduce supply voltage
18. What are the methods to reduce static power dissipation ?
1. By selecting multi threshold voltages on circuit paths with low-Vt transistors
while leakage on other paths with high-Vt transistors.
2. By using two operating modes, active and standby for each function blocks.
3. By adjusting the body bias (i.e) adjusting FBB (Forward Body Bias) in active mode
to
increase performance and RBB (Reverse Body Bias) in standby mode to reduce
leakage.
4. By using sleep transistors to isolate the supply from the block to achieve
significant leakage power savings.
19. What is short circuit power dissipation ?
During switching, both NMOS and PMOS transistors will conduct
simultaneously and provide a direct path between Vdd and the ground rail resulting in
short circuit power dissipation.
20. Define design margin ?
The additional performance capability above required standard basic system
parameters that may be specified by a system designer to compensate for uncertainties is
called design margin. Design margin required as there are three sources of variation-
two environmental and one manufacturing.
21. Write the applications of transmission gate ?
i) Multiplexing element of path selector
ii) A latch element An unlock switch
iii) Act as a voltage controlled resistor connecting the input and output.
22. What is pass transistor?
It is a MOS transistor, in which gate is driven by a control signal the source (out),
the drain of the transistor is called constant or variable voltage potential(in) when the
control signal is high, input is passed to the output and when the control signal is low,
the output is floating topology such topology circuits is called pass transistor.
23. List the advantages of pass transistor?
i) Pass transistor logic (PTL) circuits are often superior to standard CMOS circuits in
terms of layout density, circuit delay and power consumption.
ii) They do not have path VDD to GND and do not dissipate standby power (static power
dissipation).
24. What is transmission gate ?
The circuit constructed with the parallel connection of PMOS and NMOS with
shorted drain and source terminals. The gate terminal uses two select signals s and s,
when s is high than the transmission gates passes the signal on the input. The main
9
advantage of transmission gate is that it eliminates the threshold voltage drop.
25. Why low power has become an important issue in the present day VLSI circuit
realization?
Indeep submicron technology the power has become as one of the most important issue
because of:
Increasing transistor count;
the number of transistor is getting doubled in every 18 months based on moore's
law higher speed of operation;
the power dissipation is proportional to clock frequency greater device leakage
current;
in nanometer technology the leakage component become a significant percentage
of the total power and the leakage current increases at a faster rate then dynamic
power in technology generations.
26. What are the various ways to reduce the delay time of a CMOS inverter ?
Various ways for reducing the delay time are given below:
a) The width of the MOS transistor can be increased to reduce delay. This is
known as gate sizing.
b) The load capacitance can be reduced to reduce delay. This is achieved by
using transistor of smaller and smaller dimension by feature generation
technology.
c) Delay can also be reduced by increasing the supply voltage Vdd and/or
reducing the threshold voltage Vt of the MOS transistors
27. Explain the basic operation of a 2- phase dynamic circuit?
The operation of the circuit can be explained using precharge logic in which the
output is precharged to HIGH level during Φ2 clockand the output is evaluated during
Φ1 clock.
28. What makes dynamic CMOS circuits faster than static CMOS circuits ?
As MOS dynamic circuits require lesser number of transistor and capacitance
is to be driven by it.this makes MOS dynamic circuits faster.
29. What is glitching power dissipation?
Because of finite delay of the gates used to realize Boolean functions, different
signals cannot reach the inputs of a gate simultaneously. This leads to spurious transition
at the output before it settles down to its final value. The spurious transition leads to
charging and discharging of the outputs causing glitching power dissipation. It can be
minimized by having balanced realization having same delay at the inputs.
30. List various sources of leakage currents?
Various source of leakage currents are listened below:
I1=Reverse-bias p-n junction diode leakage current.
I2=band-to-band tunneling current
I3=Subthreshold leakage current
I4=Gate oxide tunneling current
I5=Gate current due to hot carrier junction
I6=Channel punch through
I7=Gate induced drain leakage current
31. Compare and contrast clock gating versus power gating approaches.
Clock gating minimizes dynamic power by stopping unnecessary
transitions,but power gating minimizes leakage power by inserting a high Vt transistor
in series with low Vt logic blocks.
10
UNIT III
SEQUENTIAL CIRCUIT DESIGN
1. What are the classification of CMOS circuit families ?
i) Static CMOS circuits.
ii) Dynamic CMOS circuits.
iii) Ratioed circuits.
iv) Pass-transistor circuits.
2. What is the characteristics of Static CMOS design ?
A static CMOS circuit is a combination of two networks – the pull-up network
(PUN) and the pull-down network (PDN) in which at every point in time, each gate
output is connected to either VDD or VSS via a low resistance line.
3. List the important properties of Static CMOS design ?
i) At any instant of time, the output of the gate is directly connected to VDD and VSS.
ii) The function of the PUN is provide a connection between the output and VDD.
iii) The function of the PDN is provide a connection between the output and VSS .
iv) Both PDN and PUN are constructed in mutually exclusive way such that one and
only one of the networks is conducting in steady state. That is, the output node is
always a low-impedance node in steady state.
4. What is Dynamic CMOS logic ?
Dynamic circuits rely on the temporary storage of signal values on the capacitance of
high impedance node.
i) Requires only N+2 transistors.
ii) Takes a sequence of precharge and conditional evaluation phases to
realizes logic functions.
5. What are the properties of Dynamic logic ?
Logic function is implemented by pull-down network
only.
Full swing outputs (VOL= GND and VOH = VDD).
Non-ratioed.
Faster switching speeds.
Needs a precharge clock.
6. What are the disadvantages of dynamic CMOS technology ?
A fundamental difficulty with dynamic circuits is a loss of noise immunity and a
serious timing restriction on the inputs of the gate.
Violate monotonicity during evaluation phase.
7. What is CMOS Domino logic ?
A static CMOS inverter placed between dynamic gates which eliminate the
monotonicity problem in dynamic circuits are called CMOS Domino logic.
8. What is called static and dynamic sequencing element ?
A sequencing element with static storage employs some sort of feedback to
retain its output value indefinitely.
A sequencing element with dynamic storage generally maintain its value as
charge on a capacitor that will leak away if not refreshed for a long period of time.
11
9. What is clock skew ?(Apr/May 2018)
In reality clocks have some uncertainty in their arrival times that can cut into
the time available for useful computation is called clock skew.
10. What are synchronizers ?
Synchronizers are used to reduce metastability. The synchronizers ensure
synchronization between asynchronous input and synchronous system.
11. What is the difference between melay and moore state machines?
In the melay state machine we can calculate the next state and output both from
the input and state. But in the moore state machine we can calculate only next state but
not output from the input and the state and the output is issued according to next state.
12. Define propagation delay and contamination delay?
Propagation delay(t pd): The amount of time needed for a change in a logic input
to result in a permanent change at an output,that is the combinational logic will not show
any further output changes in response to an input change alter time fod units
Contamination delay (tea): The amount of time needed for a change in a logic
input to result in an initial change at an output, that is the combinational logic is
guaranteed not to show any output change in response to an input change before fed
time units have passed.
13. Define Setup time and Hold time.
Setup time (t setup): The amount of time before the clock edge that data input D must
be stable the rising clock edge arrives.
Hold time (t hold): This indicates the amount of time after the clock edge arrives the
data input D must be held stable in order for FF to latch the correct value. Hold time is
always measured from the rising clock edge to a point after the clock edge.
14. Difference between latches and Flip-Flop.(Apr/May 2018)
S.No Latch Flip-Flop
1. A Latch is Level-Sensitive A FF is edge triggered.
A latch stores when the clock
A FF stores when the clock rises
2. level is low and is transparent
and is mostly never transparent.
when the level is high.
15. Define Pipelining. (Apr/May 2017)
Pipelining is a popular design technique often used to accelerate the operation of
the data path in digital processors. The major advantages of pipelinig are to reduce
glitching in complex logic networks and getting lower energy due to operand isolation.
16. How the limitations of a ROM-based realization is overcome in a PLA-based
realization.
In a ROM, the encoder part is only programmable and use of ROMs to realize
Boolean functions is wasteful in many situations because there is no cross-connect for a
significant part. This wastage can be overcome by using Programmable Logic
Array(PLA), which requires much lesser chip area.
17. In what way the DRAMs differ from SRAMs?
Both SRAMs and DRAMs are volatile in nature, ie. Information is lost if power
line is removed. However SRAMs provide high switching speed, good noise margin
but require large chip area than DRAMs.
18. Explain the read and write operations for a one-transistor DRAM cell.
A significant improvement in the DRAM evolution was to realize 1-T DRAM
cell. One additional capacitor is explicitly fabricated for storage purpose. To store 'I', it is
charged to store '0' it is discharged to '0' volt. Read operation is destructive. Sense
12
amplifier is needed for reading. Read operation is followed by restoration operation.
19. What is MTBF ?
MTBF=(1/P(failure)) = ( Ti e(Ti=tsetup/ti)/Nto)
20. What do you meant by Max delay constraint and Min delay constraint ?
Min delay constraint: the path begins with the rising edge of the clock triggering F1. The
data may begin to change at Q1 after a clk-to-Q contamination delay. However, it must
not reach D2 until at least the hold after the clock edge, lest it corrupt the contents of F2.
Hence, we solve for minimum logic contamination delay :
tcd >= thold – tccq
Max delay constraint : the path begins with the rising edge of the clock triggering F1.
The data must propagate to the output of the flipflop Q1 and through the combinational
logic to D2, setting up at F2 before the next rising clock edge. Under ideal conditions,
the worst case propagation delays determine the minimum clock period for this
sequential circuitry
Tc >= tpcq + tpd + tsetup
21. What are the static properties of complementary CMOS Gates?
a. They exhibit rails-to-rail swing with VOH = VDD and VOL = GND.
b. The circuits have no static power dissipation, since the circuits are
designed such that the pull-down and pull-up networks are mutually exclusive.
c. The analysis of the DC voltage transfer characteristics and the noise
margins is more complicated than for the inverter, as these parameters depend upon the
data input patterns applied to the gate.
22. Draw the equivalent RC model for a two-input NAND gate.
23. What are the major limitations associated with complementary CMOS gate?
a. The number of transistors required to implement an N fan-in gate is
2N. This can result in a significantly large implementation area.
b. The propagation delay of a complementary CMOS gate deteriorates
rapidly as a function of the fan-in.
24. What is meant by ratioed logic?
In ratioed logic, a gate consists of an nMOS pull-down network that realizes the logic
function and a simple load device, which replace the entire pull-up network. A ratioed
logic which uses a grounded pMOS load is referred to as a pseudo-nMOS gate
25. What is true single phase clocked register?
The True single-phase clocked register (TSPCR) uses a single clock, CLK. For the
positive latch, when CLK is high, the latch is in the transparent mode and corresponds to
two cascaded inverters; the latch is non-inverting, and propagates the input to the output.
13
On the other hand, when CLK=0, both inverters are disabled, and the latch is in the hold
mode.
26. Define a tally circuit.
A tally circuit counts the number of inputs that are high and outputs the answer. If
there are N inputs there are N +1 possible outputs, corresponding to 0, 1, 2, …. N inputs
that are high.
29. Draw the CMOS implementation of 4-to-1 MUX using transmission gates .
14
30. What are the types of programmable device?
Programmable logic structure
Programmable Interconnect
Reprogrammable gate array
31. What is CLB?
CLB means Configurable Logic Block.
32. What are the two types of MOSFET?
Two types of MOSET are n-channel MOSET and p-channel MOSFET. These are
known as n-MOS and p-MOS.
33. Which MOS can pass logic 1 and logic 0 strongly?
p-MOS can pass strong logic 1
n-MOS can pass strong logic 0
34. What is AOI logic function?
AND OR Invert logic function (AOI) implements operation in the order of AND,
OR,NOT operations. So this logic function is known as AOI logic function.
35. What is bubble pushing?
According to De Morgan’s laws,
= +
+ =
So NAND gate may be drawn as bubbled OR gate. Bubbles are introduced in the input
side. This concept is known as bubble pushing.
36. Implement y = using bubble pushing concept?
Y= can be implemented using bubbled AND gate.
= +
37. What is OAI 221 Gate?
OAI 221, here 221 refers to number of inputs in each section.
38. Write the features of CMOS Domino Logic?
These structures occupy small area compared with conventional logic structure.
Parasitic capacitance is to be small to increase the speed.
Each gate can make one ‘logic 1’ to ‘logic 0’ transition.
39. What are the tally circuits?
Tally circuits one of the applications of the pass transistor logic.
It is used to count the number of inputs which are high and the output is produced.
40. What are the various forms of inverter based CMOS logic?
15
i. Pseudo N-MOS logic
ii. Dynamic C-MOS logic
iii. Clocked C-MOS logic
iv. C-MOS domino logic
v. n-p C-MOS logic
41. What is PIP in XILINIX?
PIP means Programmable Interconnect Point in XILINIX.
42. What are the advantages and disadvantages of PLA?
Advantages of PLA
Simplicity
Small size
Disadvantages of PLA
Speed problem occur (pull-ups may become slow on large terms )
43. What are the various modeling used in Verilog?
1. Gate-level modeling
2. Data-flow modeling
3. Switch-level modeling
4. Behavioral modeling
18
UNIT IV
DESIGN OF ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM
1. How path can be implemented in VLSI system?
A data path is best implemented in a bit –sliced fashion. A single layout is used
respectively for every bit in the data word. This regular approach eases the design effort
and results in fast and dense layouts.
2. Comment on performance of ripple carry adder.
A ripple carry adder has a performance that is linearly proportional to the number of
bits. Circuit optimizations concentrate on reducing the delay of the carry path. A number of
circuit topologies exist providing that careful optimization of the circuit topology and the
transistor sizes helps to reduce the capacitance on the carry bit.
3. What is the logic of adder for increasing its performance ?
Other adder structures use logic optimizations to increase the performance (carry
bypass, carry select, carry look ahead). Performance increase comes at the cost area.
4. What is multiplier circuit ?
A multiplier is nothing more than a collection of cascaded adders. Critical path
is far more complex and optimizations are different compared to adders.
5. Which factors dominate the performance of programmable shifter ?
The performance and the area of a programmable shifter are dominated by the wiring.
6. What is meant by data path ?
A data path is a functional units, such as arithmetic logic units or multipliers, that
perform data processing operations, registers and buses. Along with the control unit it
composes the central processing unit.
7. Write down the expression for worst-case delay for RCA.
t = (n-1)tc+ts
8. Write down the expression to obtain delay for N-bit carry bypass adder.
tadder = tsetup +Mtcarry +(N/M-1)tbypass +(M-1)tcarry + tsum
9. Define Braun multiplier.
The simplest multiplier is the Braun multiplier. All the partial products are
computed in parallel, and then collected through a cascade of Carry Save Adders. The
completion time is limited by the depth of the carry save array, and by the carry
propagation in the adder. This multiplier is suitable for positive operands.
10. Why we go to Booth’s algorithm ?
19
Booth algorithm is a method that will reduce the number of multiplicand multiples.
For a given number of ranges to be represented , a higher representation radix leads to
fewer digits.
11. Draw the truth table for Modified booth’s algorithm.
X2n+1 X2n X2n-1 f(2n) f(2n)Y
0 0 0 0 0
0 0 1 1 Y
0 1 0 1 Y
0 1 1 2 2Y
1 0 0 -2 -2Y
1 0 1 -1 -Y
1 1 0 -1 -Y
1 1 1 0 0
12. List the different types of shifter.
Array shifter
Barrel shifter
Logarithm shifter
13. Give the basic nMOS PLA structure.
The basic PLA structure consists of an AND plane driving an OR plane. The
terminology corresponds to a sum of products (SOP) realization of the desired function. The
SOP realization converts directly into a NAND-NAND implementation. When a product of
sums (POS) realization is desired, it can be implemented in OR-AND or NOR-NOR logic.
In either case, the first array is referred to as the AND plane, and the second array as the OR
plane. The line connecting the AND plane to the OR plane are called the product lines.
14. What do you mean by CMOS PLA.
The basic CMOS PLA is obtained by providing a well and replacing the pull-up
devices in the NAND-NAND array or in the NOR- NOR array with enhancement mode
pMOS devices. The CMOS array can be precharged or not, and can be clocked 2 AND
plane OR plane Register Register In puts Outputs 1 with the same two-phase clocking
scheme as used for the MOS PLA. CMOS PLA design offers many more varieties of layout
than does nMOS.
15. Define finite state machine.
When feedback is added to the AND OR PLA structure, the PLA becomes a finite
state machine (FSM). An FSM can be designed as a Mealy Machine or a Moore Machine.
The Mealy machine has outputs, which may change with input changes in an asynchronous
manner and cause erroneous behavior. Hence, the Mealy machine should be avoided
whenever possible. The Moore machine has outputs which depend upon and change only
20
with state changes, since all the outputs of the Boolean-logic block go through a state
register, and are synchronously clocked.
16. What are the importance of the PLA/FSM in VLSI?
(i) Regularity : It has a standard, easily expandable layout.
(ii) Convenience : Little design effort is required.
(iii) Compacted : It is efficient for small circuits.
(iv) Modularity : It makes it possible to design hierarchical PLAs and
FSMs into large sequential systems.
(v) Suitability to being computer generated.
17. Give the structure of a CPLD.
A CPLD comprises multiple circuit blocks on a single chip, with internal wiring
resources to connect the circuit blocks. Each circuit block is similar to a PLA or a PAL.It
includes four PAL like blocks that are connected to a set of interconnection wires. Each
PAL like block is also connected to a sub circuit labeled I/O block, which is attached to a
number of the chip’s input and output pins.
21
20. What is meant by FPGA?
A field programmable gate array (FPGA) is a programmable logic device that
supports implementation of relatively large logic circuits. FPGAs can be used to implement
a logic circuit with more than 20,000 gates whereas a CPLD can implement circuits of upto
about 20,000 equivalent gates. FPGAs are quite different from CPLDs because FPGAs do
not contain AND or OR planes. Instead, they provide logic blocks for implementation of the
required functions.
23
Channeled Gate Array Channel less Gate Array
1. Only the interconnect is customized only the top few mask layers are customized.
2. The interconnect uses predefined spaces between rows of base cells. No predefined areas
are set aside for routing between cells.
3. Routing is done using the spaces Routing is done using the area of transistors unused.
4. Logic density is less Logic density is higher.
38. What is a FPGA?
A field programmable gate array (FPGA) is a programmable logic device that supports
implementation of relatively large logic circuits. FPGAs can be used to implement a logic
circuit with more than 20,000 gates whereas a CPLD can implement circuits of upto about
20,000 equivalent gates.
39. What are the different methods of programming of PALs?
The programming of PALs is done in three main ways:
• Fusible links
• UV – erasable EPROM
• EEPROM (E2PROM) – Electrically Erasable Programmable ROM
40. What is an antifuse?(Nov/Dec 2016)
An antifuse is normally high resistance (>100MW). On application of appropriate
programming voltages, the antifuse is changed permanently to a low-resistance
structure (200-500W).
41. What are the different levels of design abstraction at physical design.
• Architectural or functional level
• Register Transfer-level (RTL)
• Logic level
• Circuit level
24
48. Give some circuit maladies to overcome the defects?
a. nodes shorted to power or ground
b. nodes shorted to each other
c. inputs floating/outputs disconnected
49. What is finite state machine (FSM)?
When feedback is added to AND-OR PLA structure, then it becomes FSM
50. What is ripple carry adder?
The ripple carry adder is constructed by cascading full adder blocks in series The
carryout of one stage is fed directly to the carry-in of the next stage For an n-bit parallel
adder, it requires n full adders
25
section, the logic for generating each carry contains all of the logic used to generate the
previous carries.
A Manchester carry chain generates the intermediate carries by tapping off nodes in
the gate that calculates the most significant carry value. Not all logic families have these
internal nodes however, CMOS being a major example. Dynamic logic can support
shared logic, as can transmission gate logic. A Manchester-carry-chain section generally
won't exceed 4 bits.
55. What is meant by barrel shifter?
A barrel shifter is a digital circuit that can shift a data word by a specified
number of bits in one clock cycle. It can be implemented as a sequence
of multiplexers (mux.), and in such an implementation the output of one mux is
connected to the input of the next mux in a way that depends on the shift distance.
26
UNIT V
IMPLEMENTATION STRATERGIES AND TESTING
1. Define full custom design.
All mask layers are customized in a full-custom ASIC. It only makes sense to design
a full-custom IC if there are no libraries available. Full-custom offers the highest
performance and lowest part cost (smallest die size) with the disadvantages of increased
design time, complexity, design expense, and highest risk. Microprocessors were
exclusively full-custom, but designers are increasingly turning to semicustom ASIC
techniques in this area too. Other examples of full-custom ICs or ASICs are requirements
for high-voltage (automobile), analog/digital (communications), or sensors and actuators.
2. Define Semi custom ASIC?
It uses pre-designed logic cells which are obtained from cell library. Cell library
consists of standard cells such as AND, OR, MUX, flip flops, counters etc. Some of the
mask layers are customized.
3. Basic building blocks in FPGA.(Apr/May 2019)
Configurable logic blocks
Programmable inter connects
Memory elements
4. Give the classification of ASIC?
Full Custom ASIC.
Semi Custom ASIC.
Programmable ASIC
5. Write the difference between standard IC and Custom IC?
Standard IC: It can be directly bought from the market.
27
Custom IC:
1.It is meant for particular application.
2. Many standard IC’s combined to form Custom IC.
6. What is meant by Embedded IC?
The Gate Array is embedded and some of the IC area is dedicated to specific
functions. Embedded area contains different base cells suitable for memory cells.
7. Write the steps used for design flow?
Design entry
Logic synthesis.
System portioning.
Pre-layout simulation.
Floor planning.
Placement.
Routing.
Circuit extraction and DRC
Post-layout simulation.
8. What are the characteristics of the FPGA?
None of the mask layers are customized. A matrix of programmable interconnect
surrounds the basic logic cells. Programmable I/O cells surround the core. Design turnaround
is a few hours.
9. What is meant by design entry?
Enter the design into an ASIC design system, either using a hardware description
language (HDL) or schematic entry.
29
19. Differentiate between channeled and channel less gate array.
Channeled gate array Channel less gate array
Only the interconnect is customized Only the top few mask layers are customized
The interconnect uses predefined spaces No predefined areas are set aside for routing
between rows of base cells between cells.
Routing is done using spaces Routing is done using the area of transistors
unused
Logic density is less Logic density is higher
20. What are the different levels of design abstraction at physical design.
Architectural or functional unit
Register Transfer-level (RTL)
Logic level
Circuit level
21. What are macros.
The logic cells in a gate-array are often called macros.
22. What are programmable Interconnects ?
In a PAL, the device is programmed by changing the characteristics if the
switching element. An alternative would be to program the routing.
23. What are the types of ASICs ?
Types of ASICs are
Full custom ASICs
Semi custom ASICs
24. What are the types of programmable devices ?
Types of programmable devices are
Programmable logic structure, Programmable Interconnect, Reprogrammable Gate
Array
25. What are the features of standard celled ASICs ?
o All mask layers are customized-transistors and interconnect.
o Custom blocks can be embedded
o Manufacturing lead time is about eight weeks.
26. What are the characteristics of FPGA ?
o None of the mask layers are customized
o A method of programming the basic logic cells and the interconnect.
o The core is a array of programmable basic logic cells that can implement
combinational as well as sequential logic (flip-flops).
o A matrix of programmable interconnect surrounds the basic logic cells
o Design turnaround is a few hours.
27. What is programmable logic array ?
A programmable logic array (PLA) is a programmable device used to implement
combinational logic circuits. The PLA has a set of programmable AND planes, which
link to a programmable OR planes, which can then be conditionally complemented to
produce an output. This layout allows for a large number of logic functions to be
synthesized in the sum of products (sometimes product of sums) canonical forms.
28. What is meant by programmable logic plane ?
The programmable logic plane is programmable read only memory(PROM)
array that allows the signals present on the devices pins to be routed to an output logic
macro cell.
29. Give the application of PLA.
Design and testing of digital circuits.
30. Give the different types of ASIC.
30
1. Full custom ASICs
2. Semicustom ASICs
Standard cell based ASICs
Gate-array based ASICs
3. Programmable ASICs
Programmable Logic Device (PLD)
Field Programmable Gate Array (FPGA).
31. What is the full custom ASIC design?
In a Full custom ASIC, an engineer designs some or all of the logic cells,
circuits or layout specifically for one ASIC. It makes sense to take this approach
only if there are no suitable existing cell libraries available that can be used for the
entire design.
32. What is standard cell-based ASIC design ?(Nov/Dec 2016)
A cell-based ASIC (CBIC) uses predefined logic cells known as STANDARD
CELLS. The standard cell areas are also called flexible block in a CBIC are built of
rows of standard cells. The ASIC designer defines only the placement of standard cells
and the interconnect in a CBIC. All the mask layers of a CBIC are customized and are
unique to a particular customer.
33. What is FPGA ?
A Field Programmable Gate Array (FPGA) is a programmable logic device that
supports implementation of relatively large logic circuits. FPGA can be used to
implement a logic circuit with more than 20,000 gates whereas a CPLD can implement
circuits of upto about 20,000 equivalent gates.
34. What are the different methods of programming of PALs?
The programming of PALs in done in three ways:
1. Fusible links
2. UV-erasable EPROM
3. EEPROM (E2PROM) – Electrically Erasable Programmable ROM.
35. What is an antifuse ?
An antifuse is normally high resistance (>100MΩ). on application of
appropriate programming voltages, the antifuse is changed permanently to a low-
resistance structure(200-500Ω) .
36. Give the steps in ASIC design flow?
1. Design entry
2. Logic synthesis system partitioning
3. Prelayout simulation
4. Floor planning
5. Placement
6. Routing
7. Extraction
8. Post layout simulation
37. Differentiate full custom design and semi custom design.(Apr/May 2019).
UNIT III
1. List the types of pipelining system. Explain the construction of pipeline using latches and
registers.
2. Explain the memory organization and memory access timing.
3. Explain the method of clock generation in digital circuits.
4. Explain the design and organization of SRAM. (Apr/May 2019)
5. Explain the design and organization of DRAM.
6. Explain the memory access timing of DRAM and SRAM.
7. Discuss the techniques to reduce switching activity in a static and dynamic CMOS
circuits.
8. Explain in detail about the pipelining concept used in sequential circuits.
9. Explain the design of asynchronous sequential circuits.
10. Explain the design of synchronous sequential circuits.
11. Write a brief note on sequencing dynamic circuits.
12. Explain in detail about the principle concepts used in sequential circuits.
13. How do you achieve low power in memory circuits? Explain in detail.
14. Discuss in detail about dynamic RAM.
15. Illustrate the principles of synchronizer and arbiter.
UNIT IV
1. Design 4 bit ripple carry adder and explain.
2. Design and explain the following adders.(Apr/May 2018)
33
i. Carry skip adder
ii. Carry select adder
iii. Carry save adder
iv. Carry by pass adder
v. Conditional sum adder
3. Explain the design of parallel prefix adder.
i. Sklansky adder
ii. Kogge stone adder
iii. Brent kung adder
4. Explain the design of parallel array multiplier
i. Wallace tree
ii. Booth Multiplier
5. Explain run time power reduction management technique in detail.
6. Explain speed and area trade off I data path logic circuits in detail.
7. Explain the circuit design of Manchester carry chain adder.
8. How architectural optimization is achieved in digital system?
9. Explain design time power reduction management technique in detail.
10. Explain the mirror full adder circuit.
11. Explain the structure of booth multiplier and list its advantages.
12. Design a 3 bit barrel shifter
13. What is 4*4 carry save multiplier. Calculate its critical path delay
14. Explain the following circuits 1. Data path circuit 2. Any one adder circuit
15. Explain with neat diagram baugh-wooley multiplier
16. Explain ripple carry adder.
17. Describe about carry look-ahead adder and its carry generation and propagation.
UNIT V
1. Explain ASIC flow and types of ASIC.
2. Explain full custom and semi custom design.
3. Explain the following
i. Channeled gate array ASICs
ii. Structured gate array ASICs
iii. Programmable array logic
iv. Standard cell based ASICs
4. Explain the FPGA interconnect routing procedures of ACTEL antifuse and Metal-Metal
antifuse.
5. Explain the architecture of Xilinx 3000 FPGA. (Apr/May 2019)
6. Explain the programming methods of PLDs.
7. Explain FPGA global routing procedure.
8. Explain FPGA detailed routing procedure. (Apr/May 2019)
9. Explain the general architecture of FPGA and bring about different programmable blocks
used.
10. Discuss in detail about full custom design and semi custom design.
11. Describe about Gate-Array Based ASICs.
12. Write short note on programmable Logic devices.
13. Write short notes on standard cell design and cell libraries.
14. Write the significance of PLA/FSM in VLSI design.
34
15. Explain the programmable interconnects and I/O blocks used in FPGA.
35
V.S.B .Engineering College, Karur
Department of Electronics and Communication Engineering
The factor (λ/4πd)2 is also known as the free space loss factor.
12. Define EIRP.
EIRP (Equivalent Isotropically Radiated Power) of a transmitting system in a given direction is
defined as the transmitter power that would be needed, with an isotropic radiator, to produce the
same power density in the given direction.
EIRP=PtGt
Where Pt-transmitted power in W, where Gt-transmitting antenna gain
13. Explain path loss.
The path loss is defined as the difference (in dB) between the effective transmitted power
and the received power. Path loss may or may not include the effect of the antenna gains.
by θB as shown below,
15. Define radar cross section.
Radar Cross Section of a scattering object is defined as the ratio of the power density of
the signal scattered in the direction of the receiver to the power density of the radio wave
incident upon the scattering object & has units of squares meters.
16. What is scattering?
When a radio wave impinges on a rough surface, the reflected energy is spread out in all
directions due to scattering.
17. Name some of the outdoor propagation models?
Some of the commonly used outdoor propagation models are
i. Longely-Rice model
ii. Durkin’s model
iii. Okumura model.
18. Define indoor propagation models.
The indoor propagation models are used to characterizing radio propagation inside the
buildings. The distances covered are much smaller, and the variability of the environment is
much greater for smaller range of Transmitter and receiver separation distances. Features such
as lay-out of the building, the construction materials, and the building type strongly influence
the propagation within the building.
19. Mention some indoor propagation models?
Some of the indoor propagation models are:
i. Long –distance path loss model
ii. Ericson multiple break point model
iii. Attenuation factor model.
20. What are merits and demerits of Okumara’s model?
Merits:
Accuracy in parameter prediction.
Suitable for modern land mobile radio system. Urban, suburban areas are analyzed.
Demerits:
Rural areas are not analyzed. Analytical explanation is not enough.
21. List the advantages and disadvantages of Hata model?
Advantages:
Suitable for large cell mobile system. Cell radius on the order of 1km is taken for analysis.
Disadvantages:
Not suitable for PCS model. This model does not have any path specific correction.
22. What is the necessity of link budget?
The necessities of link budget are:
i. A link budget is the clearest and most intuitive way of computing the required
Transmitter power. It tabulates all equations that connect the Transmitter power to the
received SNR
ii. It is reliable for communications.
iii. It is used to ensure the sufficient receiver power is available.
iv. To meet the SNR requirement link budget is calculated.
23. Write the effects of fading.
1. Rapid changes in signal strength over a small travel distance or time interval.
2. Random frequency modulation due to varying Doppler shifts on different multipath signals
3. Time dispersion caused by multipath propagation delays.
24. Define coherence bandwidth. (April/May 2016)
The coherence bandwidth is related to the specific multipath structure of the channel. The
coherence bandwidth is a measure of the maximum frequency difference for which signals are still
strongly correlated in amplitude. This bandwidth is inversely proportional to the rms value of time
delay spread.
25. What is coherence time?(Nov/Dec 2018)
It is defined as the required time interval to obtain an envelope correlation of 0.9 or less.
26. Define Doppler shift.
The shift in received signal frequency due to motion is called the Doppler shift.
27. What is Doppler spread?
It is defined as the range of frequencies over which the received Doppler spectrum is essentially
non-zero.
28. What are the effects of multipath propagation?
Slow fading and fast fading
29. What is flat fading?(Nov/Dec 2017)
If the mobile radio channel has a constant gain and linear phase response over a bandwidth which
is greater than the bandwidth of the transmitted signal, then the received signal will undergo flat fading.
30. Write the conditions for flat fading.
BW of signal<<BW of channel , Bs<<Bc
Symbol period>>Delay spread, T >>ơλ
31. What is frequency selective fading?(Nov/Dec 2016)
If the channel possesses a constant gain and linear phase response over a bandwidth that is,
smaller than the bandwidth of transmitted signal, then the channel creates frequency selective fading on
the received signal.
32. Write the conditions for frequency selective fading.
BW of signal>BW of channel Bs>Bc
Symbol period< Delay spread Ts<ơλ
33. Define fast fading channel.
The channel impulse response changes rapidly within the symbol duration. This type of channel is
called fast fading channel.
34. Define slow fading channel.
The channel impulse response changes at a rate much slower than the transmitted baseband
signal. This type of channel is called slow fading channel.
35. What is meant by link budget?
A link budget is the clearest and the most intuitive way of computing the required transmit power.
36. What is the need of path loss models in link budget design?
The path loss models are used to estimate the received signal level as the function of distance it
becomes possible to predict the SNR for a mobile communication system.
37. What is ISI?
Intersymbol interference (ISI) is a form of distortion of a signal in which one symbol interferes
with subsequent symbols
38. What is meant by small scale fading? (April/May 2013)
The rapid fluctuations of the amplitudes, phases; or multipath delays of a radio signal over a short
period of time or travel distance is known as small scale fading.
39. What is meant by large scale fading? (April/May 2013)
The rapid fluctuations of the amplitudes, phases, or multipath delays of a radio signal over a long
period of time or travel distance is known as large scale fading.
40. What are the factors influencing small scale fading?
Speed of surrounding objects, Multipath propagation, Speed of the mobile, Transmission
bandwidth of the signal.
41. What is free space propagation model?
It is a model which is used to predict received signal strength, when unobstructed line of
sight path.
42. What is meant by frequency dispersion?
The received signal has a larger bandwidth than that of the transmitted signal, due to the different
Doppler shifts introduced by the components of the multipath between transmitter and receiver.
43. What are Fresnel zones?
The concentric circles on the transparent plane located between a transmitter and receiver
represent the loci of the origins of secondary wavelets which propagate to the receiver such that the total
path length increases by λ/2 for successive circles. These circles are called Fresnel zones.
44. Explain knife-edge diffraction model.
Knife edge is the simplest of diffraction models, and the diffraction loss can be readily estimated
using the classical Fresnel solution for the field behind the knife edge.
45. Find the far field distance for an antenna with maximum dimension of 2m and operating
Frequency 1GHz?(Dec 2015)
Df = 2D2/λ= 2 * 2 * 2/0.3 = 26.7 m
45. Define Snell’s law. (May 2013)
Snell's law states that the ratio of the sines of the angles of incidence and refraction is equivalent
to the ratio of phase velocities in the two media, or equivalent to the reciprocal of the ratio of the indices
of refraction:
46. Calculate the Brewster Angle for a wave impinging on ground having a permittivity of εr = 5.
(May 2016)
0.409Brewster Angle = sin -1 (0.409) = 24.14
47.What is frequency flat and frequency selective fading?
Selective fading or frequency selective fading is a radio propagation anomaly caused by partial
cancellation of a radio signal by itself — the signal arrives at the receiver by two different paths, and at
least one of the paths is changing (lengthening or shortening).
Frequency flat :A type of small scale fading where all frequency signal components experience the
same magnitude of fading; corresponds to the case where the signal bandwidth is smaller than the
channel coherence bandwidth
48.What is the major advantage of wireless communication?(April/May 2017)
Increased efficiency
Access and availability.
Flexibility.
Cost savings.
New opportunities.
Security.
Installation problems.
Coverage
49.What is shadow fading? Why it is called so?(Nov/Dec 2019)
Fading is variation of the attenuation of a signal with various variables. These variables include
time, geographical position, and radio frequency. Fading is often modeled as a random process. A fading
channel is a communication channel that experiences fading. In wireless systems, fading may either be
due to multipath propagation, referred to as multipath-induced fading, weather (particularly rain), or
shadowing from obstacles affecting the wave propagation, sometimes referred to as shadow fading.
50.Which factors does diffraction depend on at higher frequencies? (Nov/Dec 2019)
Diffraction occurs in water waves, sound waves, and light waves, but the amount of diffraction
depends on the size of the obstacle or opening in relation to the wavelength of the wave. Waves with
larger wavelengths diffract more than those with smaller wavelengths.
51. Differentiate small from large scale fading. (April/May 2019)
The large scale fading is used to describe the signal level at the receiver after traveling over
a large area (hundreds of wavelengths). Small scale fading is used to describe the signal level at the
receiver after encountering obstacles near (several wavelengths to fractions of wavelengths) the receiver.
PART B:
1. Discuss in brief about the Free-space model. And Derive the loss in the signal strength (April/ May
2018,2019)
2. What are the factors influencing small scale fading? (Nov/Dec 2016)
3. Explain the effects of multipath time delay spread and fading effects due to Doppler spread.
(Nov/Dec 2016)
4. What do you mean by path loss model? Explain in detail about log distance path loss model.
(Nov/Dec 2017)
5. Explain i) Fading and ii) Multipath propagation.
6. Derive the path loss considering a two ray model for the propagation mechanism wireless
channel. Is considering just two rays alone sufficient? Why? (April/ May 2017)
7. Write short notes on i) time-selective channels ii) frequency-selective channels(Nov/Dec 2018)
8. Differentiate narrowband and wideband channels.
9. Explain the advantages and disadvantages of two ray ground reflection model in the analysis of
path loss. (Nov/Dec 2015)
10. What is link budget? Explain with an example how it can be computed for noise limited system.
11. Write short notes on WSSUS channels.
12. Derive the impulse response model of a multipath channel and also obtain the relationship between
bandwidth and received power. (Nov/Dec 2015)
13. Explain coherence time and coherence bandwidth with expressions.
14. Explain in detail about the parameters of mobile multipath channels. (April/ May 2016)
(April/ May 2017) (May/June 2016)
15. Explain briefly on outdoor propagation model. (Nov/Dec 2014)
16. Describe in detail Two Ray Rayleigh Fading Model. (Nov/Dec 2014)
17.Explain the time invariant two path model of a wireless propagation channel. (Nov/Dec 2016)
18. In free space propagation describe how the signals are affected by reflection, diffraction and
scattering. (April/ May 2016)
19.Describe small scale fading and derive the expressions for parameters of mobile multipath
channels.(Nov/Dec 2018)
20.Discuss the flat fading channel characteristics with relevant diagrams. (April/ May 2019)
21. Describe the classification of small scale fading with respect to Doppler spread. (April/ May 2019)
22.Compare and contrast wired and wireless communication.(Nov/Dec 2019)
PART C:
1. Explain Okumura-Hata empirical and Nakagamimodel in detail.
2. (i) Explain on path loss estimation techniques using path loss models.
(ii)Describe on Ricean Distribution.
3. In free space propagation describe how the signals are affected by reflection, diffraction and
scattering. (May/June 2016)
4. Consider a transmitter which radiates a sinusoidal carrier frequency of 1850MHz. Forvehicle moving
60 mph, compute the received carrier frequency if the mobile is moving directly toward the
transmitter.
5. Determine the proper spatial sampling interval required to make small scale propagation
measurements which assume that consecutive samples are highly correlated in time. How many
samples will be required over 10m travel distance if fc = 1900MHz and v=50m/s. how long would it
take to make these measurements, assuming they could be made in real time from a moving vehicle.
What is the Doppler spread BD for the channel.
6. Analyze and compare the error performance in fading channels with and without diversity reception
techniques. (Nov/Dec 2017)
7. Determine the error probability for different fading channels with diversity reception.
8. Examine the effectiveness of flat fading and frequency selective fading.(Nov/Dec 2019)
UNIT II CELLULAR ARCHITECTURE
1. What is meant by frequency reuse?(April/May 2018)(Nov/Dec 2017)
If an area is served by a single Base Station, then the available spectrum can be divided into N
frequency channels that can serve N users simultaneously. If more than N users are to be served,
multiple BSs are required, and frequency channels have to be reused in different locations. Since
spectrum is limited, the same spectrum has to be used for different wireless connections in different
locations. This method of reusing the frequency is called as frequency reuse.
2. What are the trends in cellular radio systems?
The trends in personal cellular radio systems are:
i. PCS – Personal Communication Services
ii. PCN – Personal Communication Networks
3. What do you mean by forward and reverse channel?
Forward channel is a radio channel used for transmission of information from base station to
mobile. Reverse channel is a radio channel used for transmission from mobile to base station.
4. What is the function of control channel? What are the types?
The function of control channel is to transmit call setup, call request, call initiation and Control.
There are two types of controlchannels,
i. Forward control channel
ii. Reverse control channel
Q=D/R =
From the above equation, small of `Q' means small value of cluster size `N' and increase in cellular
capacity.
16. Define FDMA, TDMA and CDMA.(April/May 2018)
FDMA - the total bandwidth is divided into non-overlapping frequency sub bands. TDMA –
divides the radio spectrum into time slots and in each slot only one user is allowed to either
transmit or receive.
CDMA – many users share the same frequency same tome with different coding.
17. Define Grade of service.(Nov/Dec 2016)
Grade of service is defined as the measure of the ability of a user to access a trunked system
during the busiest hour.
18. What is blocked call clear system (BCC)?
In a system, a user is blocked without access by a system when no channels are available in
the system. The call blocked by the system is cleared and the user should try again .This is called
BCC system.
19. What is blocked call delay system?
If a channel is not available immediately, the call request may be delayed until a channel becomes
available. This is called as blocked call delay system.
20. Define cell splitting.
Cell splitting is the process of subdividing congested cells into smaller cells each with its own
base stations and a corresponding reduction in antenna height and transmitter power. It increases the
capacity of cellular system.
21. What is sectoring?
Sectoring is a technique for decreasing co-channel interference and thus increasing the system
performance by using directional antennas.
22. What are the features of TDMA?
Features of TDMA are:
i. TDMA shares a single carrier frequency with several users, where each user makes use of non
overlapping time slots.
ii. Data transmission occurs in bursts.
iii. Handoff process is much simpler
iv. Duplexers are not required, since transmission and reception occurs at different time slots.
23. What are the features of FDMA?(Nov/Dec 2019)
Features of FDMA are:
i. FDMA channel carries only one phone circuit at a time
ii. The bandwidth of FDMA channels is relatively narrow as each channel
supports only one circuit per carrier.
24. What are the different types of multiple access schemes? (Dec 2013) (May 2016).
FDMA-Frequency division multiple access-different frequencies are assigned to different users
TDMA-Time division multiple access-different time slots are assigned to different users. CDMA-
Code division multiple access-each user is assigned a different code.
25. What are the disadvantages of FDMA?
1. Sensitivity to fading
2. Sensitivity to random frequency modulation
3. Inter modulation
26. What are the advantages of FDMA?
The transmitter and receiver require much less digital signal processing, Synchronization is simple.
27. Define SAMA.
Spread Aloha Multiple Access is a combination of CDMA and TDMA. The CDMA better suits
for connection oriented services only and not for connection less burst data traffic because it requires to
program both sender and receiver to access different users with different codes.
28. Define CDMA.(April/May 2018)
Code Division Multiple Access systems use codes with certain characteristics to separate different
users. To enable access to the shared medium without interference. The users use the same frequency and
time to transmit data. The main problem is to find good codes and to separate this signal from noise. The
good code can be found the following 2 characteristics 1.Orthogonal. 2. Autocorrelation.
29. What is SDMA?
Space Division Multiple Access (SDMA) is used for allocating separated spaces to users in
wireless networks. The basis for the SDMA algorithm is formed by cells and sectorized antennas which
constitute the infrastructure implementing space division multiplexing (SDM).
30. What is FDD?
In FDMA, the base station and the mobile station establish a duplex channel. The two directions,
mobile station to base station and vice versa are separated using different frequencies. This Scheme is
called Frequency Division Duplex (FDD)
31. What limits the number of user in TDM and FDM compared to CDM?
The code space is huge compared to the frequency space and time space. Because of the limited
time space and frequency space, the number of user in TDM and FDM are limited.
32. How does near and far effect influence CDMA? What are counter measurements?
The near and far effect is a server problem of wireless networks using CDM. All signals should
arrive at the receiver with more or less the same strength. Precise power control is needed to receive all
senders with the same strength at a receiver.
33. Define FCA and DCA.
Allocating a fixed frequencies for a channel is called as Fixed channel Allocation (FCA). In
Dynamic Channel Allocation (DCA) scheme frequencies can only be borrowed, but it is also possible to
freely allocate frequencies to cells. With dynamic assignment of frequencies to cells, the danger of the
interference with cells with same frequency exists. Thus the borrowed frequencies in the surroundings
cells can be blocked.
34. What is guard space?
Guard spaces are needed to avoid frequency band overlapping is also called channel interference.
35. When handoff occurs?
Hand-off occurs when a received signal from its serving cell becomes weak and another cell site
can provide a stronger signal to the mobile subscriber. If the new cell-site has some free voice channels
then its assigns one of them to the handed-off call.
36. Differentiate soft and hard handoff. (May 2016).
Hard handoff mode is characterized by a mobile having a radio link with only AP at any time.
Thus, the old connection is terminated before a new connection is activated. This mode of operation is
referred to as break before make.
In Soft handoff, the mobile can simultaneously communicate with more than one AP during the
handoff. This new connection is made before breaking the old connection, and is referred to as make
before break.
37. What is the function of Medium Access Control Layer?
The functions of Medium Access Control Layer are responsible for stablishes, maintains, and
releases channels for higher layers by activating and deactivating physical channels.
38. What are the 2 sub layers in DLC?
Logical Link Control (LLC), Media Access Control (MAC)
39. Define traffic multi frame and control multi frame?
The periodic pattern of 26 slots occurs in all TDMA frames with a TCH. The combination of
these frames is called traffic multi frame TDMA frames containing data for the other logical channels are
combined o a control multi frame.
1. Compare and Contrast the TDMA, FDMA and CDMA techniques. (May 2016) (June 2013).
2. Summarize the features of various multiple access techniques used in wireless mobile
communication. State the advantages and disadvantages of each technique. (May/June 2016)
3. Explain the Channel Assignment and handoff Strategies in detail. (April/May 2018)
(April/May 2017)
4. Explain in detail how to improve coverage and channel capacity in cellular system.
(May/June 2016)
5. Describe the Operations of Cellular systems and Explain it steps with a neat sketch(June 2013)
6. Explain in detail about multiple accesses with collision avoidance scheme. Also explain the
advantages of the same. (Nov/Dec 2013)
7. Derive the expressions for cellular CDMA schemes for both noise limited and interference limited
scenarios. (April/May 2017, 2019)
8. Explain about co-channel interference and adjacent channel interference. Describe the technique to
avoid interference. (Nov/Dec 2016)
9. Explain the concept of cell planning with relevant diagrams and expressions.
10. Identify the channel capacity of TDMA in a cell system. (Nov/Dec 2017)
11. Explain the principle of cellular networks and various types of Handoff techniques.
(Nov/Dec 2013) (Nov/Dec 2014)
12. Write a short notes on i) trunking ii) grade of service.(Nov/Dec 2017,2019)
13. Illustrate Cellular Frequency Reuse with a neat sketch.
14. Discuss the technical challenges faced by the wireless communication. (May/June 2014)
15. How is hand-off in a cellular system implemented. Explain the different types of hands-
offs(Nov/Dec 2018,2019)
16. How can capacity of a cellular communication system be improved? Explain any two capacity
expansion techniques.(Nov/Dec 2018)
17. Discuss the impact of interference in a cellular system and system capacity.(Nov/Dec 2018)
18. Write a short notes on i) Cell splitting.(April/May 2019)
PART C:
1. A spectrum of 33MHZ is allocated to a wireless FDD cellular system which uses two 25KHZ simplex
channels to provide full duplex voice and control channels, compute the number of channels available
per cell if a system uses ( a)four-cell reuse (b)seven-cell reuse ,and (c)12-cell reuse. If 1MHZ of the
allocated spectrum is dedicated to control channels, determine an equitable distribution of control
channels and voice channels in each cell for each of three systems.
2. If a signal to interference ratio of 15db is required for satisfactory forward channel performance of the
cellular system, what is the frequency reuse factor and cluster size that should be used for maximum
capacity if the pathloss exponent is (a) n=4 (b) n=3? Assume that there are six co-channel cells in the
first tier and all of them are at the same distance from the mobile. Use suitable approximations.
3. Consider global system for mobile which is a TDMA/FDD system that uses 25MHz for the forward
link, which is broken into radio channels of 200MHz. If 8 speech signals are supported on a single
radio channel and if no guard band is assumed, find the number of simultaneous users that can be
accommodated in GSM.
4. If GSM uses a frame structure where each frame consists of 8 time slots, and each time slot contains
156.25 bits, and data is transmitted at 270.833 Kbps, in the channel, find (1) the time duration of a bit
(2) the time duration of a slot (3) the time duration of a frame and (4) how long must a user occupying
a single time slot wait between two successive transmissions.
5. Explain the various methods that increase the channel capacity and coverage. (April/May 2016)
6.Explain any two ways of improving the coverage and capacity in cellular systems.(Nov/Dec 2019)
UNIT III DIGITAL SIGNALLING FOR FADING CHANNELS
3. What is QPSK?
The Quadrature Phase Shift Keying (QPSK) is a 4-ary PSK signal. The phase of the carrier in
the QPSK takes 1 of 4 equally spaced shifts.
Two successive bits in the data sequence are grouped together.
1 symbol = 2 bits
This reduces bit rate and bandwidth of the channel.
Coherent QPSK = 2 x coherent BPSK system
The phase of the carrier takes on one of four equally spaced values such as π/4, 3π/4, 5π/4 and 7π/4.
4. Define offset QPSK and π/4 differential QPSK.
In offset QPSK the amplitude of data pulses are kept constant. The time alignment of the even
and odd bit streams are offset by one bit period in offset QPSK. In π/4 QPSK, signaling points of the
modulated signal are selected from two QPSK constellations which are shifted by π/4 with respect to
each other. It is differentially encoded and detected so called π/4 differential QPSK.
5. What is meant by MSK?(Nov/Dec- 2019)
A continuous phase FSK signal with a deviation ratio of one half is referred to as MSK. It is a
spectrally efficient modulation scheme.
6. List the salient features of MSK scheme.
Salient features of MSK are:
i. It has constant envelope, smoother waveforms than QPSK.
ii. Relatively narrow bandwidth.
iii. Coherent detection suitable for satellitecommunications.
iv. Side lobes are zero outside the frequency band, so it has resistance
to co- channel interference.
7. Why GMSK is preferred for multiuser, cellular communication?(Nov/Dec 2018)
It is a simple binary modulation scheme.
Premodulation is done by Gaussian pulse shaping filter, so side lobe levels are much reduced. GMSK
has excellent power efficiency and spectral efficiency than FSK. For the above reasons GMSK is
preferred for multiuser, cellular communication.
8. How can we improve the performance of digital modulation under fading channels?
By the using of diversity technique, error control coding and equalization techniques
performance of the digital modulation under fading channels are improved.
9. Write the advantages of MSK over QPSK.(April/May 2017)
Advantages of MSK over QPSK:
i. In QPSK the phase changes by 90degree or 180 degree .This creates abrupt amplitude
variations in the waveform, Therefore bandwidth requirement of QPSK is more filters of other
methods overcome these problems , but they have other side effects.
ii. MSK overcomes those problems. In MSK the output waveform is continuous in phase hence
there are no abrupt changes in amplitude.
10. Define M-ary transmission system?
In digital modulations instead of transmitting one bit at a time, two or more bits are
transmitted simultaneously. This is called M-arytransmission.
11. What is quadrature modulation?
Sometimes two or more quadrature carriers are used for modulation. It is called quadrature
modulation.
12. What is QAM?
At high bit rates a combination of ASK and PSK is employed in order to minimize the errors
in the received data. This method is known as “Quadrature Amplitude Modulation”.
13. Define QPSK
QPSK is defined as the multilevel modulation scheme in which four phase shifts are used for
representing four different symbols.
14. What is linear modulation?
In linear modulation technique the amplitude of the transmitted signal varies linearly with the
modulating digital signal. In general, linear modulation does not have a constant envelope.
PART B
1. Explain QPSK transmitter and receiver with signal space diagram and give an expression for spectral
efficiency. (Nov/Dec 2013)( Nov/Dec 2014)
2. Explain π/4 Differential QPSK & OQPSK transmitter and receiver with signal space diagram and
give an expression for spectral efficiency. (May/June 2013) (April/May 2016).
3. Derive the bit error rate for binary phase shift keying modulation for frequency flat fading channels.
(April/May 2018)
4. Explain BFSK transmitter and receiver with signal space diagram and give an expression for spectral
efficiency.( Nov/Dec 2014)
5. Explain MSK transmitter and receiver with signal space diagram and give an expression for spectral
efficiency. (June 2013), (Nov/Dec 2015)
6. What is offset QPSK? What is the advantage? Describe the offset-QPSK scheme.
7. Discuss about the performance of digital modulation in fading channels. (Nov/Dec 2013)
8. Explain the Nyquist criterion for ISI cancellation. (Nov/Dec 2013)
9. Importance of MSK in wireless communication system(Nov/Dec 2018)
10. Explain in detail about OFDM modulation technique with necessary diagrams.List out its advantages
and disadvantages(Nov/Dec 2018,2019) (April/May 2018)
11. Prove the OFDM system converts the delay spread channel into a set of parallel fading channels,
using the concept of cyclic prefix. (April/May 2018)
12. (i) Describe with a block diagram π/4 Quadrature phase shift keying and its advantages.(April/May
2019)(Nov/Dec 2019)
(ii)What is MSK? Explain its power spectral density. (Dec 2014)
13. Describe with neat diagram the modulation technique of QPSK. (Nov/Dec 2017)
14. List the advantages and applications of BFSK. (Nov/Dec 2017)
15. Explain the principle of MSK modulation and derive the expression for power spectral density.
(Nov/Dec 2017)
16. Explain the principal of OFDM by comparing it with FDMA with a neat sketch. (April/May 2019)
17. Discuss any four reasons for the physical cause of error floors in delay and frequency dispersive
fading channels. (April/May 2019)
PART C
1. With neat diagrams explain the modulation and demodulation of π/4 DQPSK modulation technique.
(April/May 2018)
2. A 880 MHz carrier signal is frequency modulated using a100 kHz sinusoidal modulating waveform.
The peak deviation of the FM signal is 500 kHz. If this FM signal is received by a super heterodyne
receiver having an IF frequency of 5MHz, determine the IF bandwidth necessary to pass the signal.
3. Demonstrate the generation, deduction and bit error probability of QPSK scheme.
4. Examine the principle of MSK modulation and derive the expression for power spectral density.
5. Explain GMSK transmitter and receiver with signal space diagram and give an expression for
spectral efficiency. (Nov/Dec 2015) (April/May 2016)
UNIT IV MULTIPATH MITIGATION TECHNIQUES
Macrodiversity Microdiversity
In antenna (or micro) diversity the signal
from antennas mounted at separate locations are In site (or macro) diversity the receiving
combined antennas are located at different receiver sites
PART B
1. Explain the classification of equalizers.
2. Analyze various diversity techniques used in wireless communication. (Nov/Dec 2017)
3. Briefly explain about linear and non-linear equalizers. (Dec 2013)(May 2016).
4. Discuss about DFE.
5. Explain the principles of RAKE receiver in detail. (April/May 2018) (April/May 2017)(Nov/Dec
2018,2019) , (April/May 2019).
6. Explain about MLSE equalizer.(Dec 2013)
7. Explain in detail various factors to determine the algorithm for adaptive equalizer. Also derive the
least Mean Square algorithm for adaptive equalizer. (Nov/Dec 2016,2019)
8. Discuss in detail about the different micro diversity concepts. (May 2016)
9. Explain about theoretical model for polarization diversity.
10. Derive an expression for performance improvement due to maximal ratio combining. (Nov/Dec 2017)
11. Describe in detail about i) Linear equalizers ii) Non linear equalizers (Nov/Dec 2017)
12. Discuss the performance of a RAKE receiver with a neat diagram.(Dec 2013).
13. Explain any two diversity techniques to combat small scale fading(June 2013)(Nov/Dec 2018)
14. With relevant diagrams explain Rake receiver. Also discuss how time diversity is achieved in a
CDMA technique in Rake receiver. (Nov/Dec 2016)
15. Describe any two adaptation algorithms for Mean square error Equalizers(June 2013)
16. (i) With a neat block diagram explain the principle of Macrodiversity
(ii)Explain the operation of an adaptive equalizer at the receiver side (Dec 2014)(April/May 2019)
17. (i) Explain with block diagram Maximal ratio combiner
(ii) Describe on Polarization and space diversity. (Dec 2014)
18. Derive the mean square error for a generic adaptive equaliser (Dec 2015).
19. What is zero forcing equalizer algorithm. Explain.(Nov/Dec 2018)
20. Write a brief note on categories of space diversity reception methods.(April/May 2019)
21. Explain selection combining technique in detail. (Nov/Dec 2019)
PART C
1. Consider uncoded spatial multiplexing over a MIMO channel with MR>=MT. Show that ML, MMSE
and ZF receivers perform equally well if the channel is orthogonal. What is the per stream SNR?
2. Describe the role played by equalization and diversity as multipath mitigation techniques. Compare
and contrast these two techniques. (April/May 2017)
3. Discuss in detail the capacity of fading and non fading channels. (April/May 2017)
4. With valid statements, analytically prove that the adaptive equalizers exhibit superior performance
over the conventional equalizers. (Nov/Dec 2017)
5. Consider the design of the US digital cellular equalizer, where f=900MHz and the mobile velocity
v=80Km/hr, determine the maximum Doppler shift, the coherence time of the channel and the
maximum number of symbols that could be transmitted without updating the equalizer assuming that
the symbol rate is 24.3 k symbols/sec.
6. Assume four branch diversity is used, where each branch receives an independent Rayleigh fading
signal. If the average SNR is 20dB, determine the probability that the SNR will drop below 10dB.
Compare this with the case of single receiver without diversity.
7. Describe the role played by equalization and diversity as multipath mitigation techniques. Compare
and contrast these two techniques.
8. Draw the chart showing the classification of equalizers.(Nov/Dec 2019)
UNIT V MULTIPLE ANTENNA TECHNIQUES
1. What is Beamforming?
The multiple antennas at the transmitter and receiver can be used to obtain array and diversity gain
instead of capacity gain. In this setting the same symbol weighted by a complex scale factor is sent over
each transmit antenna, so that the input covariance matrix has u it rank. This scheme is also referred to as
MIMO beamforming.
2. What are the advantages of Beamforming?
Beamforming provides diversity and array gain via coherent combining of the multiple signal paths.
UNIT 1
INTRODUCTION TO MANAGEMENT AND ORGANIZATIONS
1. Define Management. (MAY 2011, MAY 2016, MAY 2017, NOV 2017)
Koontz and Weihrich defines Management as “the process of
designing and maintaining an environment in which individuals, working together
in groups, accomplish their aims effectively and efficiently”.
2. What are the various levels of management?
The various levels existing in an average firm / company are: Top level
management, Middle level management, and Lower level management.
3. What are the various skills required of a manager?
Technical skill – Knowledge of and proficiency in working with tools and technology Human
skill – Ability to work with people Conceptual skill – Ability to recognize important element in
a situation and understand relationship among elements, and Design skill – Ability to solve
problems which will benefit the company
4. What are the roles played by managers? (MAY 2011, MAY 2015)
Interpersonal roles: Figurehead, Leader, Liaison.
Informational roles: Recipient, Disseminator, Spokesman.
Decision roles: Entrepreneur, Disturbance handler, Resource allocator, Negotiator
13. List the factors that are involved in either producing (or) preventing knock.
Fayol classified business activities into six groups: Technical, Commercial,
Financial, Accounting, Security, and Administrative (Managerial).
14. What is a ‘scalar chain’?
A scalar chain is a hierarchical chain of authority which extends from the
top to the bottom of an organization and defines the communication path. However,
horizontal communication (gangplank) is also encouraged as long as the managers in the
chain are kept informed.
15. What is ‘Esprit-de-corps’?
It means ‘Unity is strength’. In an organization, there should be harmony and unity
amongst the employees.
16. What is meant by ‘Business environment’?
An organization, being a subsystem of broader societal system, has to work within the
framework provided by the society and its various constituents. These constituents are
combined to constitute environment for a given organization. Thus environment
MG8591 Principles of Management Academic Year2021-2022
includes all the conditions, circumstances, and influences surrounding and affecting
the total organization or any of its part.
21. What are the differences between administration and management?(MAY 2013)
1 It is higher level function It is lower level function
PART B
1. Discuss the role of manager and important functions of management. Management:
Science and Art – Discuss.(MAY 2017, MAY 2016, MAY 2015, MAY 2014)
5.Explain the types of Business organization. (Or Elucidate any four types of
organization). (MAY 2017, MAY 2015, MAY 2014)
PART C
1. Explain the trends and challenges of management in global scenario. Brief about the
functions of MNC
MG8591 Principles of Management Academic Year2021-2022
UNIT 2
PLANNING
1. What is planning?
Planning involves selecting missions and objectives and the actions to achieve
them. It requires decision making that is, choosing future courses of action from among
alternatives.
7. What is an Objective?
Both goal and objective can be defined as statements that reflect the end towards
which the organization is aiming to achieve. However, there are significant differences
between the two. A goal is an abstract and general umbrella statement, under which
specific objectives can be clustered. Objectives are statements that describe—in precise,
measurable, and obtainable terms which reflect the desired organization’s outcomes.
14. What are the steps in decision making? What are the types of decisions?
(MAY 2016)
Premising; identifying alternatives; Evaluating the alternatives in terms of the goal
sought; and Choosing the alternative. There are two types of decisions they are
Programmed decisions and non-programmed decisions.
15. What are the various decision-making conditions?
Decision making under certainty; Decision making under risk; and Decision
making under uncertainty.
16. Distinguish between ‘risk’ and ‘uncertainty’ in decision making.
‘Risk’ condition exists when the probabilities of occurrence of various outcomes of the
decision are known.
‘Uncertainty’ condition exists when these probabilities are unknown.
19.What is KRA?
KRA-Key Result Areas are identified on basis of organizational objectives and
planning premises where organizational health can be measured.
23. What are the steps in policy formulation process and type of policies?
Definition of policy, Creation of policy alternative, evaluation of policy, choice
of policy, communication of policy, implementation and review.Types of policies:
Formulated policies, appealed policy, imposed policy, written policy and implied
policy.
25. What are the planning tools and techniques available in business management?
(MAY 2017)
It is classified under the following headings
• Production planning tools such as machine chart, load chart, gantt chart,
• Project planning tools such as PERT/CPM, etc.
• Tools for allocation resources : Budgeting, etc.
• Techniques for assessing the environment: Forecasting, benchmarking, etc.
MG8591 Principles of Management Academic Year2021-2022
PART B
1. Explain the general planning process adopted by business organizations. Explain the
planning premises with types.
2. Explain in detail the various types of planning. (NOV 2017)
3. What are the steps involved in strategic planning? (MAY 2014)
4. Discuss the various types of decision. Explain the process followed while taking a
decision in normal situation. Is decision making a rational process? Discuss. (NOV
2017, MAY 2017, MAY 2016, MAY 2015, MAY 2014, MAY 2013).
5. What is MBO? State and explain the common steps involved in designing a
scheme of MBO. (MAY 2017, MAY 2015, MAY 2013, MAY 2012)
PART C
1. Explain in detail about the TOWS matrix and SWOT analysis. (May 2015)
2. What are the objectives of planning? Illustrate how you will set objectives for
manufacturing Organization.(MAY 2016)
UNIT 3
ORGANISING
1. Define the term ‘Organization’.
"Organizations are collections of people that have been established for the pursuit of
specific objectives on a more or less continuous basis."
2. What is Organizing?(MAY 2011, MAY 2013, MAY 2016)
Organizing involves establishing a structure of roles for people to fill in an
organization and ensuring that all the tasks necessary to accomplish goals are assigned to
people who can do those best.
17. What are the various sources of external recruitment? (MAY 2012)
1.Re-employing former employees; 2. Friends and relatives of present employees;
3.Applicants at the gate; 4. Colleges and technical institutions; 5. Employment
exchanges; 6. Advertising the vacancy; 7. Labor unions; and 8. Competitors’
organizations.
17. What are the various steps in the selection process?
Designing application blank; Receiving applications; Screening of applications;
Conducting selection tests; Conducting formal interview; Examining the previous work
MG8591 Principles of Management Academic Year2021-2022
history; Checking references; Provisional selection; Physical/medical examination; Final
selection; Employment.
19. What is application blank?
It is a good means of quickly collecting verifiable historical data from the candidate. It
is highly structured in which the questions are standardized and determined in advance.
Besides, it tests the applicant’s ability to write, organize his thoughts and present facts.
23. What do you understand by organizational chart? What are the types of
organization chart? (NOV 2017)
Organizational chart is graphical representation of organizational structure. The
relationship existing between the members of an organization can be understood by an
organizational chart. Types are :Vertical chart, Horizontal chart, Circular chart.
25. What are the differences between formal and informal organization?
Point of view formal organization informal organization
3. List the difference between formal and informal organization. (NOV 2015, MAY 2015)
PART C
1. State and explain the basic steps involved in a typical selection procedure. Discuss
in detail about the performance appraisal. (MAY 2015, MAY 2012, NOV 2012)
2. Explain about the human resource planning. Distinguish between training and
development. Explain the various methods of training. (NOV 2017, MAY 2017)
MG8591 Principles of Management Academic Year2021-2022
UNIT 4
DIRECTING
1. What are the various approaches to (theories of) leadership?
Traits approach; Behavioral approach; Managerial Grid; Fiedler’s contingency
approach; Path-Goal approach, etc.
Job Enlargement : Job enlargement changes the jobs to include more and / or different
tasks. Job enlargement should add interest to the work but may or may not give
employees more responsibility.
Job Rotation : Job rotation moves employees from one task to another. It distributes the
group tasks among a number of employees.
Job Enrichment : Job enrichment allows employees to assume more responsibility ,
accountability, and independence when learning new tasks or to allow for greater
participation and new opportunities .
23. Who is a leader? What are the qualities of a leader? (MAY 2012)
Leader is someone who can influence others and who has managerial authority.
Honesty, confidence, patience, focus, dedication, consistency, motivate others, effective
communication, individuality are the qualities of an effective leader.
PART B
1. Explain the different characteristics, functions and traits of leader. What are the
essential qualities of a good leader? (MAY 2015, MAY 2016)
3. Explain about the theories of Motivation. Compare and discuss the Maslow and
Herzberg’s theory of Motivation. (NOV 2017, MAY 2017, MAY 2015, MAY 2014)
4. What are the various barriers in communication? How will you overcome these
barriers? (NOV 2017, MAY 2017, MAY 2013, MAY 2012, NOV 2012)
PART C
1. Job performance of Individual is significantly influenced by the employee’s
attitude” – Discuss. (MAY 2017)
MG8591 Principles of Management Academic Year2021-2022
UNIT 5
CONTROLLING
1. What are the steps in controlling process?
Establishing standards; Measuring performance; Comparing performance with
standard;Taking corrective action.
2. What are the three types of control with respect to time? (MAY 2013)
[a]Feed forward control, [b]Concurrent control, and [c] Feedback control.
1. It measures only the output of the It measures the input of the process
process
4. What is a Budget?
Budget is a financial and/or quantitative statement prepared prior to a definite period
of time, of the policy to be pursued during that period, for the purpose of achieving a given
objective.
PART B
1. Define controlling. Explain the steps involved in the process of controlling. (MAY
2017, MAY 2011)
2. Explain the steps in the implementation of budgetary control and non-budgetary control
techniques (or Explain the various controlling technique). Explain the different types of
budgets.(NOV 2017, MAY 2015, MAY 2013, MAY 2012)
3. Distinguish direct control from preventive control. Explain the preventive control
mechanism towards achieving a unified global management theory.(MAY 2016, MAY 2015)
MG8591 Principles of Management Academic Year2021-2022
4. Define productivity and identify the problems involved in measuring the productivity of
knowledge workers. What tools and techniques do you suggest to improve productivity in
Indian Organizations (IT Sector)? (MAY 2016, MAY 2012, MAY 2011)
5. Explain the term operations management and major activities associated with operations
management. (NOV 2011)
.PART C
Modern Manufacturing Company has been using a budgetary control system for the last three
years. When asked to explain the system, Mr.John, the Managing Director of the company,
observed: “We’re pretty flexible in our budgetary system. Every manager is given a total
amount that he or she can spend for the next year. We don’t care how it is used as long as the
total isn’t exceeded and organizational objectives are achieved”.
2. What are the secondary constants of a line? Why the line parameters are
called distributed elements?
The secondary constants of a line are: Characteristic Impedance Propagation Constant.
Since the line constants R, L, C, G are distributed through the entire length of the line, they are
called as distributed elements. They are also called as primary constants.
10. How to avoid the frequency distortion that occurs in the line?
In order to reduce frequency distortion occurring in the line, a) The attenuation constant
α should be made independent of frequency. b) By using equalizers at the line terminals which
minimize the frequency distortion. Equalizers are networks whose frequency and phase
characteristics are adjusted to be inverse to those of the lines, which result in a uniform
frequency response over the desired frequency band, and hence the attenuation is equal for all
the frequencies.
15. How the telephone line can be made a distortion less line?
For the telephone cable to be distortion less line, the inductance value should be
increased by placing lumped inductors along the line.
26. What are the conditions for a perfect line? What is a smooth line?
For a perfect line, the resistance and the leakage conductance value were neglected. The
conditions for a perfect line are R=G=0. A smooth line is one in which the load is terminated by
its characteristic impedance and no reflections occur in such a line. It is also called as flat line.
16 MARKS:
1. Discuss in detail about inductance loading of telephone cables and derive the attenuation
constant, phase constant and velocity of signal transmission for the uniformly loaded cable.
2. Explain in detail about the reflection on a line not terminated in its characteristics impedance.
3. A transmission line operating at 500 MHz has Z₀=80Ω, α= 0.04 Np/m, β=1.5 rad/m. Find the
line parameter series resistance (R Ω/m), series inductance (L H/m), shunt conductance (G
mho/m) and capacitance between conductors (C F/m).
4. A distortion less transmission line has attenuation constant α=1.15×10ˉᶟ Np/m, and
capacitance of 0.01 n F/m. the characteristic resistance L/C=50Ω find the resistance
inductance and conductance per more of the line.
5. Derive the general transmission line equation for the voltage and current at any point on a line.
6. write a brief note on frequency and phase distortion.
7. The characteristics impedance of a 805m-long transmission line is 94 -23.2⁰Ω the attenuation
constant is 74.5×10ˉ⁶ Np/m. and the phase shift constant is 174×10ˉ⁶ rad/m at 5KHz calculate
the line parameters R,L,G and C per meter and the phase velocity on the line.
8. Derive expression for the attenuation and phase constant of transmission line in constant
R,L,G and C. The constants of a transmission line are R= 6ohms/km, L=2.2m H/km,
C=0.005×10ˉ⁶ and G=0.25×10ˉ⁶ mho/km. Determine the characteristics impedance and
propagation constant at 1000 Hz.
9. Derive the expression for the input impedance of a transmission line Hence obtain the input
impedance for a loss less line.
10.write a short note on reflection factor and reflection loss.
11.Derive the expression for the input impedance of a loss less line.
12.Draw the L-type equivalent circuit model of a two-conductor transmission line and derive the
transmission line equations.
13.Discuss the reflection coefficient of different transmission lines.
14.A transmission line operating at 10⁶ rad/s has α= 8 d B/m, β= 1 rad/m. and z₀= 60+ j40ohms,
and is 2meter long. The line is connected to a source of 10 v, Zg=40ohms and terminated by a
load of 20 + j50ohms. Determine the current at the middle of the line.
15. A low loss transmission line of 100 ohms characteristic impedance is connected to a load of
200ohm. Calculate the voltage reflection coefficient and the standing wave ratio.
16. Discuss the theory of open and short circuited lines with voltage and current distribution
diagram and also get the input impedance expression.
17. A transmission line has the following per unit length parameters : L = 0.1μ H, R =5 ohms,
C = 300 pF and G = 0.01 mho. Calculate the propagation constant.
UNIT II
HIGH FREQUENCY T RANSMISSION LINES
2 MARKS:
1. State the assumptions for the analysis of the performance of the radio frequency line.
a. Due to the skin effect, the currents are assumed to flow on the surface of the
conductor. The internal inductance is zero.
b. 2.The resistance R increases with square root of f while inductance L
increases with f . Hence ωL>>R.
c. The leakage conductance G is zero.
2. State the expressions for inductance L of a open wire line and coaxial line.
a. For open wire line ,
b. L=9.21*10-7(µ/µr +4ln d/a)=10-7(µr +9.21log d/a) H/m
c. For coaxial line,L = 4.60*10-7[log b/a]H/m
3. State the expressions for the capacitance of a open wire line For open wire line.
C=(12.07)/(ln d/a)µµf/m
5. What is the nature and value of Z0 for the dissipation less line?
For the dissipation less line, the Z0 is purley resistive and given by, Z0=R0 = ( L/c) ½
10. State the relation between standing wave ratio and reflection coefficient.
Ans: S = 1+ΙKΙ/1- ΙKΙ
11. What are standing waves?
If the transmission is not terminated in its characteristic impedance ,then there will be
two waves traveling along the line which gives rise to standing waves having fixed
maxima and fixed minima.
12. What is called standing wave ratio?
The ratio of the maximum to minimum magnitudes of current or voltage on a line having
standing wave is called the standing-wave ratio S.
13. State the relation between standing were ratio S and reflection co-efficient k.
The relation between standing wave ratio S and ref lection co-efficient k is,
i. S =1+ΙKΙ/1- ΙKΙ,k = S-1/S+1
14. How will you make standing wave measurements on coaxial lines?
For coaxial lines it is necessary to use a length of line in which a longitudinal slot,
one half wavelength or more long has been cut. A wire probe is inserted into the
air dielectric of the line as a pickup device, a vacuum tube voltmeter or other
detector being connected between probe and sheath as an indicator. If the meter
provides linear indications, S is readily determined. If the indicator is non linear,
corrections must be applied to the readings obtained.
16. Give the maximum and minimum input impedance of the dissipationless line.
a. Maximum input impedance
b. Minimum input impedance
17. Give the input impedance of open and short circuited lines.
The input impedance of open and short circuited lines are given.
18. Why the point of voltage minimum is measured rather than voltage maximum?
The point of a voltage minimum is measured rather than a voltage maximum
because it is usually possible to determine the exact point of minimum voltage
with greater accuracy.
20. Give the input impendence of eighth wave line terminated in a pure resistance
Rr. The input impendence of eighth wave line terminated in a pure resistance Rr. Is given
by Zs = (ZR+jRo/Ro+jZR). From the above equation it is seen that ΙZsΙ = Ro.
27. Give reasons for preferring a short- circuited stub when compared to an open
circuited stub.
A short circuited stub is preferred to an open circuited stub because of greater
ease in constructions and because of the inability to maintain high enough
insulation resistance at the open .circuit point to ensure that the stub is really open
circuited. A shorted stub also has a lower loss of energy due to radiation, since the
short circuit can be definitely established with a large metal plate, effectively
stopping all field propagation.
28. What are the two independent measurements that must be made to find the location
and length of the stub?
The standing wave ratio S and the position of a voltage minimum are the
independent measurements that must be made to find the location and length of
the stub.
29. Give the formula to calculate the distance of the point from the load at which the
stub is to be connected.
The formula to calculate the distance of the point from the load at which the stub
is to be Connected is, S1 = (ф +π-cos-1|K|)/(2β)
30. Give the formula to calculate the distance d from the voltage minimum to the point
stub be connection.
The formula to calculate the distance d from the voltage minimum to the point of
stub be connection is, d= cos-1|K| /(2β)
16 MARKS:
1. Explain the application of smith chart A 30 m long loss less transmission line with
Z0=50ohms operating at 2 MHz is terminated with a load ZL=60+j40ohms if U=0.6C find
the reflection coefficient y, the standing wave ratios and the input impedance.
2. i) Derive the expression that permit easy measurement of power flow on a line of
negligible losses.
3. ii) Derive the expression for input impedance of open and short circuited lines.
4. Discuss the various parameters of open wire and co axial lines at radio frequency.
5. (i) An ideal loss less quarter wave transmission line of characteristics impedance 60ohms
is terminated in a load impedance ZL. Give the value of the input impedance of the line
when
6. ZL=0, ∞ and 60ohm.
7. 5.i) A 100ohm, 200 m long loss less line transmission line operators at 10 MHz and its
terminated into an impedance of 50-j200ohm the transit time is 1μs. Determine the length
and location of short circuited stub line
8. 6. (i) Draw and explain the operation of quarter wave line.
9. It is required to match a 200 ohms load to a 300 ohms transmission line to reduce the
SWR along the line to 1. What must be the characteristic impedance of the quarter wave
transformer used for this purpose if it is directly connected to the load?
10. What are the drawbacks of single stub matching and open circuited stubs?
11. i) Derive equation of attenuation constant and phase constant of transmission line in terms
of line constants R, L, C and G and explain the significance of reflection coefficient and
insertion loss.
12. A generator of 1v, 1kHz supplies power to a 100km open wire line terminated in 200
ohms resistance The line parameter are R= 10ohm/km, L=3.8 Mh/km G= 1×10
mho/km. c=0.0085
13. μF/km calculate the impedance, reflection coefficient power and transmission
efficiency.
14. Explain the parameters of open wire line and co axial at RF. Mention the standard
assumptions made for radio frequency line.
15. Derive the expressions for the input impedance of the dissipation less line. Deduce the
input impedance of open and short circuited dissipation less line.
UNIT-III
IMPEDANCE MATCHING IN HIGH FREQUENCY LINES
2 MARKS:
1. Give the formula to calculate the length of the short circuited stub.
a. The formula to calculate the length of the short circuited stub is, L=λ/2π tan-
1
((s)½ /(s-1))
b. This is the length of the short . circuited stub to be placed d meters towards the
load from a point at which a voltage minimum existed before attachment of the
stub.
5. How is the circle diagram useful to find the input impendence of short and open
circuited lines?
An open circuited line has s =α the correspondent circle appearing as the
vertical axis .The input impendence is then pure reactance , with the
value for various electrical lengths determined by the intersections of the
corresponding βs circles with the vertical axis. A short circuited line may be
solved by determining its admittance .The S circle is again the vertical axis,
and suceptance values may be read off at appropriate intersection of the βs
circles with the vertical axis.
9. Give reason for an open line not frequently employed for impedance matching.
An open line is rarely used for impedance matching because of radiation
losses from the open end, and capacitance effects and the difficulty of smooth
adjustment of length.
11. Why Double stub matching is preferred over single stub matching.
Double stub matching is preferred over single stub due to following
disadvantages of single stub. Single stub matching is useful for a fixed
frequency. So as frequency changes the location of single stub will have to be
changed. The single stub matching system is based on the measurement of
voltage minimum .Hence for coaxial line it is very difficult to get such voltage
minimum, without using slotted line section.
16 MARKS:
1. i) Discuss the application of quarter wave line in impedance matching and copper
insulator.
ii) A 30 m long lossless transmission line with characteristic impedance Z₀ of 50Ω is
terminated by a load impedance ZL=60 + j 40Ω The operating wavelength is 90 m.
Find the reflection coefficient, standing wave ration and input impedance using
SMITH chart.
2. A 50 Ω transmission line is connected to a load impedance ZL= 60+j80Ω. The
operating frequency is 300MHz A double stub matching an eight of a wave length
apart is used to match the load to the line find the required lengths of the short
circuited stubs using SMITH chart.
3. i) A 75 Ω lossless transmission line is to be matched to a resistive load impedance of
ZL=100Ω via a quarter wave section find the characteristic impedance of the quarter
wave transformer.
13. A UHF lossless transmission line working at 1 GHz is connected to an unmatched line
producing a voltage reflection coefficient of 0.5(0.866 + j 0.5). Calculate the length
and position of the stub to match the line.
9. Write down the expression for cut off frequency when the wave is propagated in
between two parallel plates.
The cut-off frequency, fc = m/ (2a (µE)1/2)
12. Give the relation between the attenuation factor for TE waves and TM waves
αTE = aTM (fc/f)2
13. Define wave impedance
Wave impedance is defined as the ratio of electric to magnetic field strength
Zxy= Ex/ Hy in the positive direction
Zxy= -Ex/ Hy in the negative direction
16. Rectangular wave guide is smaller in size than a circular wave guide of the same
operating frequency
It does not maintain its polarization through the circular wave guide
The frequency difference between the lowest frequency on dominant mode and the
next mode of a rectangular wave-guide is bigger than in a circular wave guide.
20. What is the dominant mode for the TE waves in the rectangular waveguide?
The lowest mode for TE wave is TE10 (m=1 , n=0)
21. What is the dominant mode for the TM waves in the rectangular waveguide?
The lowest mode for TM wave is TM11(m=1 , n=1)
22. What is the dominant mode for the rectangular waveguide?
The lowest mode for TE wave is TE10 (m=1 , n=0) whereas the lowest mode for TM
wave is TM11(m=1 , n=1). The TE10 wave have the lowest cut off frequency compared to
the TM11 mode. Hence the TE10 (m=1 , n=0) is the dominant mode of a rectangular
waveguide. Because the TE10 mode has the lowest attenuation of all modes in a
rectangular waveguide and its electric field is definitely polarized in one direction
everywhere.
23. Which are the non-zero field components for the for the TM11 mode in a
rectangular waveguide?
Hx, Hy ,Ey. and Ez.
33. What are the disadvantages if the resonator is made using lumped elements at
high frequencies?
The inductance and the capacitance values are too small as the
frequency is increased beyond the VHF range and hence difficult to realize .
36. Why transmission line resonator is not usually used as microwave resonator?
At very high frequencies transmission line resonator does not give very high
quality factor Q due to skin effect and radiation loss. So, transmission line resonator is
not used as microwave resonator
16 MARKS:
1. i) Derive the expression for TM wave components in wave guides using Bessel
function. ii) Write the brief note on excitation of modes in circular wave guides.
2. Derive the equation for Q-factor of rectangular cavity resonator for TE₁₀₁ mode.
3. Derive the TM wave components in circular wave guide using Bessel function?
4. Calculate the resonant frequency of an air filed rectangular resonator of dimensions
a=3cm, b=2cm, d=4cm operating in TE₁₀₁ mode.
5. Derive the solution of field equation using cylindrical co-ordinates.
6. Draw the field configuration of different TM and TE modes for a circular guide.
7. A circular air filed copper cavity is excited in the TM₀₁₀ mode at 9.375 GHz. The
cavity has ratio length radius = 1.5. Find the Q-factor.
8. Derive expressions for the field components existing in a rectangular cavity.
9. Discuss the propagation of TM waves in a circular waveguide with relevant expression
for the field components.
10. Explain the field components of the TE waves in a rectangular cavity resonator with
relevant expression.
11. Calculate the cutoff wavelength, guide wavelength and characteristic wave impedance
of a circular wave guide with an internal diameter of 4 cm for a 10 GHz signal
propagated in it in the TE₁₁ mode.
12. A rectangular wave guide with dimension a=2.5cm, b=1cm is to operate below 15 GHz
How many TE and TM modes can the wave guide transmit if the guide is filed with a
medium characterized by σ=0, ͼ=4 ͼ0, βr=1? Calculate the cutoff frequency of the
modes.
13. Discuss the propagation of TM waves in a rectangular waveguide with relevant
expressions and diagrams for the field components.
2 Marks:
1. Define Transducer power gain?
The gain of amplifier when placed between source and load is called transducer power
gain(GT).
GT = Power delivered to load
Available power from source
2. Define Stability.
Stability in a network means when the magnitudes of reflection co-efficient are than
unity.
│ΓL│ ˂1 and │ΓS│˂ 1
6. What is HIPERLAN?
The HIPERLAN stands for High PERformance Radio LAN is an initiation of RES-10 group of the
ETSI as a PAN European standard for high speed wireless local networks
8. What is Bluetooth?
Bluetooth is an inexpensive personal area Ad-hoc network operating in unlicensed bands and owned
by the user. It is an open specification for short range wireless voice and data communications that
was developed for cable replacement in PAN (Personal Area Network).
The main reason for the development of WIMAX( World Interoperability Microwave Access ) is
the demand of high data rates not only the faster downloading but also for the use of new
applications like VoIP, Video, streaming multimedia conferencing and interactive gaming.
13. What is the functionality L2CAP? List the different types of logical channels. (N/D)-2017
L2CAP is a data link control protocol on top of the baseband layer offering logical channels
between Bluetooth devices with QOS properties.
Connectionless: These unidirectional channels are typically used for broadcasts from a master to its
slave(s).
Connection-oriented: Each channel of this type is bidirectional and supports QOS flow
specifications for each direction.
Signaling: This third type of logical channel is used to exchanging signaling messages between
L2CAP entities. Each channel can be identified by its channel Identifier (CID).
14. Give any three differences between HIPERLAN 1 AND HIPERLAN2 (A/M 2018)
HIPERLAN1: This high speed WLAN supports mobility at data rates above 20Mbit/s. Range is 50
m, connections are multi-point-to-multi-point using ad-hoc or infrastructure networks.
HIPERLAN2: This technology can be used for wireless access to ATM or IP networks and supports
up to 25Mbit/s user data rate in a point-to-multi-point configuration. Transmission range is 50m
with support of slow (<10m/s) mobility. This standard has been modified over time as a high
performance WLAN with QOS support.
15. What is IEEE 802.11? What is the function of MAC layer in IEEE 802.11? (A/M 2018)
IEEE 802.11 WLAN is designed to support a network where most decision-making is distributed to
mobile stations. Wireless LAN has the following components.
Wireless medium Stations
Basic service set
Extended service set
Distributed system
18. State the issues in designing a MAC protocol for adhoc wireless networks. (A/M-2015)
Bandwidth Efficiency
QoS support
Synchronization
Hidden and Exposed Terminal Problems
Error -Prone Share Broadcast Channel
Prone Share Broadcast Channel
19. What is the principle behind infrared technology? What are the advantages and
disadvantages of infrared technology? (N/D 2018)
The molecules emit infrared radiation as they move, and emit more radiation, including visible light,
as they get hotter. This is why a heated metal emits a red or white glow. The function of the
thermopile is to absorb infrared radiation and convert it to heat.
Advantages:
1. These devices very cheap
2. These devices consume low power, light weight.
Disadvantages:
1. It requires both transmitter and receiver in line of sight.
2. Used for very short distance applications.
The main purpose of the registration is to inform the HA of the current location for correct
forwarding of packets.
7. What is DHCP?
The Dynamic Host Configuration Protocol (DHCP) is based on the bootstrap protocol (BOOTP),
which provides the framework for passing configuration information to hosts on a TCP/IP network.
DHCP adds the automatically allocate reusable network addresses and configuration options to
internet hosts.
8. What is SIP?
The Session Initiation Protocol (SIP) is an application-layer control (signaling) protocol for creating,
modifying and terminating sessions with one or more participants. It is a IETF (Internet Standard)
RFC 3261 protocol.
12. When the agent solicitation message has to be sent by mobile node? (N/D)-2017
If no agent advertisement is present or the inter-arrival time is to high and the MN has not received a
COA by other reason.
So, the mobile node must send the agent solicitations.
14. What is a mobile IP? What are the entities of mobile IP? (A/M 2018)
Mobile IP is an internet protocol designed to support host mobility.
EC 8004WIRELESS NETWORKS Academic Year 2021-2022
Its goal is to provide the ability of a host to stay connected to the internet regardless of their
location.
Mobile IP is able to track a mobile host without needing to change the mobile host’s long-
term IP
address.
16. What is the need for self organization in a adhoc networks. (A/M-2015)
The general idea of a self-organization is that a global order arises from local interactions between
system components and a higher level of order is called emergent property of the system. Therefore
we could say that an ad hoc network can be considered as a self-organizing system and connectivity
as an emergent property.
18. Differentiate proactive and reactive routing protocols. write examples for each. (N/D 2018)
Proactive: A table -driven approach, follows a static route throughout the lifetime
Reactive: Dynamically changes the Routing decisions based on the present network
conditions.
Ex :
1.Distance Vector (DV) Protocol
2.Wireless Routing Protocol (WRP)
1. What is 3GPP?
3rd generation partnership project (3GPP) is a collaborative project aimed at developing globally
acceptable specifications for third generation mobile systems. The 3GPP caters to a large majority
of the telecommunications networks in the world.
based on using spread spectrum multiple access across multiple time slots. TD CDMA is the
channel access method for UTRA-TDD HCR, which is an acronym for UMTS terrestrial radio
access time division duplex high chip rate.
9. What is UMTS? What are the layers of UMTS? (A/M 2018)
The UMTS network architecture is partly based on existing 2G network components and some new
#G network components. It inherits the basic functional elements from GSM architecture on the
core network (CN) side. The CN provides circuit switched (CS) functions as well as packet
switched (PS) junctions.
23. What are the functions of MAC sub layer and Radio link control layer in UMTS?
The MAC sub layer is accountable for efficiently transferring data for both real time and non real
time services to physical layer and provides data transfer services on logical channels. It is also
responsible for
Service multiplexing on Random access channel (RACH)
Forward access channel (FACH)
Access control on RACH and FACH
Contention revolution on RACH
Radio link control sets up a logical link over the radio interface and is responsible for fulfilling Qos
requirements, It includes
Segmentation and assembly of packet data unit
Transfer of user data
Error correction through Retransmission
Sequence integrity
Flow control
EC 8004WIRELESS NETWORKS Academic Year 2021-2022
1. Give the advantages of Multicarrier modulation over single carrier schemes. (A/M 2018)
MCM’s advantages are better performance in the inter symbol-interference environment and
avoidance of single-frequency interferers. However, MCM increases the peak-to-average ratio of the
signal, and to overcome inter symbol interference a cyclic extension or guard band must be added to
the data.
2. What is meant by multi carrier modulation? Mention its merits and demerits? (N/D 2018)
Multi-carrier modulation (MCM) is a method of transmitting data by splitting it into several
components, and sending each of these components over
separate carrier signals. The individual carriers have narrow bandwidth , but the composite signal
can have broad bandwidth.
Advantages:
Makes efficient use of the spectrum by allowing overlap.
By dividing the channel into narrowband flat fading sub channels, OFDM is more resistant
to frequency selective fading than single carrier systems are.
Eliminates ISI and IFI through use of a cyclic prefix.
Using adequate channel coding and interleaving one can recover symbols lost due to the
frequency selectivity of the channel.
Channel equalization becomes simpler than by using adaptive equalization techniques with
single carrier systems.
Disadvantages :
The OFDM signal has a noise like amplitude with a very large dynamic range, therefore it
requires RF power amplifiers with a high peak to average power ratio.
It is more sensitive to carrier frequency offset and drift than single carrier systems are due to
leakage of the DFT.
3. What is the need to integrate 3G and WLANs?
The integration of 3G wireless and WLANs is highly significant to make wireless multimedia and
other high data rate services a reality for a large population. A multimedia 3G/WLAN terminal can
access high bandwidth data services where WLAN coverage is offered, while accessing wide area
networks using 3G at other places.
4. What are the objectives on internetworking?
To allow independent evolution of 3GPP (WWAN) and WLAN standards. The extent of
independence between these standards should be minimized or localized at the point of
interconnection.
To support legacy WLAN should be able to access 3GPP services without substantial
hardware/software upgrades
Single subscription
5. What are the requirements of internetworking?
Common billing and customer care
3GPP based access control and charging
Access to 3GPP based packet switched services
Service continuity
EC 8004WIRELESS NETWORKS Academic Year 2021-2022
4. Define 4G network.
4G can defined as MAGIC
MAGIC
Mobile Multimedia
Anytime Anywhere
Global Mobility Support
Integrated Wireless Solution
Customized Personal Services
Also known as Mobile Broadband Everywhere
8. What are the types of MCM that are likely preferred for 4G?
The two different types of MCM that are likely preferred for 4G are:
Multi Carrier Code Division Multiple Access
Orthogonal Frequency Division Multiplexing (OFDM) using TDMA
PART B QUESTIONS
UNIT 1
1. What are the basic differences between wireless WANs and WLANs, and what
are the common features? Consider mode of operation, administration,
frequencies, capabilities of nodes, services, national/international regulations.
2. With a neat sketch explain about MAC mechanism of IEEE 802.11.
3. Compare IEEE 802.11,Hiper LAN2, and Bluetooth with regard to their ad-hoc
capabilities. Where is the focus of these technologies?
4. If Bluetooth is a commercial success, what are remaining reasons for the use of
infra red transmission for WLANs?
5. Discuss the architecture, access method and frame format of IEEE 802.11
6. Explain WLAN technologies in detail?
7. Why is the PHY layer in IEEE 802.11 subdivide? What about hiperLAN2 and
Bluetooth?
EC 8004WIRELESS NETWORKS Academic Year 2021-2022
8. Compare the power saving mechanisms in all three LANs introduced in this
chapter?
9. Discuss the architecture of HIPERLAN 1 and HIPERLAN 2.
10. Explain Bluetooth protocol stack?
11. What are advantages and problems of forwarding mechanisms in Bluetooth
networks regarding security, power saving and network stability?
12. Name the reasons for the development of WATM. What is one of the ain
differences to internet technologies from this point of view? Why did WATM not
succeed as stand - alone technology, what parts of WATM succeeded?
13. Explain the frame format in Bluetooth technology?
14. Explain in detail Bluetooth security features and security levels with proper
diagrams?
15. Discuss Wimax. What are the main differences between WIFI and Wimax?
16. Compare 6LowPAn and Zigbee
17. Discuss in detail about 6lowPAN with neat sketch.
18. Draw and explain the architecture of Zigbee nework.
UNIT 2
1. What are the differences between AODV and the standard distance vector
algorithm? Why are extensions needed?
2. Discuss briefly about agent discovery and Registration process in Mobile IP.
3. Discuss in detail about IPv6 in the internet.
4. With example describe destination sequence distance vector routing protocol and
mention its features.
5. Explain the mobile IP session initiation protocol for IP packet delivery in Mobile
IP networks.
6. Explain about how tunnelling and encapsulation works in mobile IP networks.
7. Discuss in detail about the functions of DHCP protocol.
8. How does dynamic source routing handle routing? What is the motivation behind
dynamic source routing compared to other routing algorithm from fixed networks?
9. What are the benefits of location information for routing in ad-hoc networks,
which problems arise?
10. With neat sketch discuss about COAP protocol.
UNIT 3
EC 8004WIRELESS NETWORKS Academic Year 2021-2022
1. What are three channel types that are used in UMTS? Discuss the role of each
channel type.
2. With neat sketch explain the UTRAN logical architecture.
3. With neat diagram discuss the protocol model for UTRAN interfaces.
4. Discuss briefly about various interfaces used in UTRAN.
5. Draw and explain the 3GPP architecture.
6. Give the detailed radio access network overview. Explain in detail functions of
Node B and RNC. Discuss UMTS bearer service layered architecture.
7. Discuss the responsibilities of RNC in the UMTS network.
8. Explain the UMTS core network architecture with neat diagram.
9. Discuss in detail about TD – CDMA and TD – SCDMA.
UNIT 4
1. Discuss about various methods of internetworking schemes to connect WLANS
and 3G networks
2. With neat sketch describe about the internetworking architecture for WLAN and
GPRS.
3. Discuss about system integration and protocol stack with tight coupling
4. With neat sketch discuss the system integration and protocol stack with loose
coupling
5. Explain in detail about Local multipoint distribution service with neat diagram
6. Compare the LMDS with MMDS
7. Explain in detail about Multichannel multipoint distribution service with neat
diagram
UNIT 5
1. Discuss the 4G features and challenges. And list out the applications of 4G
2. Write short notes on i) smart antenna techniques ii) Multi carrier modulation
3. Compare 3G and 4G
4. Discuss about technologies used in 4G
5. With neat diagram explain about the architecture of IMS
6. Describe in detail about the LTE network architecture with neat sketch
7. Write short notes on MVNO.
8. What is multi input and multi output system? Explain and compare.
EC 8004WIRELESS NETWORKS Academic Year 2021-2022