EC8691 - MICROPROCESSORS

AND MICROCONTROLLERS

1.1
 BLOOM’S TAXONOMY LEVELS (BTL)

Level 1 – Remembering (R)

Level 2 – Understanding (U)
Level 3 – Applying (A)
Level 4 – Analyzing (AZ)
Level 5 – Evaluating (E)
Level 6 – Creating (C)
UNIT-I THE 8086 MICROPROCESSOR

Part-A
1. Define microprocessor? (R)

A microprocessor is a multipurpose, programmable, clock-driven, register –

based electronic device that reads binary instructions from a storage device called memory
. Accepts binary data as input and processes data according to instructions, and provides
result as output.

2. What are the basic units of a microprocessor ? (R)

The basic units or blocks of a microprocessor are ALU, an array of registers and control
unit.

3. What are machine language and assembly language programs?(U)

The software developed using 1's and 0's are called machine language programs. The
software developed using mnemonics are called assembly language programs.

4. What is the drawback in machine language and assembly language programs?(U)

The machine language and assembly language programs are machine dependent. The
programs developed using these languages for a particular machine cannot be directly run on
another machine.

5. What is assembly language? (R)

The language in which the mnemonics (short -hand form of instructions) are used to
write a program is called assembly language. The manufacturers of microprocessor give the
mnemonics.

6. Define bit, byte and word.(U)

A digit of the binary number or code is called bit. Also, the bit is the fundamental storage
unit of computer memory. The 8-bit (8-digit) binary number or code is called byte and 16-bit
binary number or code is called word. (Some microprocessor manufactures refer the basic data
size operated by the processor as word).

7. What is a bus? (R)

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 Bus is a group of conducting lines that carries data, address and control signals.

8. Why data bus is bi-directional?(U)

The microprocessor has to fetch (read) the data from memory or input device for
processing and after processing, it has to store (write) the data to memory or output device.
Hence the data bus is bi-directional.

9. Why address bus is unidirectional?(U)

The address is an identification number used by the microprocessor to identify or access

a memory location or I / O device. It is an output signal from the processor. Hence the address
bus is unidirectional.

10. Differentiate between Memory mapped I/O and I/O mapped I/O.(AZ)

S.NO Memory mapped I/O I/O mapped I/O

1. It is treated as memory location It is not treated as memory
location
2. No special instructions are It requires special instructions
needed to access the I/O devices like IN, OUT to access I/O
devices
3. Microprocessor can access 1 Microprocessor can access 64
MByte memory locations or I/O KByte memory locations or I/O
ports ports
4. It requires 20 address lines It requires 16 address lines
5. MEMR, MEMW signals can be IOR , IOW signals are used
used to access I/O devices
6. It is suitable for small system It is suitable for large system

11. What is an interrupt? (R)

Interrupt is a signal send by an external device to the processor so as to request the

processor to perform a particular task or work.

12. Define (a)Instruction Cycle (b) M/C Cycle (c) T-state. (R)

Instruction cycle: Time required completing the execution of an instruction. One

instruction cycle consists of 3 to 6 machine cycles.
Machine cycle: Time required completing one operation of accessing memory or I/O
device. One machine cycle consists of 3 to 6 T-states.
T-State: The portion of the operation performed in one clock period.

13. Define machine cycle. (R)

Machine cycle is defined as the time required to complete one operation of accessing
memory, I/O, or acknowledging an external request. This cycle may consist of three to six T-
states.
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14. Define T-State. (R)

T-State is defined as one subdivision of the operation performed in one clock period.
These subdivisions are internal states synchronized with the system clock, and each T-State is
precisely equal to one clock period.

15. What is the difference between Opcode and Operand?(AZ)

Opcode is the part of an instruction that identifies a specific operation. Operand is a part
of an instruction that represents a value on which the instruction acts.
Example: MVI A ,18H MVI A is Opcode and 18 H is Operand.
16. What is Stack and Subroutine? (R)

Stack -It is a reserved area of the memory in the RAM , where temporary information
may be stored. Subroutine-It is a group of instructions written from the main program to perform
a function that occurs repeatedly in the main program

17. What are the difference between PUSH and POP instruction?(AZ)

S.NO PUSH POP

1. Push register pack onto stack Pop off stack to register pair
2. The contents of the register pair The contents of memory location
designated in the operand are pointed out by the SP register are
copied into the stack. The SP is copied into the low order register of
decremented and the contents of the operand.
the high order register are copied
into that location.

18. What is meant by LATCH? (U)

Latch is a D- type flip-flop used as a temporary storage device controlled by a timing

signal, which can store 0 or 1. The primary function of a Latch is data storage. It is used in
output devices such as LED, to hold the data for display.

19. What is flag? (R)

Flag is a flip-flop used to store the information about the status of a processor and the status
of the instruction executed most recently.

20. Why are the program counter and the stack pointer 16-bit registers? [NOV/DEC
2012](AZ)

Program Counter (PC) and Stack Pointer (SP) are basically used to hold 16-bit memory
addresses. PC stores the 16-bit memory address of the next instruction to be fetched. SP can be
used to temporarily store the 16-bit memory address as well as data. So PC & SP are 16-bit
registers.

21. What are the modes in which 8086 can operate?(U)

The 8086 can operate in two modes and they are minimum (or uniprocessor) mode and
maximum ( or multiprocessor) mode.
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22. What are the flags in 8086? (R)

 Carry flag
 Parity flag
 Auxiliary carry flag
 Zero flag
 Overflow flag
 Trap flag
 Interrupt flag
 Direction flag and
 Sign flag.
23. What are the various interrupts in 8086? (R)

Maskable interrupts, Non-Maskable interrupts.

24. What is meant by Maskable interrupts and Non-Maskable interrupts? (R)

An interrupt that can be turned off by the programmer is known as Maskable interrupt.
An interrupt which can be never be turned off (ie.disabled) is known as Non-Maskable
interrupt.

25. What is meant by vectored interrupt? [MAY/JUNE 2014] (R)

A vectored interrupt is a processing technique in which the interrupting device directs the
processor to the appropriate interrupt service routine. Vectored interrupts are achieved by
assigning each interrupting device a unique code, typically four to eight bits in length. [1] When a
device interrupts, it sends its unique code over the data bus to the processor, telling the processor
which interrupt service routine to execute.

26. What are the different functional units in 8086? (R)

Bus Interface Unit and Execution unit are the two different functional units in 8086.

27. Which Segment is used to store interrupt and subroutine return address registers? (U)

Stack Segment in segment register is used to store interrupt and subroutine return
address registers.

28. Which Flags can be set or reset by the programmer and also used to control the
Operation of the processor? (U)

Trap Flag, Interrupt Flag, Direction Flag.

29. What does EU do?(U)

Execution Unit receives program instruction codes and data from BIU, executes
these instructions and store the result in general registers.

30. What are the addressing modes of 8086? (R)

 Immediate addressing mode

 Direct addressing mode
1.5
  Register addressing mode
 Register indirect addressing mode
 Indexed addressing mode
 Register relative addressing mode
 Based indexed addressing mode
 Relative based indexed addressing mode
 Intra segment direct mode
 Intra segment indirect mode
 Inter segment direct mode
 Inter segment indirect mode
31. What are the types of instructions in instruction set of 8086? (R)

 Data copy / Transfer instructions

 Arithmetic and Logical instructions
 Branch instructions
 Machine control instructions
 Flag manipulation instructions
 String instructions

32. List some functions of BIU?(U)

 Sends address of the memory or I/O

 Fetches instructions from memory
 Reads data from port / memory
 Writes data into port / memory
 Supports instruction queuing
 Provides address relocation facility

33. Define assembler directives? (R)

There are some instructions in the assembly language program which are not a part of
processor instruction set. These are instructions to assembler and are referred as pseudo
operations or assembler directives.

34. List some features of 8086? (R)

 16 bit microprocessor
 Has a 16 bit data bus, 20 bit address bus
 Can generate 16 bit I / O address
 Provides fourteen 16 bit registers
 Has multiplexed address and data bus
 Can operate in minimum and maximum mode

35. What is pipelining? (R)

In 8086, to speed up the execution of program, the instructions fetching and execution of
instructions are overlapped each other. This technique is known as pipelining. In pipelining,
when the n th instruction is executed, the n+1 th instruction is fetched and thus the processing
speed is increased.

36. How many data lines and address lines are available in 8086? (R)
1.6
 Address lines= 20 bit address bus
Data lines= 16 bit data bus

37. What is the use of Instruction Queue in 8086 microprocessor? (U)

The queue operates on the principle of first in first out(FIFO). So that the execution unit
gets the instruction for execution in the order they fetched .Feature of fetching the next
instruction while the current instruction is executing is called pipelining which will reduce the
execution time.

38. Write the size of physical memory and virtual memory of 8086 microprocessor. (R)

Physical addresses are formed when the left shifted segment base address is added to the
offset address. The combination of segment register base addresses and offset address is the
logical address in memory.
Size of physical memory=220=1MB
Size of virtual memory=216=64 KB

39. List the advantages of using segment registers in 8086. (R)

 It allows the memory addressing capacity to be 1MB even though the address
associated with individual instruction is only 16-bit.
 It facilitates use of separate memory areas for program , data and stack.
 It allows the program to be relocated which is very useful in multiprogramming.

40. What are the segment registers of 8086? (R)

CS- Code segment, DS-Data segment, ES-Extra segment, SS- Stack segment.

41. State the operation of minimum mode 8086 system? (R)

The 8086 microprocessor can be operated in minimum mode by connecting MN /

MX pin to logic1. In this mode all control signals are given by the microprocessor chip itself.
There is only a single microprocessor in minimum mode system.

42. What is pipelined architecture? (R)

In pipelined architecture the processor will have number of functional units and the
execution time of functional units is overlapped. Each functional unit works independently most
of the time.

43. What is the difference between segment register and general-purpose register? (AZ)

The segment registers are used to store 16-bit segment base address of the four memory
segments. The general-purpose registers are used s the source or destination register during data
transfer and computations, as pointers to memory and as counters.

44. What is the control bits used in IC 8086? (R)

The flags TF, IF and DF of 8086 are used to control the processor operation and so they
are called control bits.
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45. What is queue? How queue is implemented in 8086? (R)

A data structure, which can be accessed on the basis of first in first out, is called queue.
The 8086 have six numbers of 8-bit FIFO registers, which is used for instruction queue.

46. What is the general purpose registers in 8086? (Nov/Dec 2011) (R)

The general purpose registers in 8086 are ax, bx, cx, dx, si, di, bp and sp. They are all 16
bit wide. Each of these has a special purpose in addition to their being of general purpose. For
example, CX is used as a counter in conjunction.

47. Discuss the function of instruction queue in 8086? (A)

In 8086, a 6-byte instruction queue is presented at the Bus Interface Unit (BIU). It is
used to prefetch and store at the maximum of 6 bytes of instruction code from the memory. Due
to this, overlapping instruction fetch with instruction execution increases the processing speed.

48. Give the importance of assembler directive EVEN. [NOV/DEC 2011]. (R)

The EVEN directive updates the location counter to the next even address, if the current
location counter contents are not even, and assigns the following routine or variable or constant
to that address.
EVEN
PROCEDURE ROOT
.
.
ROOT ENDP

49. List the pointer and index registers of 8086 architecture.[NOV/DEC 2010]. (R)

The pointers contain offset within the particular segment.

The pointer registers are
IP - Instruction Pointer
BP - Base Pointer
SP - Stack Pointer.
The index registers are used as general purpose registers as well as for offset storage.
SI - Source Index Register - used to store the offset of source data
DI - Destination Index Register - used to store the offset of destination data.

50. Identify the addressing modes involved in the following 8086 instructions:
MOV AX, 0005H; MOV AX, 50H [BX] [SI]. [NOV/DEC 2010]. (U)

MOV AX, 0005H - Immediate Addressing Mode

MOV AX, 50H [BX] [SI] - Relative Based Indexed Addressing Mode

51. What are assembler directives? Give examples. [APRIL / MAY 2011] (R)

Assembler directives help the assembler to correctly understand the assembly language
programs to prepare the codes.
Examples: DB - Define Byte
DW - Define Word
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END - End of Program
ENDP - End of Procedure.

52. What address in the interrupt vector table, are used for a Type-2 interrupt in 8086?
[NOV/DEC 2012] (R)

The address used in the interrupt vector table for a Type-2 interrupt is 0000:0008 to
0000:000A reserved for Non-Maskable Interrupt.

53. Why do we use macros?[NOV/DEC 2012] (R)

Suppose a number of instructions are appearing again and again in the main program, the
program becomes lengthy. So, a label is assigned with the repeatedly appearing string of
instructions is called macro. Macro reduces the time for execution.

54. What do you mean by addressing modes? [MAY/JUNE 2014] (R)

An addressing mode specifies how to calculate the effective memory address of an

operand by using information held in registers and/or constants contained within a machine
instruction or elsewhere.

Part – B & C

1. Draw the 8086 functional block diagram and explain its architectural features.
(May 07, May 10, May 12.Nov 08, Nov 11, Nov 2012)(U)
2. Draw and explain the pin configuration of 8086. (May 12, May 07)(U)
3. Explain in detail about the various addressing modes used in 8086 processor? Give
Examples. (May 08, Nov 08, Nov 10, May 11)(U)
4. Explain the string manipulation instructions, process control instructions, and program
Execution transfer instruction, bit manipulation instructions and machine control
Instructions of 8086 microprocessor with suitable examples.(Nov 10, May 10) (U)
5. Discuss in detail about the interrupts and Interrupt Service Routine (ISR) with interrupts
Cycle of 8086.(Nov 07, May 12, Nov 10, May 08, May 07, Nov 11, Nov 2012) (U)
6. What are assembler directives? Explain ENDP, EQU, EXTERN, EVEN with example.
(May 10, May 12, May 07, May 2013) (R)
7. Explain the BIOS function, procedures and Macros. (Nov 08, May 06, May 12, Nov 10)(U)
8. Develop an 8086 assembly language program for transferring block of data from one set of
Memory location to other set of memory locations using suitable string instructions.
(Nov 07, May 08) (C)
9. Give an example of 8086 instructions: AAA, CWD, JNBE, LAHF, MOVS, RCL, ROL and
SAHF. (Nov 2012) (R & U)
10. Explain how to pass parameters to macros? (May 2012)(U)
11. How does one define and call macro parameters of 8086 microprocessor? (May 10)(AZ)
12. Draw and discuss the interrupt structure of 8086. (May 2014)(U)

1.9
 UNIT - II 8086 SYSTEM BUS STRUCTURE

Part – A

1.What is the function of LOCK and RQ/GT Signals? [MAY/JUNE 2013] (R)

LOCK - this output pin indicates that other system bus masters will be prevented from
gaining the system bus, while the LOCK signal is low.

RQ/GT - Request/Grant - these pins are used by other local bus masters to force the
processor to release the local bus at the end of the processor's current bus cycle.

2. What is the minimum mode signals used in 8086? (R)

The minimum mode signals used in 8086 are DT/R, DEN, ALE, M/IO, WR, INTA,
HOLD and HLDA.

3. Describe about the maximum mode 8086 system? (R &U)

In maximum mode, the 8086 is operated by connecting the MN / MX pin to ground. The
processor drives the status signals S1, S2 and S3. Another chip called bus controller drives the
control signals using the status information.

4. How clock signal is generated in 8086? What is the maximum internal clock frequency
of 8086? (U)

The 8086 do not have on-chip clock generation circuit. Hence the clock generation chip,
8284 is connected to CLK pin of 8086.the clock signal supplied by 8284 is divided by three for
internal use. The maximum internal clock frequency is 5MHz.

5. What are the signals used in 8086 maximum mode operation? (R)

Qs1, Qs0, s0, s1, s2, LOCK, RQ/GT1, and RQ/GT0 are the signals used in 8086
maximum mode operation.

6. What are the signals involved in memory bank selection in 8086 microprocessor? (R)

Entire memory is divided into two memory banks : bank0 and bank1. Bank0 is selected
only when A0 is zero and Bank1 is selected only when BHE is zero. A0 is zero for all even
addresses. So bank0 is usually referred as even addressed memory bank.BHE is used to access
higher order memory bank , referred to as odd addressed memory bank.

7. What is the use of MN/MX signals in 8086? (R)

It is used to operate the microprocessor in two operating modes i.e. maximum and
minimum mode. The minimum mode is used for small systems with a single processor and
maximum mode is for medium size to large systems, which include two or more processors.

8. Differentiate between tightly coupled and loosely coupled configurations? (Apr/may

2010) (AZ)

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  In a tightly coupled configuration, the 8089 shares the system bus and memory with the
host CPU using the RQ / GT pins
 In a loosely coupled configuration, 8089 has its own local bus and communicate with the
host using the bus arbiter and controller.

9. What are the three basic bus access control and arbitration scheme? (R)

 Daisy chaining
 Independent request
 Polling
10. List the advantages of loosely coupled systems over the tightly couples systems? (R)

 More number of CPUs can be added in a loosely coupled system to improve the
system performance.
 System structure is modular and hence easy to maintain and trouble shoot.
 Fault in a single module does not lead to a complete system break down.
 It is more fault tolerant due to independent processing modules.
 More suitable to parallel applications due to its modular organization.

11. State the disadvantages of microprocessor based system design? (R)

 Overall system cost is high as compared to microcontroller based system.

 A large size PCB is required for assembling all the components, resulting in an
enhanced cost of the system.
 Overall product design requires more time.
 Physical size of the product is big and it is not handy.

12. What is a co-processor? What is its use in a typical microprocessor based system.
(Apr/may 2010) (R)

8087 NDP (numerical data processor) is also known as math co-processor which is used
in parallel with the main processor for number crunching applications, which would otherwise
require complex programming. It is also faster than 8086/8088 processor in performing
mathematical computation. It has its own specialized instruction sets to handle mathematical
programs. It is a processor which works in parallel with the main processor. It has its own set of
specialized instructions. The number crunching part of the program is executed by 8087.
Instruction for 8087 are written in the main program interspersed with the 8086 instructions. All
the 8087 instruction codes have 11011 as the most significant bits of their first code byte.

13. What is bus contention? (U)

Bus contention, in computer design, is an undesirable state of the bus in which more than
one device on the bus attempts to place values on the bus at the same time. Most bus
architectures require their devices follow an arbitration protocol carefully designed to make the
likelihood of contention negligible. However, when devices on the bus have logic errors,
manufacturing defects or are driven beyond their design speeds, arbitration may break down and
contention may result. Contention may also arise on systems which have a programmable
memory mapping and when illegal values are written to the registers controlling the mapping.

14. Give the types of multiprocessor configuration. (R)

Types of multiprocessor configuration:
1. Coprocessor configuration
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2. Closely coupled configuration
3. Loosely coupled configuration

15. Write a short note on data register in 8087. (R)

1. It has 8 data register.
2. Each register is 8 bit and accessed as a stack
3. A PUSH operation decrements the TOP of the stack by one and loads the value on
The top register.
4. A POP register stores the value from the current TOP register and increments TOP
by one.

16. Write a short note on status register in 8087. (R)

1. Status register is 16 bit register.

2. It indicates various errors, stores condition code for certain instruction and indicates
the BUSY status.

17. Write a short note on TAG register in 8087. (R)

TAG register holds the status of the contents of the data register.
00 - Data valid
01 - Zero
10 - A special value
11 – Empty

18. List any four 8087 data formats.[MAY/JUNE 2012] (R)

• Word integer
• Short integer
• Long integer
• Packed BCD
• Short real
• Temporary real

19. Give the instruction set of 8087? (R)

1. Data Transfer Instructions

2. Arithmetic Instructions
3. Comparison Instructions.
4. Transcendental Operations.
5. Constant Operations.
6. Coprocessor Control Operations.

20. How does CPU differentiate the 8087 instructions from its own instructions?
[MAY/JUNE 2013,NOV/DEC 2012,APRIL/MAY 2011] (U)

The CPU identifies the 8087 instructions by using ESCAPE code bits in them. Once the
CPU recognizes the ESCAPE code, it triggers the execution of the numeric processor instruction
in 8087.

1.12
21. Mention the need for co-processor in a microprocessor based system?
[APRIL/MAY 2010] (U)

In a microprocessor based system, the co-processor is needed for achieving higher

processing speed, capable of performing complicated calculations in less time.

22. What are the two internal sections of 8087 architecture? [NOV/DEC 2010] (R)

8087 is divided into two sections internally as

o control unit (CU)
o numeric extension unit (NEU)

23. What is meant by loosely coupled configuration? [MAY 2014] (R)

Loosely coupled system consists of different processor module, each processor has a set
of input-output devices and a large local memory where it accesses most of the instructions and
data, to which other processors do not have direct access. But, they can share system resources.
The processor, its local memory and input-output interfaces together called computer module.

24. What are tightly coupled systems or closely coupled systems? (R)

In a tightly coupled systems the microprocessor (either coprocessor or independent

processors may share a common clock and bus control logic.. The two processors in a closely
coupled system may communicate using a common system bus or common memory.

25. What are loosely coupled systems?(Apr/May 2010) (R)

In loosely coupled systems each CPU may have its own bus control logic. The bus
arbitration is handled by an external circuit, common to all processors. The loosely coupled
system configuration like LAN & WAN can be spreaded over a large area.

26. Write some disadvantages of loosely coupled systems. (U)

 More complicated due to the required additional communication hardware.

 They are less portable and more expensive due to the additional hardware and the
communication media requirement.

27. What are the multi microprocessor configuration methods.[apr/may 2009] (R)

 Tightly coupled systems or closely coupled systems

 Loosely coupled systems

28. What is meant by Daisy chaining method? (R)

It does not require any priority resolving network, rather the priorities of all the devices
are essentially assumed to be in sequence. All the masters use a single bus request line for
requesting the bus access. The controller sends a bus grant signal, in response to the request, if
the busy signal is inactive when the bus is free. The bus grant pulse goes to each of the masters
in the sequence till it reaches a requesting master .The master then receives the grant signal,
activates the busy line and gains the control of the bus. The priority is decided by the position
of the requesting master in the sequence.

1.13
29. What is independent bus request scheme? (R)

Each of the masters requires a pair of request and grant pins which are connected to the
controlling logic. The busy line is common for all the masters. . f the controlling logic receives
a request on a bus request line, it immediately grants the bus access using the corresponding
bus grant signal, provided the BUSY line is inactive, and then grants the request. This is quite
fast, because each of the masters can independently communicate with the controller.

30. What is meant by polling? (R)

In polling schemes, a set of address lines is driven by the controller to address each of
the masters in sequence. When a bus request is received from a device by the controller, it
generates the address on the address lines. If the generated address matches with that of the
requesting masters, the controller activates the BUSY line.

PART B & C

1. Draw and explain the minimum mode configuration of 8086 with timing diagram. (AZ)
(Nov 11, Nov 05, May 06, Nov 10, Nov 08, May 2013)

2. Draw and explain the maximum mode configuration of 8086 with timing diagram.(AZ)
(Nov 07, Nov 08, May 06, May 07, May 08, Nov 10, May 11, May 2013)

3. Explain the multiprocessor configuration of 8086. (Nov 07, May 07) (U)

4. Explain the architecture of 8087 with neat block diagram.(May07, May08, May10, May 12,
Nov 11) (U)

5. Explain the 8087 co-processor data format. (May 10, May 21, Nov 10) (U)

6. Explain in detail about closely coupled and loosely coupled configuration. What are the
relative advantages and disadvantages? (Nov 07, Nov 10, May 08, Nov 11) (U)

7. Discuss the schemes used to solve bus arbitration problem in multiprocessors. (Nov 11)(U)

8. Explain the exception handling feature of 8087. (Nov 10)(U)

9. Explain the closely coupled configuration of multiprocessor configuration with suitable

example. (May 2014)(U)

10. Explain the execution steps of 8087. (May 2014)(U)

1.14
 UNIT – III I/O INTERFACING

Part – A

1. What are the modes of operation of 8255? (R)

 BSR Mode
 IO Mode
- Mode 0
- Mode 1
- Mode 2

2. List the steps in the general algorithm for ADC interfacing? (R)

o Ensure the stability of analog input applied to the ADC.

o Issue start of conversion (SOC) pulse to ADC.
o Read end of conversion (EOC) signal to mark the end of conversion process.
o Read analog data output of the ADC as equivalent digital output.

3. List the six modes of operation of 8253? (R)

 Mode 0 (Interrupt on terminal count)

 Mode 1 (Programmable monoshot)
 Mode 2 (Rate generator)
 Mode 3 (Square wave generator)
 Mode 4 (Software triggered strobe)
 Mode 5 (Hardware triggered strobe)

4. List the command words of 8259A. (R)

 Initialization command word &

 Operation command word

5. What are the operational modes of 8279? (R)

 Input (Keyboard) mode &

 Output (Display) mode

6. What are three modes of data transmission? (R)

 Simplex
 Half duplex &
 Full duplex
7. List the transfer modes of 8237? [ MAY/JUNE 2013] .(R)
 Single transfer mode
 Block transfer mode
 Demand transfer mode
 Cascade mode
 Memory to memory transfer
8. List the commands that can be executed by 8237? (R)

1.15
  Clear First / Last Flip flop
 Clear Mask Register
 Master Clear Command

9. List the salient features of Mode0 of 8255? (R)

 Two 8 bit ports ( Port A and Port B ) and two 4 bit ports ( Port C upper and lower) are
available. The two 4 bit ports can be combinedly used as third 8 bit port.
 Any port can be used as an input or output port.
 Output ports are latched. Input ports are not latched.
 A maximum of 4 ports are available so that overall 16 I / O configurations are possible.

10. State the features of 8255 in Mode1? (R)

 Group A and Group B are available for strobed data transfer.

 Each group contain one 8bit data I / O port and one 4 bit control / data port.
 8bit data port can be either used as input or output port.
 Out of 8bit portC, PC0 – PC2 are used to generate control signals for port B, PC3
– Pc5 are used to generate control signals for port A. PC6, PC7 may be used as
independent data lines.

11. State the salient features of Mode2 of 8255? (R)

o Single 8 bit port in group A is available

o 8bit port is bidirectional and a 5bit control port is available.
o 3 I / O ports are available at port C, PC2 – PC0
o Inputs and outputs are both latched.
o 5 control bits of portC (PC3 – PC7) is used for generating / accepting handshake signals
for the 8bit data transfer on portA.

12. What is the disadvantage in keyboard interfacing using ports? (R)

The disadvantage in keyboard interfacing using ports is that most of the processor time is
utilized in keyboard scanning and debouncing. As a result the computational speed of the
processor will be reduced.

13.What is the advantage in using INTEL 8279 for keyboard and display interfacing? (R)

When 8279 is used for keyboard and display interfacing, it takes care of all the task
involved in keyboard scanning and display refreshing. Hence the processor is relieved from the
task of keyboard scanning, debouncing, keyboard generation and display refreshing and the
processor time can be more effectively used for computing.

14. What is a programmable peripheral device? (R)

If the functions performed by a peripheral device can be altered or changed by a

program instruction, then the peripheral device is called programmable device. Usually the
programmable devices will have control registers. The device can be programmed by sending
control word in the prescribed format to the control register.

15. What is synchronous data transfer scheme? (R)

1.16
 In synchronous data transfer scheme, the processor does not check the readiness of the
device after a command have been issued for read/write operation in this scheme the processor
will request the device to get ready and then read/write to the device immediately after the
request.

16. What is asynchronous data transfer scheme? (R)

In asynchronous data transfer scheme, first the processor sends a request to the device
for read/write operation. Then the processor keeps on polling the status of the device. Once the
device is ready, the processor execute a data transfer instruction to complete the process.

17. What are the operating modes of 8255? (R)

The port of 8255 can be programmed to work in any one of the following operating
modes as input or output port.
Mode-0 : simple I/O port , Mode-1 :handshake I/O port , Mode-2:bi-directional I/O port

18. What are the functions performed by port-C of 8255? (R)

 the port-C pins are used for handshake signals.

 Port-C can be used as an 8-bit parallel I/O port in mode-0
 It can be used as two numbers of 4-bit parallel port in mode-0
 The individual pins of port-C can be set or reset for various control applications.

19. What is USART? (R)

The device which can be programmed to perform synchronous or asynchronous serial

communication is called USART(Universal Synchronous Asynchronous Receiver
Transmitter).The INTEL 8251 is an example of USART.

20. What are the functions performed by INTEL 8251? (U)

The INTEL 8251 is used for converting parallel data to serial or viceversa.the data
transmission or reception can be either asynchronous or synchronous. The 8251 can be used to
interface MODEM and or synchronously. The 8251 can be used to interface MODEM and
establish serial communication through MODEM over telephone lines.

21. What are the control words of 8251 and what are its functions? (R)

The control words of 8251 are mode word and command word. The mode word informs
8251 about the baud rate, character length, parity and stop bits .The command word can be send
to enable the data transmission and reception.

22. What is the information that can be obtained from the status word of 8251? (R)

The CPU to check the readiness of the transmitter or receiver and to check the character
synchronization in synchronous reception can read the status word. It also provides information
regarding various errors in the data received .The various error conditions that can be checked
from the status word are the parity error, overrun error and framing error.

23. What is baud rate? (R)

1.17
 The baud rate at which the serial data are transmitted. Baud rate is defined as 1/(the time
for a bit cell).In some systems one bit cell has one data bit, then the baud rate and bits/sec are
same.

24. What are the different types of data transfer scheme? (R)

The different types of data transfer transfer scheme are

 Synchronous u data transfer scheme.
 Asynchronous data transfer scheme
 Interrupt driven data transfer scheme.

25. What are the different types of DMA data transfer scheme? (R)

The different types of DMA data transfer scheme are

 Cycle stealing DMA
 Block or burst mode DMA
 Demand transfer mode DMA

26. What is the need for interrupt controller? (U)

The interrupt controller is employed to expand the interrupt inputs. It can handle the
interrupt request from various devices and allow one by one to the processor.

27. List some of the features of INTEL 8259? (R)

 It manage eight interrupt request

 The interrupt vector addresses are programmable
 The priorities of interrupts are programmable.
 The interrupt can be masked or unmasked individually.

28. Write the various functional blocks of INTEL 8259? (R)

The various functional blocks of 8259 are control logic, read/write logic, data bus buffer,
interrupt request register, in service register, interrupt mask register, priority resolver and
cascade buffer.

29. How 8259 is programmed? (U)

The 8259 is programmed by sending initialization command words(ICW’s) and

operational command words(OCW’s).

30. What are the features of 8259 that can be programmed using OCW’s? (R)

The OCW’s are used to program the following features of 8259

 masking of individual interrupts
 specific on nonspecific end of interrupt
 priority modes

1.18
31. What are the different scan modes of 8279? (R)

The different scan modes of 8279 are decoded scan and encoded scan and encoded scan.
In decoded scan, the output of scan lines will be similar to a 2-to-4 decoder. In encoded scan
mode, the output of scan lines will be binary count, and so an external decoder should be used to
convert the binary count to decoded output.

32. What are the different programmed data transfer schemes used in microprocessor?
(R)

The various data tranfer schemes are

 Synchronous data transfer
 Asynchronous data transfer(hand shaking)
 Interrupt driven data transfer

33. What are the two various modes of DMA transfer? (R)

 Burst mode
 Cycle stealing

34. What is meant by control word? (U)

The content of control register is called as control word or command word. It

specifies the various mode of operations, I/O functions of the port etc.

35. What is handshake port ? Explain the working of a handshake input port and output
port. (U)
In handshake port, signals are exchanged between I/O device and port or
port and processor for checking or informing various condition of the device.
In handshake input operation, the input device will check whether the port is empty or not. If the
port is empty then it will load data to port. When the port receives the data, it will inform the
processor for read operation. Once the data have been read by the processor, the port will signal
the input device that it is empty. Now the input device can load another data to port and the
above process is repeated.
In handshake output operation, the processor will load a data to port. When the port
receives the data, it will inform the output device to collect the data. Once the output device
accepts the data, the port will inform the processor that it is empty. Now the processor can
load another data to port and the above process is repeated.

36. What is debouncing ? (U)

When a key is, pressed it bounces for a short time. If a key code is generated
immediately after sensing a key actuation, then the processor will generate the same keycode a
number of times.(A key typically bounces for 10 to 20 msec). Hence the processor has to wait
for the key bounces to settle before reading the keycode. This process is called keyboard
debouncing.

37. What are the requirements to be met while interfacing memory or I/O devices to
8086 processor? [MAY/JUN 2013] (R)

The requirements to be met are:

1.19
  the microprocessor should be able to select the chip
 identify the register
 enable the appropriate buffer

38. What is DMA? [NOV/DEC 2011] (R)

DMA is direct memory access technique in which the bulk data is transferred directly
to/from memory under the control of a DMA controller without any interference from the CPU.

39. State the use of cascading signals of 8259 programmable interrupt controller.
[APRIL/MAY 2011]. (R)

CAS0-CAS2 Cascade lines - A single 8259 provides eight vectored interrupts. If more
interrupts are required, 8259 is used in cascade mode. In cascade mode, a master 8259 along
with eight slaves 8259 can provide upto 64 vectored interrupt lines. These three lines act as
select lines for addressing the slaves 8259.

40. What are the advantages of Programmable Interval Timer / Counter IC? [ MAY
2014] (R)
The Intel 8253 and 8254 are Programmable Interval Timers (PITs), which perform
timing and counting functions. The timer has three counters, called channels. Each channel can
be programmed to operate in one of six modes. Once programmed, the channels can perform
their tasks independently. The timer is usually assigned to IRQ-0 (highest priority hardware
interrupt) because of the critical function it performs and because so many devices depend on it.

PART B & C

1. Explain the block diagram of 8255 (PPI) in detail. (Nov 08, Nov 05, Nov 06, May 12,
May 08) (U)
2. Explain the operating modes and control word format of 8255. (Nov 12)(AZ)
3. Explain the block diagram of 8251(serial Communication) in detail (May 10, May 06, May
07) (U)
4. Explain the control word format of 8251. (May 10, May 06, May 12, Nov 11) (AZ)
5. Explain the block diagram of 8253(timer) with control word and also explain the
Operating modes with timing diagram. (May 10, Nov 08, May 12, Nov 10, Nov 11) (AZ)
6. Explain the block diagram of 8279(Keyboard/display) in detail. (Nov 07, May 05, Nov
08, Nov 11, May 13) (AZ)
7. Explain the block diagram of 8259(PIC) in detail. (May 10, May 06, May 12, Nov 10, May
08, May 07, Nov 11) (U)
8. Explain the block diagram of 8237(DMA) in detail. (Nov 07, May 06, Nov 10, May12, May
08, May 07, May 12) (U)
9. Explain the (i) modes of operation of timer (ii) operation of interrupt controller. (May 13) (U)
10. Explain the parallel communication interface with the microprocessor. (Nov 12) (U)
11. Draw the functional block diagram and control word format of 8254 programmable
Interval timer and its mode of operation and explain. (May 10, May 12). (U)
12. Explain in detail about 8237 DMA controller with a neat block diagram. (May 11) (U)
13. Explain the four modes of keyboard operation in 8279. (Nov 10) (AZ)
14. Explain the mode 0 operation of programmable peripheral interface. (May 2014) (AZ)
15. Explain the different modes of operation of a timer. (May 2014) (AZ)
16. Explain the internal architecture of 8237 Direct Memory Access controller. (May 2014) (U)

1.20
 UNIT – IV MICROCONTROLLER

Part – A
1. What is Microcontroller?(R)

Microcontroller incorporates all the features that are found in microprocessor with the
added features of in-built ROM, RAM, Parallel I/O, Serial I/O, counters and clock circuit to
make a micro computer system on its own.

2. What are the alternate functions of Port 3 in 8051 microcontroller?(R)

P3.0-RXD
P3.1-TXD
P3.2-INT0
P3.3-INT1
P3.4-T0
P3.5-T1
P3.6-WR
P3.7-RD

3. What is the function of SM2 bit present in SCON register in 8051?(R)

 SM2 enables the multiprocessor communication feature in modes 2 and 3. If SM2 = 1,

RI will not be activated if the received 9th data bit (RB8) is 0.
 In mode 1, if SM2 = 1, RI will not be activated if a valid stop bit was not received.
 In mode 0, SM2 should be 0.

4. If a 12 MHz crystal is connected with 8051, how much is the time taken for the count in
timer 0 to get incremented by one?(R)

Baud rate = oscillator frequency/12

= (12 Χ 106) / 12
=1 Χ 106 Hz
T = 1/f
= 1 / (1 Χ 106 )
= 1 μ sec

5. What is the advantage of microcontroller over microprocessor?(R)

 The overall system cost is low, as the peripherals are integrated in a single chip.
 The size is very small
 The system is easy to troubleshoot and maintain.
 If required additional RAM, ROM and I/O ports may be interfaced.
 The system is more reliable.

6. What is the function of IP register in 8051?(R)

The IP register is used to set high priority to one or more interrupts in 8051.

- - - PS PT1 PX1 PT0 PX0

1.21
 Setting a bit to 1 makes the corresponding interrupt to have high priority and setting a bit
to 0 makes the corresponding interrupt to have low priority.

7. What is the importance of special function registers(SFR) in 8051?(R)

The 8051 operations that do not use the internal 128 byte RAM address from 00 H to 7F
H are done by a group of special internal registers called SPFs(Special Function Registers)
Which have address between 80 H and FF H.

8. Define baud rate. (R)

Baud rate is used to indicate the rate at which data is being transferred .
Baud rate = 1/Time for a bit cell.

9. Name any 4 additional hardware features available in 8051 when compared to

microprocessor. (R)

ROM, RAM, Parallel I/O, Serial I/O, Counters, and a clock circuit are available.

10. What is the function of DPTR register? (R)

The data pointer register (DPTR) is the 16 bit address register that can be used to fetch
any 8 bit data from the data memory space. When it is not being used for this purpose, it can be
used as two eight bit registers, DPH and DPL.

11. What are the features of 8051 microcontroller? (R)

 8 bit CPU with registers A and B

 16 bit PC and DPTR
 8 bit PSW
 Internal ROM of 4KB
 Internal RAM of 128 bytes
 Two 16 bit timers and counters: T0 and T1
 Two external and three internal interrupts
 32 input / output pins arranged as four 8 bit ports: Port0, port1, port2 and port3.
 Control registers are: TMOD, TCON, SCON, PCON, IP and IE.

12. List any applications of microcontroller.(R)

 Industrial control (process control)
 Motor speed control(stepper motor control)
 Peripheral devices(printer)
 Stand alone devices(colour Xerox machine)
 Automobile applications(power steering)
 Home applications (washing machine)
 Length measurement
 Square wave generator

1.22
13. Explain the instruction: SWAP. (E)

SWAP instruction works only on the accumulator (SWAP A) . It swaps the lower nibble and
higher nibble .The lower 4 bits are put into the higher 4 bits and the higher 4 bits are put into the
lower 4 bits.
E.g. - SWAP A
ACC
Before execution: 1111 0000
After execution: 0000 1111

15. Explain the PUSH and POP instruction in 8051?

PUSH direct: (sp)  (SP) + 1

((SP)) (Direct)
The SP is incremented by 1. The content of the indicated register is then copied to the internal
RAM location addressed by SP.
POP direct: (direct)  ((SP))
(SP)  (SP) – 1
The content of the internal RAM location addressed by SP is read , and SP is decremented by
one . The value is then transferred to the directly addressed byte indicated.

16. How does 8051 differentiate between the external and internal program memory?(AZ)

S.NO EXTERNAL PROGRAM INTERNAL PROGRAM MEMORY

MEMORY
1 EA pin is high EA pin is grounded
2. PSEN signal is activated PSEN is grounded
3. 8051 can address up to 64 KB of 4KB of internal program memory is
External program available
memory
4. Accessible by only direct and indirect Accessible by all addressing modes
addressing modes.

17. What is the maximum frequency of the clock signal that can be counted by 8051
counter? (R)

The maximum frequency of the clock signal is 1/12th of the oscillator frequency.

18. What are the two memory address pointers in 8051 microcontroller? (R)

Program counter and Data Pointer are the two memory address pointers in 8051. The
program instruction bytes are fetched from the locations in memory that are addressed by the
PC. The DPTR register is made up of two 8 bit registers named DPH and DPL, which are used
to furnish memory address for internal and external code access and external data access.

1.23
19. Give the PSW setting for register bank 2 as default bank in 8051 microcontroller.
(Apr 2010, Apr 2013) (R)

20. What is the difference between timer and counter operation in 8051?(AZ)
The timer counts the internal clock pulses whose frequency is 1/12 th of oscillator
frequency .The counter counts the internal clock pulses which are given through T0 pin (for
counter 0) and T1 pin (for counter 1) of 8051.

21. What happens in power down mode of 8051 microcontroller? (R)

The memory locations of power down RAM can be maintained through a separate small
battery backup supply so that the content of these RAM can be preserved during power failure
conditions.

22. What are the difference between a microprocessor and microcontroller? (Nov/Dec
2011, May 2014) (AZ)

Sl.No Microprocessor Microcontroller

Microprocessor contains Microcontroller contains the circuitry of
ALU,general purpose registers,stack microprocessor and in addition it has built-
1
pointer, program counter, clock in ROM, RAM, I/O devices, timers and
timing circuit and interrupt circuit. counters.
It has many instructions to move data It has one or two instructions to move data
2
between memory and CPU. between memory and CPU.
It has one or two bit handling It has many bit handling instructions.
3
instructions.
Access times for memory and I/O Less access times for built-in memory and
4
devices are more. I/O devices.
Microprocessor based system Microcontroller based system requires less
5 requires more hardware. hardware reducing PCB size and
increasing the reliability.

1.24
23. How does the status of EA pin affect the access to internal and external program
memory? (R)
EA- Enable Interrupt bit. Cleared to 0 by program to disable all interrupts , set to 1 to
permit individual interrupts to be enabled by their enabled bits . It is set to access data from
external memory or else it is grounded for internal memory operations.

24. What are the register banks in 8051 microcontroller? (R)

The 32 registers are arranged as part of the internal RAM in 4 banks : bank 0 , bank 1,
bank 2 and bank 3, each of eight registers.

25. State the function of RS1 and RS0 bits in the flag register of intel 8051
microcontroller? [MAY/JUNE 2013,nov/dec 2011] (R)
RS1, RS0 – Register bank select bits

RS1 RS0 Bank Selection

0 0 Bank 0
0 1 Bank 1
1 0 Bank 2
1 1 Bank 3

26. Give the alternate functions for the port pins of port3? (R)

RD WR T1 T0 INT1 INT0 TXD RXD

RD – Read data control output.

WR – Write data control output.
T1 – Timer / Counter1 external input or test pin.
T0 – Timer / Counter0 external input or test pin.
INT1- Interrupt 1 input pin.
INT 0 – Interrupt 0 input pin.
TXD – Transmit data pin for serial port in UART mode.
RXD - Receive data pin for serial port in UART mode.

27. Explain the function of the pins PSEN and EA of 8051. (U)

PSEN :
PSEN stands for program store enable. In 8051 based system in which an
external ROM holds the program code, this pin is connected to the OE pin of the ROM.
EA :
EA stands for external access. When the EA pin is connected to Vcc, program
fetched to addresses 0000H through 0FFFH are directed to the internal ROM and program
fetches to addresses 1000H through FFFFH are directed to external ROM/EPROM. When the
EA pin is grounded, all addresses fetched by program are directed to the external
ROM/EPROM.

28. Explain the 16-bit registers DPTR and SP of 8051. (R)

DPTR:
DPTR stands for data pointer. DPTR consists of a high byte (DPH) and a low byte
(DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-bit data register or
1.25
as two independent 8-bit registers. It serves as a base register in indirect jumps, lookup table
instructions and external data transfer.

SP:
SP stands for stack pointer. SP is a 8- bit wide register. It is incremented before data is
stored during PUSH and CALL instructions. The stack array can reside anywhere in on-chip
RAM. The stack pointer is initialized to 07H after a reset. This causes the stack to begin at
location 08H.

29. Name the special functions registers available in 8051. (R)

a. Accumulator
b. B Register
c. Program Status Word.
d. Stack Pointer.
e. Data Pointer.
f. Port 0
g. Port 1
h. Port 2
i. Port 3
j. Interrupt priority control register.
k. Interrupt enable control register.

30. List the register set of 8051? (R)

Accumulator, B, PSW, P0, P1, P2, P3, IP, IE, TCON and SCON.

31. List the addressing modes supported by 8051? (R)

 Direct addressing
 Indirect addressing
 Register instructions
 Register specific ( Register implicit)
 Immediate mode
 Indexed addressing

32. Define direct addressing of 8051? (R)

The operands are specified using the 8bit address field in the instruction format.
Ex: MOV R0,89H
89H is the address of a special function register TMOD.

33. Discuss about the indirect addressing of 8051? (R)

The 8bit address of an operand is stored in a register and the register instead of the 8bit
address is specified in the instruction. Ex: ADD A,@R0

34. Write about the register instructions of 8051? (R)

In this addressing mode, the operands are stored in the registers R0 – R7 of the selected
register bank.
Ex: ADD A, R7
1.26
35. Write about the register specific instructions of 8051? (R)

In this type of instructions, the operand is implicitly specified using one of the registers.
Some of the instructions always operate on a specific register.
Ex: RLA – Rotate left the accumulator

36. What are the types of register set available in 8051? (R)

 Bit addressable registers

 Byte addressable registers

37. List the registers available in 8051? (R)

8051 has twenty one 8bit, bit addressable registers.

Bit addressable registers – A, B, PSW, P0, P1, P2, P3, IP, IE, TCON & SCON
Byte addressable registers – SP, DPH, DPL, TMOD, TH0, TH1, TL0, TL1, SBUF, PCON.

38. What is the significance of EA line of 8051 microcontroller? [May 2014] (R)

The External Access (EA) line at pin 31 is used when the part is first powered up to
determine whether the program will be executed from external code memory or from internal
code memory.
If EA is tied high (connected to +5V) the microcontroller executes first the program from built-
in ROM, then the program stored in external memory.
If EA is tied low (to ground) then the microcontroller completely ignores internal program
memory and executes only the program stored in external memory.

39. List the I / O ports available in 8051? (R)

 Port0
 Port1
 Port2
 Port3

PART B & C

1. Explain the architecture of 8051 microcontroller with neat block diagram. (U)
(Nov 07,May 07,Nov 05,Nov 08,Nov 06,May 06, May 08,May 12)
2. Draw and explain the pin configuration of 8051. (R & U) (May 08, Nov 11)
3. Explain the I/O port structure of 8051. (May 12) (U)
4. How a program and data memory is interfaced with 8051?(May 12) (R)
5. Briefly explain about 8051 addressing modes. (R &U)
6. Explain about instruction set of 8051.(U)
7. Discuss about the Special Function Registers (SFRs) of 8051.(C)
8. Describe briefly various registers in 8051 microcontroller. (May 11,Nov 11) (A)
9. Explain the features of 8051 and compare it with 8086. (May 11) (U)
10. Discuss the functions of signals present in 8051. (May 13) (C)
11. Draw the pin diagram of 8051 microcontroller and explain the Input / Output lines in
Detail. (May 14) (R &U)

1.27
 UNIT – V INTERFACING MICROCONTROLLER

Part – A

1. Name the interrupts of 8051 microcontroller. (R)

External interrupt-0 , External interrupt-1,Timer-0 interrupt, Timer-1 interrupt, and
serial port interrupt.

2. What is the job of the TMOD register? (R)

TMOD (timer mode) register is used to set the various timer operation modes . TMOD
is dedicated to the two timers (Timer0 and Timer1) and can be considered to be two duplicate 4
bit registers, each of which controls the action of one of the timers

3. What are the bits available in TMOD register? (R)

GATE C/T M1 M0 GAT C/T M1 M0
E
TIMER 1 TIMER 0

M1 M0 Mode
0 0 0 (13 bit Timer Mode)
0 1 1 (16 bit Timer Mode)
1 0 2 (8 bit auto reload)
1 1 3 (split Timer Mode)
GATE: Gating control when set
C/T : Timer or counter selection; 1= counter , 0= Timer.

4. What are the timers available in 8051? (R)

 Timer 0
 Timer 1
Each 16 bit timer is accessed as two separate 8 bit registers : Low byte register(TL) and High
byte register (TH).

5. What are the external hardware interrupts in 8051? (R)

INT0 - External hardware interrupt 0
INT1 - External hardware interrupt 1

6. What is the interrupt priority in 8051 ? and write its vector address(R)
SEQUENCE ADDRESS
PRIORITY INTERRUPTS
Highest priority - External interrupt - 0 (INT 0) - 0003 H
Timer interrupt - 0 (TF 0) - 000B H
External interrupt - 1 (INT 1) - 0013 H
Timer interrupt - 1 (TF 1) - 001B H
Lowest priority - serial communication (RI,TI) - 0023 H

7. When 8051 is reset, all interrupts are disabled. How to enable these interrupts? (R)
Each of the interrupts sources can be individually enabled or disabled by setting or
clearing a bit in the Special Function Register IE . IE also has a global disable bit, which
disables all interrupts at once.

1.28
8. What is nested interrupts? (R)
The 8051 is executing an ISR for servicing an interrupt and another interrupt occurs. If
the new coming interrupt is high priority then only it can interrupt the previously occurred low
priority interrupt. These are called nested interrupts.

9. Give steps to program 8051 for serial data transfer. (R)

The 8051 has a serial data communication circuit that uses register SBUF to hold data.
Register SCON controls data communication, register PCON controls data rates, and pins RXD
(P3.0) and TXD (P3.1) connect to serial data network.

10. What is the significant of GATE in TMOD control register? (R)

It is OR gate enable bit which controls RUN/STOP of timer 1/0.
Timer/ Counter is enabled while TR 1/0 in TCON is set and signal on external interrupt INT1/0
pin is high. Cleared to 0 by program to enable timer to run, if bit TR1/0 in TCON is set.

11. What is the asynchronous data transmission format of 8051 serial port? (R)
Receiver samples data in centre of bit time

Idle state
1 2 3 4 5 6 7 8

Start bit  Data Bits Minimum of one stop bit

Bit time = 1/f t 

12. Write down the different operating modes for serial communication of 8051. (R)
Serial communication of 8051 operates under four modes. They are mode 0 , mode 1,
mode 2 and mode3 .SM0 and SM1 bits of SCON register specifies the mode.

Part – B & C

1. Explain the operating modes of timer/counter in 8051. (May 12, May 08, May 10) (R &U)
2. Explain how the serial communication is performed in 8051. (May 06) (R &U)
3. Explain the Interrupt structure of 8051. (Nov 08, Nov 06, Nov 10, May 12) (R &U)
4. With a neat circuit diagram explain how a 4*4 Keyboard is interfaced with 8051
Microcontroller and write 8051 ALP for keyboard scanning. (May 12) (R &U)
5. Explain the interfacing of LCD display with 8051 in detail.(May 12, May 10, Nov 12) (R
&U)
6. Explain the interfacing of ADC with 8051 with neat block diagram. (May 10, Nov 10) (R
&U)
7. Explain the interfacing of DAC with 8051 with neat block diagram. (May 11, May 13) (R
&U)
8. Develop an 8051 assembly language program to transfer the letter ‘A’ serially with 4800
Baud, 1stop bit continuously. (C)
10. Explain the on-chip timer modes of 8051. (May 10) (R &U)
11. How to transfer data between a PC and microcontroller using serial communication?
Draw the necessary diagrams and explain. (R &U) (Nov 12)
12. What is timer/counter? Explain 16-bit timer mode and 8-bit auto reload mode of 8051.
(Nov 12) (R &U)
13. Explain how LCD and keyboard is interfaced with 8051. (May 13) (R &U)
14. Describe about serial port interface of 8051. (U) (May 13)
15. Explain the different techniques to convert a digital quantity into its equivalent analog
quantity. (May 2014) (R &U)

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 ASSIGNMENT QUESTIONS BASED ON BLOOM’S TAXONOMY LEVELS (BTL)

UNIT-I THE 8086 MICROPROCESSOR

ASSIGNMENT -I
Q. No Question BTL
PART A
1. Write an ALP to generate a delay of 1 sec using a microprocessor running at 5 U
MHZ. Also show the delay calculations.
2. To find the factorial of a number. C
PART B & C
3. Develop an ALP using 8086 instructions to convert upper case letter in to a C
lower case letter and lower case letter in to a upper case letter.

UNIT-II 8086 SYSTEM BUS STRUCTURE

ASSIGNMENT -II
Q. No Question BTL
PART A
1. Bring out the differences between memory mapped I/O and I/O mapped I/O. AZ
2. Name the four different ways of passing parameters in 8086 microprocessor to a R
procedure in assembly language.
PART B & C
3. Explain in detail the stack structure of 8086.Write a simple program to illustrate U
the concept of programming the stack.

UNIT-III I/O INTERFACING

ASSIGNMENT -III
Q. No Question BTL
PART A
1. List the functions performed by 8279. R
2. What are the signals normally handled in ADC interfacing. R
PART B & C
3. Explain the interfacing of alphanumeric displays to microprocessors. U

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 UNIT-IV MICROCONTROLLER
ASSIGNMENT -IV
Q. No Question BTL
PART A
1. Multiply two 8 bit numbers. U
2. What are the functions of EA (low) and ALE. R
PART B & C
3. Explain about an interfacing of servomotor with 8051. U

UNIT-V INTERFACING MICROCONTROLLER

ASSIGNMENT -V
Q. No Question BTL
PART A
1. List any two applications of microcontroller. R
2. Mention the hardware requirement to interface an LCD using 8255. R
PART B & C
3. Develop a program to display “Engineer” on LCD on 8 X 1. AZ

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