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Tutorial Exercises

This document provides instructions for completing four exercises using the Dynamatic tutorial. It describes synthesizing code samples using Dynamatic and simulating the resulting circuits in ModelSim. The exercises illustrate Dynamatic's basic features, buffers, load store queues, and modifying the tool flow. Additional questions are provided for each exercise to analyze the outputs and waveforms. Tips for using ModelSim to view the simulations are also included.

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Srijeet Guha
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© © All Rights Reserved
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14 views

Tutorial Exercises

This document provides instructions for completing four exercises using the Dynamatic tutorial. It describes synthesizing code samples using Dynamatic and simulating the resulting circuits in ModelSim. The exercises illustrate Dynamatic's basic features, buffers, load store queues, and modifying the tool flow. Additional questions are provided for each exercise to analyze the outputs and waveforms. Tips for using ModelSim to view the simulations are also included.

Uploaded by

Srijeet Guha
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Dynamatic Tutorial: Exercise Instructions

Exercises 1, 2, and 3: Using Dynamatic


This part of the Dynamatic tutorial contains three exercises which illustrate the basic features and usage of Dyna-
matic on a toy example. The exercises are located in the following folders:
– Exercise 1: tutorial/1-example-naive
– Exercise 2: tutorial/2-example-buffers
– Exercise 3: tutorial/3-example-lsq
For all three exercises, follow the five steps below. Each exercise has additional questions in the following section.
1) Open a terminal and set the appropriate exercise folder as the working directory. For Exercise 1:
cd tutorial/1-example-naive
2) Consider the code in src/example.cpp and the Dynamatic commands in synthesis.tcl. Use this script to
synthesize the example function into a dataflow circuit:
dynamatic synthesis.tcl
3) Study the DOT, PNG, and VHDL outputs of Dynamatic in folders reports and hdl.
4) Simulate the design using ModelSim:
vsim -do simulation.tcl
Study the waveforms and note the total execution time. Refer to the next page for tips on using ModelSim.
5) Check the correctness of the circuit by comparing the simulation results with the software results:
meld sim/C OUT/output a.dat sim/VHDL OUT/output a.dat
For details on the compiler commands and the output files, please refer to the Dynamatic tutorial paper.

Exercises 1, 2, and 3: Additional Questions


Exercise 1*. All questions refer to the outputs of Exercise 1 in tutorial/1-example-naive.
a) In example.png, consider the buffer buffI 0. In the waveform, find the input and output signals of this
buffer. What do the values stored in this buffer (i.e., values of buffI 0 dataOutArray 0) correspond to? Find
a point in the simulation when the buffer is stalled by its successor (i.e., signal buffI 0 nReadyArray 0 is set
to zero while the buffer produces valid data and buffI 0 validArray 0 is set to 1).
b) In example.png, consider component icmp 15. Find a point in the simulation where the loop condition (i.e.,
i < 100) evaluates to false (i.e., icmp 15 dataOutArray 0 returns from value 1 to value 0).
c) In example.png, consider component branch 1. In the simulation, investigate how the change of the condi-
tion value from true to false affects the validity of the Branch outputs (i.e., signals branch 1 validArray 0
and branch 1 validArray 1).
Exercise 2*. All questions refer to the outputs of Exercise 2 in tutorial/2-example-buffers.
a) In example optimized.png, find all buffers and investigate their size and transparency (values provided
in squared brackets for each buffer; for instance, Buffer 1[2] indicates a 2-slot nontransparent buffer and
Buffer 2[2t] indicates a 2-slot transparent buffer).
b) In example optimized.png, consider the buffer Buffer 1. In the waveform, find the input and output
signals of this buffer. Check if, at any point in the simulation, the buffer is stalled by its successor (i.e., signal
Buffer 1 nReadyArray 0 is set to zero while the buffer produces valid data and Buffer 1 validArray 0
is set to 1).
c) In the simulation, locate the read-after-write hazard between loop iterations 4 and 5. The load of iteration 5
occurs at 42 ns and the store of iteration 4 at 58 ns. The read and write address are named a address1 and
a address0, respectively.
Exercise 3*. All questions refer to the outputs of Exercise 3 in tutorial/3-example-lsq.
a) In example optimized.png, locate the new LSQ component and study its inputs and outputs. Note that only
the load (load 7) and store (store 0) to array a are connected to the LSQ, whereas the other loads connect to
separate memories.
b) Check if the read-after-write dependency between iterations 4 and 5 is honoured. The load receives the read
data (signal load 7 dataInArray 0) of iteration 5 at 82 ns. The store writes the data of iteration 4 to memory
at 74 ns. Write address and data are named a address0 and a dout0, respectively.
1
7

4 2

Figure 1: ModelSim.

Exercise 4: Modifying the Dynamatic Flow


This part of the tutorial illustrates some possibilities for modifying the Dynamatic flow (i.e., integrating new VHDL
components and changing the intermediate representation). All questions refer to the files in tutorial/4-example-mul.

a) Synthesize and simulate example mul.cpp as in the previous exercises. Note the simulation execution time.
b) In hdl/mul wrapper.vhd, replace the 4-stage multiplier with an 8-stage multiplier by changing the multiplier
entity from work.mul 4 stage to work.mul 8 stage. In the same file, change the LATENCY constant to
reflect the component latency change. Simulate the design and compare the execution time to the prior one.
c) Integrate the information about the new multiplier into the Dynamatic flow:
– Invoke the Dynamatic shell using the command dynamatic and type manually the commands from
synthesis.tcl to set up the project and synthesize the design (i.e., all commands up to optimize).
– Before invoking the optimize command, in reports/example mul.dot, update the latency field of mul-
tiplier mul 8 to reflect the latency change.
– Run the remaining commands from synthesis.tcl to place buffers and produce the VHDL netlist.
– Repeat the steps from question 4b to replace the multiplier in hdl/mul wrapper.vhd.
Simulate the design, note the total execution time, and compare it from the one from the previous questions.

Using ModelSim
To complete the exercises, use the ModelSim features described in this section and depicted in Figure 1.

– After running the simulation.tcl script, wait for the simulation to complete; a green text line will appear
in the Transcript window (marked with number 1 in the figure), indicating simulation break.
– Extend the waveform across the entire screen by clicking on the undock button (number 2).
– To change the number format of a signal from binary to unsigned, right-click on the signal name (e.g., number
3) and choose Radix > Unsigned.
– Zoom in/out of the waveforms using the zoom in/out buttons (number 4).
– Scroll through simulation time using the horizontal bar (number 5) and through signals using the vertical bar
(number 6).
– Search for a signal by name using the find button (number 7).

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