VLSI DESIGN LAB (7EC4-21)

LAB MANUAL

Lab Name : VLSI Design Lab

Lab Code : 7S8A

Branch : Electronics and Communication Engineering

Year : 4th Year

Jaipur Engineering College and Research Center, Jaipur

Electronics and Communication Engineering
(Rajasthan Technical University, KOTA)

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 VLSI DESIGN LAB (7EC4-21)
INDEX

S.NO CONTENTS CO PAGE

NO.

1 VISION/MISION 4

2. PEO 4

3. POS 5

4. COS 6

5. MAPPING OF CO & PO 6

6. SYLLABUS 7

7. BOOKS 8

8. INSTRUCTIONAL METHODS 8

9. LEARNING MATERIALS 8

10. ASSESSMENT OF OUTCOMES 9

LIST OF EXPERIMENTS (RTU SYLLABUS)

Exp:- 1 Objectives: - Design and Simulate all the Logic gates with two inputs using
Verilog/VHDL.

Exp:- 2 Objectives :- Design and Simulate 2-to-4 decoder,3-8 decoder & 4*1
multiplexer using VHDL/ Verilog.

Exp:-3 Objectives :- . Design and Simulate half Adder & Full Adder using VHDL
(Data flow Methood)/Verilog.

Exp:-4
Objectives: - . Design and Simulate D, T & JK Flip-flop using VHDL/
Verilog.
Exp:-5 Objectives: - Design a 4 bit binary Asynchronous Counter. Obtain its
number of gate, area and speed.

LAB MANUAL (VII SEMECE) Page8

 VLSI DESIGN LAB (7EC4-21)
Exp:-6 Objectives: - Design a 4bit Serial in Serial out Shift register. Obtain its
number of gate, area and speed.

PART-2 1) Design and Simulate following experiment using ECAD Software

Viz.Orcade, PSpice Cadence.

2) Draw of layout of the Schematic diagram obtain 1 and post layout

simulation using ECAD Software.

Exp:-1 Objectives: -. Design and Simulate all logic gates with 2 inputs CMOS
Technology.

Exp:-2 Objectives: Design and Simulate 4*1 Multiplexer.

Exp:-3 Objectives: - Design and Simulate Half Adder and Full Adder using CMOS
Technology.
Exp:4 Objectives: Design and Simulate SR Flip-flop using CMOS Technology.

Exp:5 Objectives: Design and Simulate any DRAM Cell.

JAIPUR ENGINEERING COLLEGE AND RESEARCH CENTER

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 VLSI DESIGN LAB (7EC4-21)
Department of Electronics and Communication Engineering

Branch: Electronics and Communication Engineering Semester: VII th

Course Name: VLSI Design Lab Code: 7ECA

External Marks: 45 Practical hrs: 3 hr/week

Internal Marks: 30 Total Marks: 75

• VISION & MISSION

VISION: To become renowned Centre of excellence in computer science and engineering and
make competent engineers & professionals with high ethical values prepared for lifelong
learning.

MISSION:

M1: To impart outcome based education for emerging technologies in the field of
computer science and engineering.
M2: To provide opportunities for interaction between academia and industry.
M3: To provide platform for lifelong learning by accepting the change in technologies
M4: To develop aptitude of fulfilling social responsibilities

PEO

1. To provide students with the fundamentals of Engineering Sciences with more emphasis in
Computer Science &Engineering by way of analyzing and exploiting engineering challenges.
2. To train students with good scientific and engineering knowledge so as to comprehend,
analyze, design, and create novel products and solutions for the real life problems.
3. To inculcate professional and ethical attitude, effective communication skills, teamwork skills,
multidisciplinary approach, entrepreneurial thinking and an ability to relate engineering issues
with social issues.
4. To provide students with an academic environment aware of excellence, leadership, written
ethical codes and guidelines, and the self motivated life-long learning needed for a successful
professional career.
5. To prepare students to excel in Industry and Higher education by Educating Students along
with High moral values and Knowledge

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 VLSI DESIGN LAB (7EC4-21)
1. PROGRAM OUTCOMES
1. Engineering Knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering
problems in IT.
2. Problem analysis: Identify, formulate, research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences in IT.
3. Design/development of solutions: Design solutions for complex engineering problems
and design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and
environmental considerations using IT.
4. Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data, and
synthesis of the information to provide valid conclusions using IT.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations in IT.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice using IT.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development in IT.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice using IT.
9. Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings in IT.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations, and give
and receive clear instructions.
11. Project Management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member
and leader in a team, to manage IT projects and in multidisciplinary environments.
12. Life –long Learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological
changes needed in IT.

4. MAPPING OF PEOs & Pos

PROGRAM PROGRAM OUTCOMES
OBJECTIVES
1 2 3 4 5 6 7 8 9 10 11 12

I H L H

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 VLSI DESIGN LAB (7EC4-21)
II M H M H H L H

III L H M H L M

IV L M H M H M

V M M

5. COURSE OUTCOMES
Graduates would be able:
CO1: Implementing the canonical form inter conversion through programming
CO2:Implementing the graphical sequencing and coloring algorithm through
programming.
CO3:Implementing decision tree concept using programming logic.
CO4:Implementing Hardware modeling of logic gates and combinational digital
circuits using VHDL
6. MAPPING OF CO & PO
VLSI LAB

POs
1 2 3 4 5 6 7 8 9 10 11 12
COs

1 H H H - M - - - H H M M

2 H H H M M - - - H H M M

3 H H H M H - - - H H H H

4 H H H H H M - - H H H H

7. SYLLABUS

7CS8A VLSI PHYSICAL DESIGN LAB

Class: VII Sem. B.Tech. Evaluation

Branch: Computer Engg. Examination Time = Four (4) Hours

Schedule per Week Maximum Marks = 75

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 VLSI DESIGN LAB (7EC4-21)
Practical Hrs : 3 [Sessional/Mid-term (45) & End-term (30)]

VLSI Physical Design Automation is essentially the research, development and productization of
algorithms and data structures related to the physical design process. The objective is to investigate optimal
arrangements of devices on a plane (or in three dimensions) and efficient interconnection schemes between
these devices to obtain the desired functionality and performance. Since space on a wafer is very expensive
real estate, algorithms must use the space very efficiently to lower costs and improve yield. In addition, the
arrangement of devices plays a key role in determining the performance of a chip. Algorithms for physical
design must also ensure that the layout generated abides by all the rules required by the fabrication process.
Fabrication rules establish the tolerance limits of the fabrication process. Finally, algorithms must be
efficient and should be able to handle very large designs. Efficient algorithms not only lead to fast turn-
around time, but also permit designers to make iterative improvements to the layouts. The VLSI physical
design process manipulates very simple geometric objects, such as polygons and lines. As a result, physical
design algorithms tend to be very intuitive in nature, and have significant overlap with graph algorithms
and combinatorial optimization algorithms. In view of this observation, many consider physical design
automation the study of graph theoretic and combinatorial algorithms for manipulation of geometric objects
in two and three dimensions. However, a pure geometric point of view ignores the electrical (both digital
and analog) aspect of the physical design problem. In a VLSI circuit, polygons and lines have inter-related
electrical properties, which exhibit a very complex behavior and depend on a host of variables. Therefore,
it is necessary to keep the electrical aspects of the geometric objects in perspective while developing
algorithms for VLSI physical design automation. With the introduction of Very Deep Sub-Micron
(VDSM), which provides very small features and allows dramatic increases in the clock frequency, the
effect of electrical parameters on physical design will play a more dominant role in the design and
development of new algorithms.

(Source: Algorithms For VLSI Physical Design Automation, by Naveed A. Sherwani, Concept of CMOS
Technology by Cobang.).

The exercise should be such that the above objectives are met.

Automation tools such as Synopsis/ Cadence are available in the area. However, to begin, the students shall
be assigned exercises on route optimization, placement & floor planning. Small circuits may be taken &
algorithms implemented. At a later stage, the students may use tools and design more complex circuits.

LAB MANUAL (VII SEMECE) Page1

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 VLSI DESIGN LAB (7EC4-21)

Department of Electronics and Communication Engineering

Branch: Electronics and Communication Engineering Semester: VII th

Course Name: VLSI Physical Design Lab Code: 7CS8A

External Marks: 45 Practical hrs: 3 hr/week

Internal Marks: 30 Total Marks: 75

Learning Outcomes: At the end of this Lab Students will able to

 VHDL/Verilog Coding in different style & Code ( Data flow, Behavioral) for
Basic Gate, Multiplexer, Encoder, Decoder, Flip –Flop.

 Learn about CMOS technology.

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 VLSI DESIGN LAB (7EC4-21)
 Learn ECAD Software (OrCad, PSpice, Cadence) and their Simulation
Technique.

 Learn how to Simulate Circuit using Cadence.

8. BOOKS:-

8.1 Text books:-

1 S.H. Gerez. Algorithms VLSI Design Automation. Wiley India. (Indian edition
available.)

2. Michael John Sebastian Smith. Application-Specific Integrated Circuits.

Addison-Wesley. (Low-priced edition is available.)

3. G.D. Micheli, Synthesis and optimization of digital circuits, TMH.

8.2 Reference Books:-

1. http://www.fie-conference.org/fie98/papers/1002.pdf

2. S. Sait and H. Youssef. VLSI Physical Design Automation: Theory and Practice.

9. INSTRUCTIONAL METHODS:-
9.1. Direct Instructions:

• White board presentation Using Zoom.

9.2. Interactive Instruction:

• coding

9.3 .Indirect Instructions:

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 VLSI DESIGN LAB (7EC4-21)
• Problem solving and Quiz.

10. LEARNING MATERIALS:-

9.1. Text/Lab Manual

11 ASSESSMENT OF OUTCOMES:-

1. End term Practical exam (Conducted by RTU, KOTA)

2. Daily Lab interaction.

12. OUTCOMES WILL BE ACHIEVED THROUGH FOLLOWING:-

1. Lab Teaching (through Veido).

2. Discussion on website work

INSTRUCTIONS OF LAB

DO’s
• Please switch off the Mobile/Cell phone before entering Lab.
• Enter the Lab with complete source code and data.
 Check whether all peripheral are available at your desktop before proceeding for
program.
• Intimate the lab In charge whenever you are incompatible in using the system
or in case software get corrupted/ infected by virus.
• Arrange all the peripheral and seats before leaving the lab.
• Properly shutdown the system before leaving the lab.
• Keep the bag outside in the racks.
• Enter the lab on time and leave at proper time.
• Maintain the decorum of the lab.
• Utilize lab hours in the corresponding experiment.
• Get your Cd / Pen drive checked by lab In charge before using it in the lab.

DON’TS
• No one is allowed to bring storage devices like Pan Drive /Floppy etc. in the lab.
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 VLSI DESIGN LAB (7EC4-21)
• Don’t mishandle the system.
• Don’t leave the system on standing for long
• Don’t bring any external material in the lab.
• Don’t make noise in the lab.
• Don’t bring the mobile in the lab. If extremely necessary then keep ringers off.
• Don’t enter in the lab without permission of lab Incharge.
• Don’t litter in the lab.
• Don’t delete or make any modification in system files.
• Don’t carry any lab equipments outside the lab.
We need your full support and cooperation for smooth functioning of the

INSTRUCTIONS FOR STUDENT

BEFORE ENTERING IN THE LAB

• All the students are supposed to prepare the theory regarding upcoming Lab.
• Students are supposed to bring the practical file and the lab copy.
• Previous programs should be written in the practical file.
• Any student not following these instructions will be denied entry in the lab.

WHILE WORKING IN THE LAB

• Adhere to experimental schedule as instructed by the lab incharge.
• Get the previously executed program signed by the instructor.
• Get the output of the current program checked by the instructor in the lab copy.
• Each student should work on his/her assigned computer at each turn of the lab.
• Take responsibility of valuable accessories.
• Concentrate on the assigned practical and do not play games.
• If anyone caught red handed carrying any equipment of the lab, then he will have to face
serious consequences.
MARKING/ASSESSMENT SYSTEM

Total marks -10

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 VLSI DESIGN LAB (7EC4-21)
Distribution of marks:

Attendance Records Performance viva

2 3 3 2

INSTRUCTIONS FOR STUDENT

BEFORE ENTERING IN THE LAB

 All the students are supposed to prepare the theory regarding the next program.
 Students are supposed to bring the practical file and the lab copy.
 Previous programs should be written in the practical file.
 Any student not following these instructions will be denied entry in the lab.

WHILE WORKING IN THE LAB

 Adhere to experimental schedule as instructed by the lab incharge.
 Get the previously executed program signed by the instructor.
 Get the output of the current program checked by the instructor in the lab copy.
 Each student should work on his/her assigned computer at each turn of the lab.
 Take responsibility of valuable accessories.
 Concentrate on the assigned practical and do not play games.
 If anyone caught red handed carrying any equipment of the lab, then he will have to
face serious consequences.

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 VLSI DESIGN LAB (7EC4-21)

EXPERIMENT No. 1

Aim:- Design of Half adder, Full adder.

Half adder

A half adder is a logical circuit that performs an addition operation on two one-bit
binary numbers often written as A and B.
The half adder output is a sum of the two inputs usually represented with the
signals Cout and S where

Following is the logic table and circuit diagram for half adder:

Inputs Outputs

A B C S

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.V Components.all;

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 VLSI DESIGN LAB (7EC4-21)
entity ha is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end ha;

architecture Behavioral of ha is
begin
s <= a xor b;
c <= a and b;
end Behavioral;

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 PART-B

Experiment: 1

For the design of any circuit with the CMOS technology; We need parallel or series connections
of nMOS and pMOS with a nMOS source tied directly or indirectly to ground and a pMOS
source tied directly or indirectly to Vdd. A basic CMOS structure of any 2-input logic gate can be
drawn as follows:

The above drawn circuit is a 2-input CMOS NAND gate. Now let’s understand how this circuit

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will behave like a NAND gate. The circuit output should follow the same pattern as in the truth
table for different input combinations.

Case-1 : VA – Low & VB – Low

As VA and VB both are low, both the pMOS will be ON and both the nMOS will be OFF. So the
output Vout will get two paths through two ON pMOS to get connected with V dd. The output will
be charged to the Vdd level. The output line will not get any path to the GND as both the nMOS
are off. So, there is no path through which the output line can discharge. The output line will
maintain the voltage level at Vdd; so, High.

Case-2 : VA – Low & VB – High

VA – Low: pMOS1 – ON; nMOS1 – OFF

VB – High: pMOS2 – OFF; nMOS2 – ON

pMOS1 and pMOS2 are in parallel. Though pMOS2 is OFF, still the output line will get a path
through pMOS1 to get connected with Vdd. nMOS1 and nMOS2 are in series. As nMOS1 is OFF,
so Vout will not be able to find a path to GND to get discharged. This in turn results the V out to be
maintained at the level of Vdd; so, High.

Case-3 Va High &

VA – High: pMOS1 – OFF; nMOS1 – ON

VB – Low: pMOS2 – ON; nMOS2 – OFF

The explanation is similar as case-2. Vout level will be High.

Case-4 : VA – High & VB – High

VA – High: pMOS1 – OFF; nMOS1 – ON

VB – High: pMOS2 – OFF; nMOS2 – ON

In this case, both the pMOS are OFF. So, Vout will not find any path to get connected with Vdd. As
both the nMOS are ON, the series connected nMOS will create a path from V out to GND. Since,
the path to ground is established, Vout will be discharged; so, Low.

In all the 4 cases we have observed that Vout is following the exact pattern as in the truth table for
the corresponding input combination.

2 Input NOR Gate

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TRUTH TABLE

CIRCUIT

The above drawn circuit is a 2-input CMOS NOR gate. Now let’s understand how this circuit
will behave like a NOR gate.

Case-1 : VA – Low & VB – Low

VA – Low: pMOS1 – ON; nMOS1 – OFF

VB – Low: pMOS2 – ON; nMOS2 – OFF

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Path establishes from Vdd to Vout through the series connected ON pMOS transistors and Vout gets
charged to Vdd level. No path from Vout to GND. Therefore, no discharging and hence Vout will
be High.

Case-2 : VA – Low & VB – High

VA – Low: pMOS1 – ON; nMOS1 – OFF

VB – High: pMOS2 – OFF; nMOS2 – ON

In this case path establishes from Vout to GND through nMOS2, but no path to Vdd. So, Vout would
get discharged and will be at level Low.

Case-3 : VA – High & VB – Low

VA – High: pMOS1 – OFF; nMOS1 – ON

VB – Low: pMOS2 – ON; nMOS2 – OFF

The explanation is similar as case-2. Vout will be at level Low.

Case-4 : VA – High & VB – High

VA – High: pMOS1 – OFF; nMOS1 – ON

VB – High: pMOS2 – OFF; nMOS2 – ON

No path to Vdd. Path establishes from Vout to GND. So, Vout will be at level low.

In all the 4 cases we have observed that Vout is following the expected value as in 2 input NOR
gate truth table.

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 Experiment: 2

AIM: Design and Simulate Half adder & Full adder.

Introduction

Half Adder

The simplest combinational circuit which performs the arithmetic addition of two binary digits is
known as half adder.. It is the necessary building block for designing any VLSI system It adds
two inputs and produces the two outputs in the form of sum and carry. The sum is 1 when either
of the input is one. The sum is 0 when both the inputs are 0 or Carry is one when both the inputs
are 1. From the truth table the logical expression of sum output can be written as a sum of
product expression by summing the inputs for which the sum is 1. S = A'B + AB' this expression
can be simplified as XOR form S = A ⨁ B Carry output can be written as product of sum
expression for which the carry is 1. Countt = AB.

The circuit is designed using CMOS as combination of Pullup and Pull-down networks. The
function of the Pullup network is to provide a connection between the output and VDD when the
output of the logic gate is meant to be 1. The function of the PDN is to connect the output to VSS
when the output of the logic gate is meant to be 0. 16 numbers of transistors are needed for the
implementation of half adder using CMOS.

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Table: Truth Table of Half Adder

Fig: Simulation of Half Adder

Fig: Output waveform of full Adder

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Full Adder
Full Adder plays important role in electronics industry especially digital signal processing
(DSP), image processing and performing arithmetic operations in microprocessors. Full Adder is
such an important element which contributes substantially to the total power consumption of the
system. With the advance of VLSI technology, to either speed up the operation or reduce the
power/energy consumption hardware implementation of many applications such as multimedia
processing, digital communication can be possible. The essence of the approximately all digital
computing lies in the full adder design. adder circuits are of great interest to digital system
designers. Adders are important components in the applications like Digital Signal Processing
(DSP) architectures. For signal processing, digital full-adder are the basic logic circuits which
can find applications in digital computing and packet labels processing. Addition is the most
basic arithmetic operation; and adder is the most fundamental arithmetic component of the
processor. The rapid increase in the number of transistors on chips has enabled a dramatic
increase in the performance of computing systems. Computations need to be performed using
low- power, area-efficient circuits operating at greater speed.

The Full-Adder (FA) is used widely in systems with operations such as counter, addition,
subtraction, multiplication and division etc. It is the basic core component of Arithmetic-Logic-
Unit (ALU). Thus, the innovation and acceleration of FA means that the speed of the Central-
Processor-Unit.

The most commonly used adder with complementary pull-up pMOS and pull-down nMOS
networks in digital circuits is conventional 28 transistor full adder. A complementary static
CMOS full adder circuit consists of an NMOS pull down network connecting the ground to the
output and a dual pMOS pull up network connecting the power to the output.

Fig: Schematic diagram of Full Adder

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Table: Truth Table of Full Adder.

Fig: Layout of full adder

Fig: Simulation result of Full Adder

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 Experiment-3

AIM: Design and Simulate 4*1 Multiplexer

Introduction

A multiplexer is a logic circuit that can select one of many analog or digital input signals and can
transfer the designated input information into a single output channel. A multiplexer of 2 n inputs
has n number of data selection lines, which are used to pick the desired input channel for
transmitting the binary data to a single output channel. This type of logic circuit is mainly used to
increase the amount of data that can be transmitted through a digital system or circuit during a
given time period and channel bandwidth (M. M. Mano and R. Kime, 2001; S.-M. Kang and Y.
Leblebici 2003; N. Weste and D. Harris, 2004). This is also termed a data selector, as it can
select a particular signal from a definite number of channels each containing data to pass to
another device. A multiplexer is an indispensable constituent in digital system design. It is
widely used in data route demanding designs. Data selectors can be considered as a multiple-
input and single-output switch. The control/select input lines connect the desired input channel to
the appropriate output channels (T. L. Floyd, 2011). At present, multiplexers have become a
universal logic element used to design any digital combinational logic circuits/systems in
integrated circuit design so it is needed to design or revise a multiplexer topology for surface
area reduction, low power consumption and high speed operation, i.e. reduced propagation delay.
In 8-bit Carry Skip Adder (CSA) and Carry Select Adder (CSA) circuits, the carry is selected by
the multiplexer (A. S. Ramya et al., 2015).

A 4:1 multiplexer comprises four data input lines as D0, D1, D2 and D3; two select input lines as
S0 and S1 and an output line as Y. The selector lines S0 and S1 select one of the four input lines

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(D0 through D3) and associate it to the output line, Y depending on combination of data of S0
and S1 as per Table 1. Fundamentally, this can be described by employing a Boolean equation.
The Boolean expression (Y) for the 4:1 multiplexer with data input lines D0 to D3 and data
selection lines S0 and S1.

Table:1 Truth Table of 481 Multiplexer.

To do this design, simulation and analysis, two software tools have been used. The circuit is
designed using 90 nm CMOS process in DSch software and then layout is extracted. A Verilog
file has been created from the simulation of this design file. After that the simulation of layout
diagram is performed in Microwind software (Aziz et al., 2010) to analyze the performance of
the designed circuit.

Layout diagram of a 4:1 multiplexer circuit extracted from DSch using 90 nm CMOS process in
Microwind is given in fig below.

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 Fig: Schematic of SR Flip Flop

Table-2 : Simulation parameter Values

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 Fig: Voltage Vs Time Simulation graph

Viva-Voice Question.

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 EXPERIMENT: 4

AIM: Design and Simulate SR Flip-Flop

Introduction:
Memories play an essential role in design of any electronics design where storage of data is
required. Memories are used to store data and retrieve data when required. Read Only Memory
(ROM) and Random Access Memory (RAM) are two types of memories used in modern day
architectures. Random Access Memory is of two types Dynamic Random Access Memory
(DRAM) and Static Random Access Memory (SRAM). SRAM is static in nature and faster as
compared to DRAM.SRAM is expensive and consume less power. SRAM have more transistors
per bit of memory. They are mostly used as cache memories. DRAMS on the other hand are
dynamic in nature and slower as compared to SRAM. DRAM are expensive and consume more
power, they require less transistor per bit of memory. They are mostly used as main memories.
DRAM is widely used for main memories in personal and mainframe computers and engineering
workstation. DRAM memory cell is used for read and write operation for single bit storage for
circuits. A single DRAM cell is capable of storing 1 bit data in the capacitor in the form of
charge. Charge of the capacitor decreases with time .Hence refresh signals are used to refresh the
data in the capacitor. When a read signal reads the data it refreshes it as well. Many different cell
designs exist for modern day DRAM cell. These designs are differentiated by the no. of
transistors used in their designing. As the no. of transistors increase, power dissipation also
increases.

Sequential circuits are logic circuits whose production in any aspect of this moment depends not
only on the input current, but the problems of the past. Sequential circuits are of two types: (i)
clocked and (ii) unclocked. The simplest type of sequential circuit is a memory cell in these two
states. It can be 1 or 0. These two circuits are called sequential flip-flop state states from one
state to another and vice versa. Flip-flops are used as memory elements which are the basic
elements of an integrated circuit. They are used in many applications such as data storage
registering in parallel flow, counter and frequency division, etc ... Computers and machines
utilize flip-flop for your memories. A combination of the number of flip-flops can cause a certain
amount of memory. Flip-flop is constructed using logic gate, which in turn is constituted by
transistors. Flip-flops are the main elements of electronic memory devices. Each flip-flop can
store a given one. The SR flip-flop, also known as SR Latch can be considered as one of the
possible most basic sequential logic circuits. One of these "set" devices (ie output = "1") and
labeled S and other "reset" devices (ie, this simple flip-flop is in fact a memory device bistable
with a little ' Having two inputs, output = "0"), labeled R. Then, SR description means "Set
reset." Resetting the flip-flop reset input in its initial state at Q output will be a logic level of "1"
or "0" depending on the state of the set / reset. 2. Working of SR Flip Flop Model: Flip-flop SR
is commonly used flip-flop. It is also known as a set-reset flip-flop. Notice that when inputs S =
"1" and R = "1" Q and Q’ can be either logical levels "1" or "0" output, depending on state of S
or R input, given input . Therefore, the condition of S = R = "1" does not change the status of
output Q and Q’. However, the input state S = "0" and R = "0" is an undesirable condition or

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invalid and should be avoided. The condition S = R = "0" causes both output Q and Q’ together
to be high logic level "1" when reverse is usually Q. Q is losing the result of the check is that
flip-flop Q and Q’ , And where the two inputs are now switched "high" after logical condition
"1", the flip-flop becomes unstable and changes in a state of unknown data based on imbalance
as shown in the pattern reduction Penalty.

Table : Truth Table of SR Flip-flop

If S= 0;R=1 then Q = 0; Q’ = 1 so flip flop is reset.

If S = 1;R=0Q = 1; Q’ = 0 so flip flop is set.

Operation of SR Flip Flop

Set State of Flip Flop.

Consider the circuit shown above. If R input is logic level "0" (R = 0) and S input is logic level
"1" (S = 1), the NAND gate has at least one inputs in logic "0" Output Q should be a logical
value "1" ( NAND gate principle). Output Q "A" input is also restored, then both input X NAND
gate is at logic level "1" and then the Q output should be no logic level "0". He leads the NAND
gate again. If input R reset R changes state and goes to HIGH logic "1" and S remains high at a
logic level of "1", NAND gate is now Y ,R = "1" and B = "0". As one of its inputs is still at logic
level "0" Q output remains highly logical "1" and has no state change. Therefore, it is said that
the flip-flop circuit is "register" or "set" Q = "1" and Q = "0".

Reset State of Flip Flop.

In the second static state, Q is at the level "0" (not Q = "0") of the inverse Q output is logic level
"1" (Q = "1") and is given by R = "1 'And S =' 0 'When the X port is one of the inputs in the logic
"0" Q output must be equal to the logic value "1" (NAND gate principle.) The Q output at input

34
"B" Returned, so that both NAND gate inputs are logical "1", therefore, Q = "0". If the S input
set is now changing its state from the logic "1", the input R in logical "1", the Q output is still
low still at logic level "0" and there is no state change. Therefore, the state of the "reset" of the
flip-flop circuit also has been blocked and may specify the action to "set

Fig: Timing Diagram of SR Flip Flop

Fig: Flip-flop Implementation using Transistor logic.

35
Fig: Transistor Level diagram of SR Flip-flop using CMOS Technology

Fig: Timing level diagram.

36
 EXPERIMENT-5

AIM: Design and Simulate any DRAM Cell

Introduction
Memories play an essential role in design of any electronics design where storage of data is
required. Memories are used to store data and retrieve data when required. Read Only Memory
(ROM) and Random Access Memory (RAM) are two types of memories used in modern day
architectures. Random Access Memory is of two types Dynamic Random Access Memory
(DRAM) and Static Random Access Memory (SRAM). SRAM is static in nature and faster as
compared to DRAM.SRAM is expensive and consume less power. SRAM have more transistors
per bit of memory. They are mostly used as cache memories. DRAMS on the other hand are
dynamic in nature and slower as compared to SRAM. DRAM are expensive and consume more
power, they require less transistor per bit of memory. They are mostly used as main memories.
DRAM is widely used for main memories in personal and mainframe computers and engineering
workstation. DRAM memory cell is used for read and write operation for single bit storage for
circuits. A single DRAM cell is capable of storing 1 bit data in the capacitor in the form of
charge. Charge of the capacitor decreases with time .Hence refresh signals are used to refresh the
data in the capacitor. When a read signal reads the data it refreshes it as well. Many different cell
designs exist for modern day DRAM cell. These designs are differentiated by the no. of
transistors used in their designing. As the no. of transistors increase, power dissipation also
increases.

The area efficiency of the memory array, i.e., the number of stored data bits per unit area, is one
of the key design criteria that determine the overall storage capacity and, hence, the memory cost
per bit. Another important issue is the memory access time, i.e., the time required to store and/or
retrieve a particular data bit in the memory array. The access time determines the memory speed,
which is an important performance criterion of the memory array. Finally, the static and dynamic
power consumption of the memory array is a significant factor to be considered in the design,
because of the increasing importance of low-power applications. In the following, we will
investigate different types of MOS memory arrays and discuss in detail the issues of area, speed,
and power consumption for each circuit type Read-write (R/W) memory circuits, on the other
hand, must permit the modification (writing) of data bits stored in the memory array, as well as
their retrieval (reading) on demand. This requires that the data storage function be volatile, i.e.,
the stored data are lost when the power supply voltage is turned off. The read-write memory

37
circuit is commonly called Dynamic Random Access Memory (RAM), mostly due to historical
reasons. Compared to sequential-access memories such as magnetic tapes, any cell in the R/W
memory array can be accessed with nearly equal access time.

Various types of DRAM Memory

1)1T1C DRAM Cell

2) 4T DRAM Cell

3) 3T DRAM Cell.

3TID DRAM Cell.

1T1C DRAM Cell

The information is stored as different charge levels at a capacitor in conventional 1T/1C DRAM.
The advantage of using DRAM is that it is structural simple: only one transistor and capacitor are
required for storing one bit, compared to six transistors required in SRAM. This allows DRAM
to have a very high density. The DRAM industry has advanced over a period of time in packing
more and more memory bits per unit area on a silicon die. But, the scaling for the conventional
1Transistor/1Capacitor (1T/1C) DRAM is becoming increasingly difficult, in particular due to a
capacitor has become harder to scale, as device geometries shrink. Apart from the problems
associated with the scaling of the capacitor, scaling also introduces yet another major problem
for the DRAM manufacturers which is the leakage current.

38
Fig: Schematic 1T1C DRAM cell

Fig: Schematic 1T1C DRAM cell

39
Fig: Read Write operation of 1T1C DRAM Cell

40
 EXPERIMENT-1
AIM: Design of various Logic Gates using VHDL

LOGIC GATES:

A logic gate performs a logical operation on one or more logic inputs and produces a
single logic output. The logic normally performed is Boolean logic and is most
commonly found in digital circuits. Logic gates are primarily implemented
electronically using diodes or transistors, but can also be constructed using
electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules,
or even mechanical elements.

INPUT OUTPUT
A B A AND B
0 0 0
0 1 0
AND 1 0 0
1 1 1

INPUT OUTPUT
A B A OR B
0 0 0
OR A+B 0 1 1
1 0 1
1 1 1

INPUT OUTPUT
A NOT A
0 1
NOT 1 0

In electronics a NOT gate is more commonly called an inverter. The circle on the
symbol is called a bubble, and is generally used in circuit diagrams to indicate an
inverted (active-low) input or output.
INPUT OUTPUT
A B A NAND B
0 0 1
0 1 1
1 0 1
1 1 0

LAB MANUAL (VII SEMECE) Page1

NAND

LAB MANUAL (VII SEMECE) Page2

 INPUT OUTPUT
A B A NOR B
0 0 1
0 1 0
NOR 1 0 0
1 1 0

INPUT OUTPUT
A B A XOR B
0 0 0
0 1 1
XOR 1 0 1
1 1 0

INPUT OUTPUT
A B A XNOR B
0 0 1
0 1 0
XNOR or 1 0 0
1 1 1

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 VLSI DESIGN LAB (7EC4-21)

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity all_ga is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC;
c1 : out STD_LOGIC;
c2 : out STD_LOGIC;
c3 : out STD_LOGIC;
c4 : out STD_LOGIC;
c5 : out STD_LOGIC;
c6 : out STD_LOGIC);
end all_ga;

architecture Behavioral of all_ga is

begin
c <= a and b;
c1 <= a or b;
c2 <= a nand b;
c3 <= a nor b;
c4 <= a xor b;
c5 <= a xnor b;
c6 <= not b;

end Behavioral;

OUTPUT:

RTL View

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 VLSI DESIGN LAB (7EC4-21)

Simulation Waveform

Quiz Questions with answer.

Q.1What is VHDL?
Ans. VHDL is the VHSIC Hardware Description Language. VHSIC is an
abbreviation for Very High Speed Integrated Circuit.
Q.2How many truth table entries are necessary for a four-input circuit?
Ans.16
Q. 3What input values will cause an AND logic gate to produce a HIGH output?
Ans. All inputs of AND gate must be HIGH.
Q.4 Name all the basic gates.
Ans. i) AND ii) OR iii) NOT
Q.5 Name all the universal gates.
Ans .i) NAND ii) NOR
Q.6 What is the full form of IEEE?
Ans. Institute of Electrical and Electronic Engineering.
Q7. What is the full form of ASCII?
Ans. American Standard Code for information Interchange.
Q8. Define Entity.
Ans. It is an external view of a design unit.
Q9. Why NAND and NOR are called universal gates?
Ans. Because all the basic gates can be derive from them.
Q10. How many architectures are present in VHDL?
Ans. 4 i.e.behavior, dataflow, structural and mixed.

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EXPERIMENT-2

Aim : Design a 4:1 Multiplexer

Multiplexer

In digital circuit design, the selector wires are of digital value. In the case of a 2-to-1
multiplexer, a logic value of 0 would connect I0 to the output while a logic value of 1
would connect I1 to the output. In larger multiplexers, the number of selector pins is
equal to [log2(n)] where n is the number of inputs.

A 4-to-1 multiplexer has a Boolean equation where A, B, C and D are the two
inputs, 1and S0 are the select lines, and Y is the output:

S1 S0 Y

0 0 A
0 1 B
1 0 C
1 1 D

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 VLSI DESIGN LAB (7EC4-21)

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity abcd is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
y : out STD_LOGIC);
end abcd;

architecture Behavioral of abcd is

begin
y <= a when s0 ='0' and s1 = '0' else
b when s0 ='0' and s1 = '1' else
c when s0 ='1' and s1 = '0' else
d;

end Behavioral;

OUTPUT:

RTL View

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 VLSI DESIGN LAB (7EC4-21)

Simulation Waveform

3:8 Decoder using VHDL

Decoder:

A decoder is a device which does the reverse of an encoder, undoing the encoding so
that the original information can be retrieved. The same method used to encode is
usually just reversed in order to decode.

In digital electronics, a decoder can take the form of a multiple-input, multiple-

output logic circuit that converts coded inputs into coded outputs, where the input and
output codes are different. Decoding is necessary in applications such as
data multiplexing, 7 segment display and memory address decoding.

The truth table for 3:8 decoder and respective circuit diagram is as follows:

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 VLSI DESIGN LAB (7EC4-21)

Program:
-----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity decoder_using_case is
port (
enable :in std_logic; -- Enable for the decoder
binary_in :in std_logic_vector (2 downto 0); -- 3-bit Input
decoder_out :out std_logic_vector (7 downto 0) -- 8-bit Output

);
end entity;

architecture behavior of decoder_using_case is

begin
process (enable, binary_in)
begin
decoder_out <= X"000";
if (enable = '1') then
case (binary_in) is
when X"0" => decoder_out <= X"000";
when X"1" => decoder_out <= X"001";
when X"2" => decoder_out <= X"010";
when X"3" => decoder_out <= X"011";
when X"4" => decoder_out <= X"100";
when X"5" => decoder_out <= X"101";
when X"6" => decoder_out <= X"110";
when X"7" => decoder_out <= X"111";
end case;
end if;
end process;
end architecture;

OUTPUT:

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Simulation
Waveform

VIVA-VOICE Questions with answer.

Multiplexer
Q.1 Name combinational logic circuit which sends data coming from a single
source to two or more separate destinations.
Ans: Demultiplexer
Q.2 What is the another name of Multiplexer.
Ans. Data Selector.
Q.3 How many control lines will be used for a 8 – to – 1 multiplexer?
Ans. The number of control lines for an 8 to 1 Multiplexer is 3.
Q.4 Which device changes serial data to parallel data .
Ans. The device which changes from serial data to parallel data is demultiplexer.
Q.5 How many select lines will a 16 to 1 multiplexer will have?
Ans. 4
Q6. Is it possible to construct 4:1 mux using two 2:1 mux?
Ans. Yes
Q7. How many outputs are there in 1:8 mux?
Ans 8.
Decoder
Q.1 Name the examples of combinational logic circuits.
Ans. Examples of common combinational logic circuits include: half adders, full
adders, multiplexers, demultiplexers, encoders and decoders.
Q.2 How many two-input AND and OR gates are required to realize
Y=CD+EF+G ?
Ans Y=CD+EF+G
Number of two input AND gates=2
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 VLSI DESIGN LAB (7EC4-21)
Number of two input OR gates = 2
One OR gate to OR CD and EF and next to OR of G & output of first OR gate.
Q.3 Which device converts BCD to Seven Segment ?
Ans. A device which converts BCD to Seven Segment is called DECODER.
Q.4 What is a test bench in vhdl?
Ans. A Test Bench in VHDL is code written in VHDL that provides stimulus for
individual modules (also written in VHDL). Individual modules are
instantiated by a single line of code showing the port.
Q.5 What are the advantages of designing?
Ans. Advantages of Designing:
1. Designing is useful in quick implementation, testing and useful in complex
circuits.
2. Designing reduces the design cycle.
Q6: Write the applications of Encoder and decoder.
Ans: They are used in communication systems.
Q7: Name some encoders.
Ans Priority encoder , 4:2 encoder and etc.
Q8: How many i/ps are in 4:2 encoder?
Ans 4 i/ps and 2 o/ps.
Q9: How many select lines are present in 2:4 decoder?
Ans none

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 VLSI DESIGN LAB (7EC4-21)

EXPERIMENT No. 3
Aim:- Design of Half adder, Full adder.

Half adder

A half adder is a logical circuit that performs an addition operation on two one-bit
binary numbers often written as A and B.
The half adder output is a sum of the two inputs usually represented with the
signals Cout and S where

Following is the logic table and circuit diagram for half adder:

Inputs Outputs

A B C S

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

Fig: Schematic diagram of Half Adder

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 VLSI DESIGN LAB (7EC4-21)

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.V Components.all;

entity ha is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end ha;

architecture Behavioral of ha is
begin
s <= a xor b;
c <= a and b;
end Behavioral;

OUTPUT:

RTL View

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 VLSI DESIGN LAB (7EC4-21)

Simulation Waveform

Full adder

A full adder is a logical circuit that performs an addition operation on three one-bit
binary numbers often written as A, B, and Cin. The full adder produces a two-bit
output sum typically represented with the signals Cout and S where

.
The full adder's truth table is:

Inputs Outputs

A B Ci Co S
0 0 0 0 0
1 0 0 0 1
0 1 0 0 1
1 1 0 1 0
0 0 1 0 1
1 0 1 1 0
0 1 1 1 0
1 1 1 1 1

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 VLSI DESIGN LAB (7EC4-21)

Fig: Schematic diagram of Full Adder

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fa is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
end fa;

architecture Behavioral of fa is

begin
s <= (a xor b) xor cin;
cout <= (a and b) or (b and cin) or (a and cin);

end Behavioral;

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 VLSI DESIGN LAB (7EC4-21)

OUTPUT:

RTL View

Simulation Waveform

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 VLSI DESIGN LAB (7EC4-21)

Viva Voice Questions with answer.

Q.1 Who is the father of VHDL?

Ans. John Hines, Wright Patterson AFB, Daton Ohio.

Q.2 What is a test bench in vhdl?

Ans.A Test Bench in VHDL is code written in VHDL that provides stimulus for
individual modules (also written in VHDL). Individual modules are instantiated by a
single line of code showing the port.

Q.3How many inputs and output are used in Full adder?

Ans. Three inputs and two output.

Q.4 What are the advantages of designing?

Ans. Advantages of Designing:

1. Designing is useful in quick implementation, testing and useful in complex

circuits.

2. Designing reduces the design cycle.

Q.5Why HDL is used?

Ans.HDL is used because it is easy to design, implement, test and document

increasingly complex digital system.

Q6. How many types of architecture in VHDL?

Ans: 4

Q7. What is the difference between sequential and combinational ckts.?

Ans: Seq ckts have memory cell inside it and combinational has no memory in it.

Q8. Is it possible to construct full adder using half adder?

Ans: Yes, by using two half adders.

Q9. How many i/ps required for half subtractor?

Ans: Two, difference and a borrow.

Q10. Is it possible to construct full subtractor using half subtractor?

Ans: Yes, by using two half subtractor.

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 VLSI DESIGN LAB (7EC4-21)

EXPERIMENT No. 4

Aim : Design a RS & JK flip-flop

RS & JK FLIP-FLOP

RS flip-flops are useful in control applications where we want to be able to set or

reset the data bit. However, unlike SR latches, SR flip-flops change their content only
at the active edge of the clock signal. Similar to SR latches, SR flip-flops can enter an
undefined state when both inputs are asserted simultaneously.

The truth table and circuit diagram are as follows:

Program:

library ieee;

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 VLSI DESIGN LAB (7EC4-21)
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;

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 VLSI DESIGN LAB (7EC4-21)

entity SR-FF is
PORT( S,R,CLOCK,CLR,PRESET: in std_logic;
Q, QBAR: out std_logic);
end SR-FF;

Architecture behavioral of SR-FF is

begin
P1: PROCESS(CLOCK,CLR,PRESET)
variable x: std_logic;
begin
if(CLR='0') then
x:='0';

elsif(PRESET='0')then
x:='1';

elsif(CLOCK='1' and CLOCK'EVENT) then

if(S='0' and R='0')then

x:=x;
elsif(S='1' and R='1')then
x:='Z';

elsif(S='0' and R='1')then

x:='0';

else
x:='1';

end if;
end if;

Q<=x;
QBAR<=not x;
end PROCESS;
end behavioral;

Simulation Waveforms

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JK FLIP-FLOP

JK flip-flops are very similar to SR flip-flops. The J input is just like the S input in that when asserted,
it sets the
flip-flop. Similarly, the K input is like the R input where it clears the flip-flop when asserted. The only
difference is when both inputs are asserted. For the SR flip-flop, the next state is undefined, whereas,
for the JK flip-flop, the next state is the inverse of the current state. In other words, the JK flip-flop
toggles its state when both inputs are asserted.

The truth table and circuit diagram are drawn below:

Program:

library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;

entity JK-FF is
PORT( J,K,CLK,PRST,CLR: in std_logic;
Q, QB: out std_logic);
end JK-FF;

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Architecture behavioral of JK-FF is

begin
P1: PROCESS(CLK,CLR,PRST)
variable x: std_logic;
begin
if(CLR='0') then
x:='0';

elsif(PRST='0')then
x:='1';

elsif(CLK='1' and CLK'EVENT) then

if(J='0' and K='0')then
x:=x;
elsif(J='1' and K='1')then
x:= not x;

elsif(J='0' and K='1')then

x:='0';
else
x:='1';

end if;
end if;
Q<=x;
QB<=not x;
end PROCESS;
end behavioral;

Simulation Waveforms

Viva Voice Questions with answer.

Q.1 Define flip-flop.

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 VLSI DESIGN LAB (7EC4-21)

Ans. A flip-flop is a device that can maintain binary information until it is directed by
an input signal to change its state. There are several different types of flip-flops, the
more commonly used are the D-FF and the JK-FF. Flip-flops are used in sequential
circuit design.
Q. 2The MSI chip 7474 is
Ans. MSI chip 7474 dual edge triggered D Flip-Flop.
Q. 3 How many flip-flops are required to construct mod 30 counter?
Ans 5
Q.4The output of SR flip flop when S=1, R=0 is
Ans As for the SR flip-flop S=set input R=reset input ,when S=1, R=0, Flip-flop will
be set.
Q.5 The number of flip flops contained in IC 7490 is
Ans 2.
Q6 What are the I/Ps of JK flip–flop where this race round condition occurs?
Ans; .Both the inputs are 1
Q7: .Flip flop is astable or bistable?
Ans Bistable.
Q8: When RS flip-flop is said to be in a SET state?
Ans. When the output is 1
Q9: What is the function of clock signal in flip-flop?
Ans. To get the output at known time.

Q10: What is the advantage of JK flip-flop over RS flip-flop?

Ans. In RS flip-flop when both the inputs are 1 output is undetermined.

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 VLSI DESIGN LAB (7EC4-21)
EXPERIMENT NO:5

AIM: Design and Simulate Asynchronous Counter

Counters remember the digital combinations of data. Counters are used everywhere and every
time in our day to day life. Example is the digital clock alarm that wakes you up in the early
morning.
There are two types of counters

 1) Synchronous and
 2) Asynchronous.

Asynchronous counters are those whose output is free from the clock signal. Because the flip
flops in asynchronous counters are supplied with different clock signals, there may be delay in
producing output.

The required number of logic gates to design asynchronous counters is very less. So they are
simple in design. Another name for Asynchronous counters is “Ripple counters”.

The number of flip flops used in a ripple counter is depends up on the number of states of counter
(ex: Mod 4, Mod 2 etc). The number of output states of counter is called “Modulus” or “MOD”
of the counter. The maximum number of states that a counter can have is 2n where n represents
the number of flip flops used in counter.

For example, if we have 2 flip flops, the maximum number of outputs of the counter is 4 i.e. 22.
So it is called as “MOD-4 counter” or “Modulus 4 counter”.

Different types of Asynchronous counters

There are many types of Asynchronous counters available in digital electronics. They are

 4 bit synchronous UP counter

 4 bit synchronous DOWN counter
 4 bit synchronous UP / DOWN counter

UP Counting

If the UP input and down inputs are 1 and 0 respectively, then the NAND gates between first flip
flop to third flip flop will pass the non inverted output of FF 0 to the clock input of FF 1.
Similarly, Q output of FF 1 will pass to the clock input of FF 2. Thus the UP /down counter
performs up counting.

DOWN Counting

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 VLSI DESIGN LAB (7EC4-21)
If the DOWN input and up inputs are 1 and 0 respectively, then the NAND gates between first
flip flop to third flip flop will pass the inverted output of FF 0 to the clock input of FF 1.
Similarly, Q output of FF 1 will pass to the clock input of FF 2. Thus the UP /down counter
performs down counting. The up/ down counter is slower than up counter or a down counter,
because the addition propagation delay will added to the NAND gate network.

Fig: block diagram of 4 bit Counter

Table: Truth Table of 4 bit Counter

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Fig: 4 Bit Asynchronous UP Counter

Fig: 4 Bit Asynchronous DOWN Counter

Advantages

 Asynchronous counters can be easily designed by T flip flop or D flip flop.

 These are also called as Ripple counters, and are used in low speed circuits.
 They are used as Divide by- n counters, which divide the input by n, where n is an integer.
 Asynchronous counters are also used as Truncated counters. These can be used to design
any mod number counters, i.e. even Mod (ex: mod 4) or odd Mod (ex: mod3).

Disadvantages

 Sometimes extra flip flop may be required for “Re synchronization”.

 To count the sequence of truncated counters (mod is not equal to 2n), we need additional
feedback logic.
 While counting large number of bits, the propagation delay of asynchronous counters is
very large.
 For high clock frequencies, counting errors may occur, due to propagation delay.

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 VLSI DESIGN LAB (7EC4-21)
Applications of Asynchronous Counters

 Asynchronous counters are used as frequency dividers, as divide by N counters.

 These are used for low power applications and low noise emission.
 These are used in designing asynchronous decade counter.
 Also used in Ring counter and Johnson counter.
 Asynchronous counters are used in Mod N ripple counters. EX: Mod 3, Mod 4, Mod 8,
Mod 14, Mod 10 etc.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity counter_universal is
port
(
clock : in STD_LOGIC;
reset : in STD_LOGIC;

clear_count : in STD_LOGIC;
enable : in STD_LOGIC;

counter_out : out STD_LOGIC_VECTOR (9 downto 0)

);
end counter_universal;

architecture Behavioral of counter_universal is

signal s_count : unsigned(9 downto 0); -- := (others => '0');

begin

process(clock, reset)
begin

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 VLSI DESIGN LAB (7EC4-21)
if reset = '1' then -- async reset -> put 'reset in sensitivity list
s_count <= (others => '0');
elsif rising_edge(clock) then
if clear_count = '1' then -- (synchr) clear count takes precedence over enable
s_count <= (others => '0');
elsif enable = '1' then
s_count <= s_count + 1;
end if;
end if;
end process;

-- connect internal signal to output

counter_out <= std_logic_vector(s_count);

end Behavioral;

- sync 'reset' and 'clear'

process(clock)
begin
if rising_edge(clock) then
if (reset = '1') or (clear_count = '1') then
s_count <= (others => '0');
elsif enable = '1' then
s_count <= s_count + 1;
end if;
end if;
end process;

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 VLSI DESIGN LAB (7EC4-21)

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