Faculty of Computers and Artificial Intelligence

CS222: Computer Architecture

Lab no 02: Simulate 2-to-1 Multiplexer &

Implement 7-Segment Decoder

The purpose of this Lab is to learn to:

1) Simulate 2-to-1 multiplexer on ModelSim and verify
multiplexer function using testbench. In this lab, you will
build the multiplexer using logic gates (refer to Lab 01).
2) Implement the seven-segment decoder on FPGA. You will
write the logic equation for each segment using Verilog
bitwise operators.
Objective: a seven-segment run on FPGA (Here).
Refer to assignment 2, to review the logic equations of the
seven-segment decoder.

Parts: -

1. Simulate 2-1 multiplexer using logic gates.

2. Implement the seven-segment decoder using logic
equations and run it on the FPGA.

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Part 1. Simulate 2-1 multiplexer using logic gates (Lab01).

out_G2
G2
not_S

G1
out_G3
G3

G4

The multiplexer chooses between the two data inputs based on

the select:
if S = 0, Y =D0, and if S = 1, Y =D1.

Verilog code for multiplexer 2-to-1

// ------------------- Mux 2-1 ---------------------//
module mux_2_1(S,D0,D1,Y);
input S, D0, D1;
output Y;
wire not_S, out_G2, out_G3;
notGate G1(S, not_S);
andGate G2(D0, not_S, out_G2);
andGate G3(D1, S, out_G3);
orGate G4(out_G2, out_G3, Y);
endmodule
// ------------------- AND Gate ---------------------//
module andGate (a,b,c);
input a, b;
output c;
assign c = a & b;
endmodule

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

// ------------------- Or Gate ---------------------//

module orGate (a,b,c);
input a, b;
output c;
assign c = a | b;
endmodule
// ------------------- Not Gate ---------------------//
module notGate (a,c);
input a;
output c;
assign c = ~a;
endmodule

Testbench of the multiplexer 2-to-1

module mux_tb;
reg s, d0, d1;
wire y;
mux_2_1 mux_dut(s,d0,d1,y);
initial
begin
s= 0; d0 = 0; d1 =0;
#10 s=0; d0=0; d1=1; // select d0=1
#10 s=0; d0=1; d1=0; // select d0=0
#10 s=1; d0=0; d1=1; // select d1=1
#10 s=1; d0=1; d1=0; // select d1=0
end
endmodule

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Part 2. Implement the seven-segment decoder using logic

equations.

A seven-segment display decoder takes a 4-bit

data input A, B, C, D and produces seven
outputs to control light-emitting diodes to display
a digit from 0 to 9. The seven outputs are often
called segments a through g, as defined in
Figure.
The truth table of the seven-segment decoder:

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

The logic equations of the seven-segment decoder

• Bitwise operators

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Verilog code for Decoder to 7 segments

module decoder_7seg (A, B, C, D, led_a, led_b, led_c,
led_d, led_e, led_f, led_g);
input A, B, C, D;
output led_a, led_b, led_c, led_d, led_e, led_f,
led_g;

assign led_a = ~(A | C | B&D | ~B&~D);

assign led_b = ~(~B | ~C&~D | C&D);
assign led_c = ~(B | ~C | D);
assign led_d = ~(~B&~D | C&~D | B&~C&D | ~B&C |A);
assign led_e = ~(~B&~D | C&~D);
assign led_f = ~(A | ~C&~D | B&~C | B&~D);
assign led_g = ~(A | B&~C | ~B&C | C&~D);
endmodule

Run the seven-segment decoder on FPGA.

We will use a DE-10lite kit, Altera MAX 10 based FPGA board,

check here. Check DE10-lite user manual (Here).
You will use Quartus to program the FPGA.

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Quartus – Seven Segment Decoder Project Steps

Step 1: Open Quartus.

Step 2: Open a New Project Wizard.

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Step 3: Select Next

Step 4: Choose a directory to put your project under. you can

place it wherever you want. Name the project as the name of
the top-level module. You will name it “decoder_7seg”, Select
Next.

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CS222: Computer Architecture

Step5: Select Empty Project, and then click Next.

Step 6: If You want to add any files here. Add the seven-
segment decoder Verilog file And Click Next.

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Step7: Board Settings, select our board DE10-lite, unmark

“create top-level design file”

Step 8: EDA Tool Settings then finish.

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Step 9: compile the design

Step 10: Pin assignment on FPGA

In this step, you will assign inputs (A,B,C,D) to the switches,

And the outputs (led_a, led_b, led_c, led_d, led_e, led_f, led_g)
to the first segment display.

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

To assign pins, refer to DE10-lite FPGA user manual.

User-Defined Slide Switch Section

7-segment displays section

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Assign pins on Quartus, open the assignment tab, click on pin

planner, and assign pins as figure below.

Step 11: Compile all project after pin assignment, like step 9.
Program the FPGA.
Step 12: load the program to the FPGA.

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Press “Start”
Hint: you may have a problem with the FPGA driver. Check the
“device manager” and update the USB driver.

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