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Lect43 How To Create An Interface

The interface construct allows grouping of related signals to represent connectivity and functionality. It can be used to define connections between testbenches and RTL modules. Interfaces contain signals, clocks, and can specify direction of ports using modports. They simplify connections and allow cleanly encapsulating common buses between modules.

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Mahesh N 22MVD0090
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43 views

Lect43 How To Create An Interface

The interface construct allows grouping of related signals to represent connectivity and functionality. It can be used to define connections between testbenches and RTL modules. Interfaces contain signals, clocks, and can specify direction of ports using modports. They simplify connections and allow cleanly encapsulating common buses between modules.

Uploaded by

Mahesh N 22MVD0090
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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The Interface Construct

•An intelligent bundle of signals. Contains:


• connectivity
• synchronization
• functionality
•Can be used for testbench as well as RTL connections
The Interface Construct
•An intelligent bundle of signals. Contains:
• connectivity
• synchronization
• functionality
•Can be used for testbench as well as RTL connections
Testbench

grant[1:0]
request[1:0]
Arbiter
rst clk

interface arb_if(input bit clk);


logic [1:0] grant, request;
Testbench Interface Arbiter bit rst;
endinterface
Using an Interface to Simplify Conn.
module arb( module arb (arb_if arb_bus);
output logic [1:0] grant, always @(posedge arb_bus.clk or
input logic [1:0] request, posedge arb_bus.rst) begin
input logic rst, if (arb_bus.rst)
input logic clk); arb_bus.grant <= 2’b00;
else
always @(posedge clk or ....
posedge rst) begin end
if (rst) endmodule
grant <= 2’b00;
else
....
module top;
end
bit clk;
endmodule
always #5 clk = ~clk;
arb_if arb_bus(clk);
interface arb_if(input bit clk); arb a1(arb_bus);
logic [1:0] grant, request; test t2(arb_bus);
bit rst; endmodule
endinterface
Source: Chris Spear: System Verilog for Verification
Connecting Interfaces and Ports
If the ports of a legacy design cannot be changed to use an interface...
interface arb_if(input bit clk);
logic [1:0] grant, request;
bit rst;
endinterface module top;
bit clk;
always #5 clk = ~clk;
arb_if arb_bus(clk);
arb a1(
.grant(arb_bus.grant),
.request(arb_bus.request),
.rst(arb_bus.rst),
.clk(arb_bus.clk)
);
test t2(arb_bus);
endmodule
Group Signals in I/F using Modport
•Default direction of signals in interface is bi-directional
•Probably not what you want for RTL or testbench.
•Specify direction using modport
interface arb_if(input bit clk);
logic [1:0] grant, request;
bit rst;

modport DUT (input request, rst, clk,


output grant);
endinterface

Usage:
Module definition
module arb(arb_if.DUT arb_bus);
or
Instantiation
arb a1 (arb_bus.DUT);
Mixing interface and ordinary ports
Typically only common busses will be encapsulated in an interface
`default_nettype none
`include "arb_if.v"

module test;
bit clk;
bit [7:0] data_in, data_out;
always #5 clk = ~clk;
arb_if arb_bus(clk);
arb arb (.data_in(data_in), arb_bus.DUT,
.data_out(data_out));
endmodule

module arb(input [7:0] data_in, arb_if arb_bus,


output [7:0] data_out);
Example
Example

Modports allow specification of direction of ports connected to the interface


SV Interface Example

Simulation Log:
Value of a = 6, b = 4
Sum of a and b, c = 10
Example
Example of named port bundle

Example of connecting port bundle


Example
Example
How to parameterize an interface ?
Interface Array
SV Interface- Summary

 Captures communication aspect


 Groups signals
 Controls direction of data flow (modport)
 Describes timing (clocking and specify blocks)
 Checks protocol validity/violation – assertions
 Checks protocol compliance - coverage

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