IJETST- Vol.

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International Journal of Emerging Trends in Science and Technology

Risc Processor Using VHDL

Autors
Dr. S. L. Lahudkar , Amit M. Mankar2, Sudesh D. Bhong3
1

Department of Electronics & Telecommunication,

JSPM’s, Imperial College Of Engineering & Research,
Savitribai Phule Pune University, Pune, India
Email: [email protected], [email protected]

ABSTRACT
Reduced Instruction Set Computer (RISC) is become a design theory that has accepted in engineering
applications. Optimizing gate capacity and performance of FPGA kit. This devices provides complex logic
systems to be performed and implemented on a single device. So the main aim of this project is to design,
study and implement an 8-bit Reduced Instruction Set Computer processor using XILINX Spartan 3E tool.
The elevate feature of Spartan-3E reduces the cost per logic cell designed. The prominent feature of the RISC
processor is that this processor is very simple. RISC processor support load/store architecture (Von
Neumann). The main components of processor include the Arithmetic Logic Unit, Control unit, Shifter, and
Rotator.
Keywords- RISC, PIPELING, VHDL, SPARTAN 3E TOOL.

processor as well as a guide for a multiprocessor

I. INTRODUCTION access for SoC designs.
In every life development is taking place at a very As given above, most SoC architectures have
rapid rate. Market is becoming more and more harsh concern the area of module and power
customer driven. Customer wants system designed optimize. For this reason, we have chosen a well-
tailor made to suit his needs. This is putting suited architecture with small demands on both of
burden and stress on the embedded system these aspects. The Microchip PIC-Core
designer. Choosing appropriate processor and architecture has sufficient performance for a broad
supporting peripherals is becoming very critical. variety of embedded applications. Therefore, we
Considering this aspect and the growth in the field designed the Core in the hardware description
of VLSI design, so the days are no longer when language VHDL, a processor core that is binary
the people will start design their own processor compatible to the Microchi
The selected project topic is aiming towards the
same direction. The core is developed by using the II. LITERATURE REVIEW
very high speed integrated circuit hardware According to [1] The concept of VHDL code is
description language (VHDL) or (VHSICHDL), realized using the Spartan 3E XC3S100E by
which offers the freedom of adding specific, interfacing the input & output with the system
advance hardware blocks for various operations. through the USB. Also this paper addresses PWM
The effects on area and power consumption as control is verified using CRO.
well as computational power are analyzed.
This paper points towards the implementation of a According to [2] Increasing performance and
RISC processor core that can be used as a single gate capacity of recent FPGA devices permits
complex logic systems to be implemented on a

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IJETST- Vol.||02||Issue||03||Pages 2134-2138||March||ISSN 2348-9480 2015
single programmable device. So the main aim of
this paper is to design Reduced Instruction Set
(RISC) processor using XILINX Spartan 3E tool.
The module process and solve the problem of
area, dissipation of power and propagation delay
are analyzed.

According to [3] This project is to write a VHDL

behavioral model, evolve test-bench and mimic
the behavior. Analyze instruction data path,
decoder module function, MIPS instruction format
and design theory based on RISC instruction set
Figure.1 Architecture Diagram of 16F84A
using pipeline process.
And finally in execution stage, the instruction is
executed, the data is employ and the result is
III. METHODOLOGY stored.
Here design of architecture of an 8-bit RISC
IV. ALGORITHMS
processor is shown in Figure. This architecture
A. The control unit reads the op-code and instruction
consists of control unit, shifter, rotator and
bit and then creates control signals as outputs that
arithmetic logic unit. The processor is designed
trigger the respective components and data path to
with Von Neumann architecture. In this separate
operate the correct task. It has two instruction
data bus and separate address bus is provided
decoder that decode the instruction bits and the
between processor and memory. Instruction and
unscramble output of the control unit is deliver as
data are fetched in linear order so that the
control signal either into Arithmetic logic unit
inactivity occur between the machine cycles can
(ALU) or Universal shifter or Barrel shift rotator.
be reduced.
B. The operands are acknowledged from register A
Four stages of pipelining have been integrated in and register B by the ALU. Depending on the
the design which provides the speed of operation. control signal from the control unit the ALU
The pipelining stages are Instruction Fetch, performs either arithmetic or logic operations.
Instruction Decode, Instruction Execute and Write C. After the execution of the instruction, the result is
back. In Instruction fetch, the instruction and the always stored in the accumulator register or A
necessary data are taken from the memory. register.
Whereas in Instruction decode, the instruction and D. Input is taken from source register A and is either
data that are drawn from the memory are loaded or shifted in right or left direction planted
separated call up the components and the data on the control lines activated by the control unit.
path so as to execute E. The shifted data is saved in the accumulator
register. Input data is prone from source register A
and rotated/shifted N number of times based on
the op-code given from the control unit.
F. The rotated data is stored in the acc. register.

V. SIMULATION & RESULT

In the simulation part first MIPS single-cycle
VHDL operation was complete. The second task

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is to pipeline the MIPS processor. Pipelining is a
mandatory feature in RISC processors which
technique used to improve both clock speed and
overall performance. Pipelining allows a processor
to work on different steps of the instruction at the
same time more instruction can be executed in a
shorter period of time. The data path is divided
into different modules, where each module must
wait for the previous one to finish before it can
execute, thereby completing one instruction in one Figure.3 Fetch Unit
long clock cycle. When the RISC processoris
pipeline, same time a single clock cycle each one B. INSTRUCTION DECODE UNIT
of those modules or stages is in use at exactly the The function of this unit is to use the 8-bit
same time executing on multiple instructions in instruction given from the previous instruction.
parallel. Figure.2 shows an example of a MIPS Fetch unit to obtain the register data values.
single-cycle pipelined (a.) versus a MIPS
pipelined implementation (b.).

Figure.2 Test Bench

The pipelined implementation is faster. The four

modules are Instruction Fetch, Instruction Decode, Figure.4 Instruction Decode Unit
Execution, and Write Back. The Hardware
Discripitive Language design becomes a 2-level However with our design of 8-bit data width, our
hierarchy. The high-level of the hierarchy is a implementation uses the instruction bits [7 – 0]
structural VHDL file which connects the all bits instead of sign extending the value. The logic
components of the single-cycle implementation, component to be implemented in VHDL include
while the lower-level contains the behavioral of several multiplexrs and the register file
VHDL models.

A. INSTRUCTION FETCH UNIT C. CONTROL UNIT

The aim of this unit is to fetch an instruction from The control unit of the RISC processorreads the
the memory using the current value and increment instruction op-code and decodes the instruction to
the next instruction. For getting the instruction produce 9-control signals to be used in the
memory we has to implement byte addressing to remaining modules. The RegDst control signal
access the register and word address. figure out which reg is written to the register file.
The function of Jump control signal is to selects
the jump address into the PC. The Branch control
signal which select the branch address sent into
the PC. The Memread control signal is affirm

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during a load instruction when the data memory is which asserts by memory load instruction and
read to load a register with its memory contents. uses the ALU result as an address of data memory.
The read output data is write into the register file.
A store instruction collects the memory write
signal and writes the data value read from a
register into the computed memory address. The
complete VHDL code used to create the memory
state of the MIPS single-cycle processor.

Figure.5 Controller Unit

The Memory to Register control signal check

whether the data memory output or ALU result is
written to the register file. The ALU Output
signals determine the ALU performs. The
Memory Write control signal is use when a
registers value is saved in the data memory. The
ALUSrc control signal determines if the ALU
second operand comes from the register file or the Figure.7 Data Memory Unit
sign extend. The RegWrite control signal is
asserted when the register file needs to be written. VII. FPGA Module
The Spartan®-3 family of Field-Programmable
D. EXECUTION UNIT Gate Arrays is specifically designed to meet the
The RISC processor contains ALU which execute needs of high volume, cost-sensitive consumer
the operation given by the ALU-output signal. The electronic applications. The eight-member family
branch address is compute by W+4 to the sign offers densities ranging from 50,000 to 5,000,000
extended immediate field shifted left by a separate system gates, The Spartan-3 family are a superior
adder. alternative to mask programmed RSICs. FPGAs
avoid the high initial cost, the lengthy
development cycles, and the inherent inflexibility
of conventional RSICs.

Figure.6 Execution Unit

Also, FPGA programmability permits design
VI. DATA MEMORY UNIT upgrades in the field with no hardware
The data memory unit is only get by the Von- replacement necessary, an impossibility with
Neuman architecture. The memory read signal RSICs

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VII. ADVANTAGES
A. The Processor Achieves Higher Performance, REFERENCES
B. Lower Area, 1. Andrzej Kos, FPGA implementation of
C. Compact in size. RISC Microcontroller‖18th International
D. Low power dissipation. Conference on MIXDES, pp. 323-238, 16-
E. Achieve highest system speed . 17 March 2011.
F. More than 20K times reprogrammable. 2. Design Processor Using VHDL
G. Fast concurrent programming. http://cegt201.bradley.edu/projects/proj200
H. Reconfigurable of logic is possible. 1/vhdlrisc/
I. Reduce serial I/O power ,cost and complexity with 3. Gray, J., Designing a Simple FPGA-
the word first 90 nm FPGA’s. Optimized RISC CPU and System-on-a-
J. Easy upgrade to new specifications. Chip, 2000.
4. IEEE Standard VHDL Language
VIII. APPLICATIONS Reference Manual.IEEE, New York, NY,
A. Portable Gaming Kits, 2002. IEEE Standard 1076-2002.
B. A Systolic Core To Perform Mathematical 5. VHDL Programming [Douglas Perry]
Computations, 6. Brown, Richard, “A Microprocessor
C. Solving Polynomial And Differential Equations. Design Project in an Introductory VLSI
Course”.
IX. ACKNOWLEDEMENT 7. VHDL Programming http://www.asic-
“Inspiration and guidance are invaluable aspect world.com/vhdl/first1.html
for every student in his life”. We would also like 8. VHDL source for simple processor
to take this opportunity to express our honour and http://www.cse.wustl.edu/~dzar/class/260/
respect to express deep sense of regards towards hw/cpu.html
our guide Dr. S. L. Lahudkar Sir of Electronics 9. J.L. Hennessy, "VLSI Processor
& Telecommunication Department, for his Architecture," IEEE Trans. Computers,
encouragement, excellent guidance and precious vol. C-33, no. 12, Dec. 1984, pp. 1221-
suggestion throughout our work and his co- 1246.
operation for successful completion of this
project. Finally, we would thanks to all those who
directly or indirectly made a contribution to
completion of this project work.

VII. CONCLUSION
RISC Processor has design and implement on
Xilinx Spartan 3E FPGA tools. This easily
represented in the Xilinx ISE Design Suite. This
project is easy to understand. It executes all the
instructions in one clock cycle including jumps,
returns from subroutines and external accesses.
RISC processor of 8-bit with 35 instruction set has
design. Every instruction is executed in one clock
cycles with 4-stage pipelining. The processor
achieves higher performance lower power
dissipation & lower area.

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