DIGITAL LOGIC DESIGN

(TEN 21604)
LAB 1
Experiment Date: 17 SEPTEMBER 2021

Submission Date: 17 SEPTEMBER 2021

Weightage :

Semester: SEPT 2021

Instruction to students:

● This is a GROUP assignment.

● Complete this cover sheet and attach it to your lab report (first page).

Student declaration:

I declare that:
● This assignment is our work
● I understand what is meant by plagiarism
● My lecturer has the right to deduct my marks in the case of:
- Late submission
- Any plagiarism found in my assignment.

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Sequential Circuits:
The logic circuits whose outputs at any instant of time depend not only on the present input but
also on the past outputs are called sequential circuits.

The simplest kind of sequential circuit which is capable of storing one bit of information is called
latch. The operation of the basic latch can be modified, by providing an additional control input
that determines, when the state of the circuit is to be changed.
The latch with additional control input is called the Flip-Flop. The additional control input is either
the clock or enables input.

Different types of Flip-Flop: There are four basic types, namely, S-R, J-K, D and T Flip-Flops.

S-R Flip-Flop

Figure 1: Clocked NOR-based S-R Flip-Flop Figure 2: NAND-based S-R Flip-Flop

Figure 3: Typical wave-form in S-R Flip-Flop

Figure 4: S-R Flip-Flop characteristic Table

*CLK, S and R signals are input signals.

Qand Q: Output signals
 J-K Flip-Flop

Figure 1: J-K Flip-Flop using S-R Flip-Flop Figure 2: NAND based J-K Flip-Flop

Figure 3: Typical wave-form in J-K Flip-Flop

Figure 4: J-K Flip-Flop characteristic Table

 D Flip-Flop

Figure 1: D Flip-Flop Figure 2: NAND-based D Flip-Flop

Figure 3: D Flip-Flop characteristic Table

Component
To build any gate we need :
1. Logic Gates.
2. Wires to connect.

PROCEDURE

1. Start the simulator as directed.This simulator supports 5-valued

logic.
2. The experiment is needed to be performed on the given
structural working modules of all kinds of flip-flops.
3. The flip-flop components are in the sequential circuit drawer in
the pallet. The pin configuration is shown whenever the mouse
is hovered on any canned component of the palette or press the
'show pinconfig' button. Pin numbering starts from 1 and from
the bottom left corner (indicated with the circle) and increases
anticlockwise.
4. Click on the flip-flop component in the pallet and then click on
the position of the editor window where you want to add the
component (no drag and drop, simple click will serve the
purpose), likewise add free running clock, bit switches and bit
displays (from Display and Input drawer of the pallet, if it is not
seen scroll down in the drawer)
5. To connect any two components select the Connection menu of
palette, and then click on the source terminal and click on the
target terminal. connect all the components, connect the clock
to the clock port of the flip-flop, connect bit switches to the
proper input ports of the flip-flop, connect bit displayes to the
proper output ports of the flip-flop.
6. To see the circuit working, click on the selection tool in the pallet
then give input by double clicking on the bit switch, turn on the
case analysis feature in the simulator if the pin configuration of
that flip-flop mentions the case analysis as required, then start
the clock now check behavior of the flip-flop according the
guideline given in the objective.
Part 1 S-R Flip-Flop Result

● When no voltage is applied to Vcc1 & Vcc2. The "Clock Start" button will be
enabled.

● Next, start the clock pulse by clicking on the "Clock Start" button and after
generation of some clock pulses stop the clock pulse by clicking on the"clock
Stop" button .
● When apply high voltage to S input and low voltage to R input and set "No of
clock pulses" to 1.See the changes at output Q and at positive clock edge
● When high voltage applied to the boths inputs (S and R). The clock
pulse will start again and the outputs (Q and Q bar) will be zero. It is
"not allowed" condition.
Part 2 :JK Flip-Flop Result

● When no voltage is applied to Vcc1 & Vcc2. The "Clock Start" button will be
enabled.

● Next, start the clock pulse by clicking on the "Clock Start" button and after
generation of some clock pulses stop the clock pulse by clicking on the"clock
Stop" button.
● When high voltage applied to J input and low voltage to K input and set "No
of clock pulses" to 1.See the changes at output(Q and Q bar) at positive clock
edge.

● When high voltage applied to K input and low voltage to J input

and start the clock pulse. See the changes at output (Q and Qbar) at
positive clock edge.
● Next, when high voltage applied to both the inputs (J and K) and start
the clock pulse again. See both the outputs (Q and Q) will toggle at
positive clock edge.
Part 3 :D Flip-Flop Result

● When no voltage is applied to Vcc1 & Vcc2. The "Clock Start" button will be
enabled.
● Next, start the clock pulse by clicking on the "Clock Start" button and after
generation of some clock pulses stop the clock pulse by clicking on the"clock
Stop" button.

● When high voltage applied to D input the clock pulse start. See the
changes at output (Q and Qbar) at positive clock edge.
Part 4 : Full Adder
The circuit diagram

1.

2.
3.

4.

5.
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7.

8.
DISCUSSION

In the SR Flip Flops result,

● When we apply high voltage to S input and low voltage to R input and set
"No of clock pulses' ' to 1. It will change output Q and positive clock edge.
● When high voltage is applied to the boths inputs (S and R). The clock pulse
will start again and the outputs (Q and Q bar) will be zero. It is "not allowed"
condition.

In the JK Flip Flops result,

● When high voltage is applied to J input and low voltage to K input and set
"No of clock pulses' ' to 1. The output(Q and Q bar) will be changed at a
positive clock edge.
● When high voltage is applied to K input and low voltage to J input and start
the clock pulse. The output (Q and Qbar) will be changed at a positive clock
edge.
● when high voltage is applied to both the inputs (J and K) and start the clock
pulse again. See both the outputs (Q and Q) will toggle at positive clock
edge.

In the D Flip Flops result,

● The output Q will track the input D so long as the flip-flop remains enabled.

In the half adder result,

● 'A' and' B' are the input variables. These variables represent the two significant
bits which are going to be added
● 'Cin' is the third input which represents the carry. From the previous lower
significant position, the carry bit is fetched.
● The 'Sum' and 'Carry' are the output variables that define the output values.
● The eight rows under the input variable designate all possible combinations of 0
and 1 that can occur in these variables.
CONCLUSION

The J-K flip-flop, the most widely used flip-flop design, is considered as the universal flip-flop
circuit. Its sequential operation is the same as the S-R flip-flop with set and reset inputs. But it
has no forbidden or invalid input states of the S-R Latch, when both inputs S and R, are both
equal to logic 1. Due to its added clocked input circuitry, a JK flip-flop has four possible input
combinations, “logic 1”, “logic 0”, “no change” and “toggle”. When both inputs are low, then no
change occurs but if both are high, the output will toggle from one state to the other. It can
perform the functions of the set/reset flip-flop and has the advantage that there are no
ambiguous states. The J-K flip-flop is the most versatile of the basic flip-flops. It has the input-
following character of the clocked D flip-flop but has two inputs,traditionally labeled J and K.
Overall, this experiment is success to be done using Virtual Labs.