Applied Electronics I ASTU

Chapter 4 Field Effect Transistors

1. Introduction
Field Effect Transistors (FETs) are three terminal electronic devices used for varieties of
application, mostly similar to BJTs, such as amplifiers, electronic switches and impedance
matching circuits. However, the field effect transistor differs from bipolar junction transistor in
the following important characteristics.
1. In FETs an Electric Field is established to control the conduction path of output devices
without the need for direct contact between the controlling and controlled quantities.
2. Its operation depends upon only the flow of majority carriers, hence, unipolar device.
3. It exhibits high input impedance, typically, in many mega ohms range
4. FET’s are less sensitive to temperature variations and because of their construction they are
more easily integrated on IC’s.
5. FET’s are also generally more static sensitive than BJT’s.
Basically there are two types of field effect transistors, the Junction Field Effect Transistor
(abbreviated as JFET) and Metal-Oxide Field Effect Transistor called MOSFET.

2 Junction Field Effect Transistors (JFET)

The basic Structure of junction field effect transistor is formed from a bar of n/p SC material
called channel with a region of p/n material embedded in each side (fig. 4.1).Top and bottom of
the channel is connected through an ohmic contact to a terminal referred to as, respectively, the
drain (D) and source(S).The two embedded regions are electrically connected and form the
Gate. In practice, the channel is always lightly doped than the gate.

Figure 4.1: Junction Field Effect Transistors basic construction and their symbols

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Operating characteristics of JFET

To demonstrate the i-v characteristics of JFET lets use the following n-channel JFET circuit
layout shown on figure 4.2.For normal operation of JFET the two junctions made between the
channel and the two gates should be reverse biased. As can be seen from the circuit diagram
there are two possible conditions to control the variation of channel current, either changing the
voltage level of VGG or VDD. Depending on this there are two operating conditions.
Case1: VGS = 0, VDS increasing to some positive value
Case2: VGS < 0 and varying, VDS fixed to some value

Figure 4.2: i-v characterstics of n-channel JFET

Case1: VGS = 0, VDS increasing to some positive value
For a few volts increase in VDS, the current will increase as determined by Ohm’s Law.(See fig.
4.3a). But further increase in VDS begins to make the depletion region near the drain to be wider
and wider than the source ends because the relative voltage level near the drain is greater than
the source. This causes the channel resistance to change. See fig. 4.3(b). As VDS increases and
when it gets large enough to cause the two depletion regions touch near the drain ,pinch-off
occurs and no further increase in ID. At this point, ID maintains the saturation level defined as
IDSS and the voltage is called pinch-off voltage Vp. In this region JFETs can act as constant
current source. See fig. 4.3(c

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Case 2: VGS < 0 (VGS varying)

As VGS becomes more negative, the width of the depletion region increases uniformly across the
channel causing an increase in channel resistance. See fig. 4.4 (b). At this condition, the effect of
varying VDS is to establish depletion regions similar to those obtained with VGS=0V but a lower
level of VDS is required to reach the saturation level. If VGS is taken up to a position where the
two depletion regions are pinched, then the device will be turned off and any change in VDS will
produce no current. See fig. 4.4 (c).

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The region to the right of the pinch-off locus on the figure is the region typically employed in
linear amplifiers (amplifiers with min distortion of the applied signal) and is commonly referred
to as the constant-current, saturation, or linear amplification region. In the ohmic region JFET
can be use as variable resistors of value given as

ro
rd 
(1  VGS )2
VP

Where ro is the resistance of the channel before applying VGS and Vp is the pinch-off voltage

Figure 4.5: current voltage relationships curve

Transfer Characteristics
In a JFET the relationship of VGS (input) and ID (output) is a little more complicated, and is given
by

2
  V 
I DS  I DSS 1   GS 
 
  GS ( pinchoff ) 
V

Figure 4.6: transfer charactersitcs curve

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3. Metal Oxide Field Effect Transistors

MOSFETs have characteristics similar to JFETs and additional characteristics but they have
added features of characteristics extended to the region of opposite polarities of V GS that make
them very useful. There are two types: Depletion-Type and Enhancement-Type MOSFET.
3.1. Depletion-Type MOSFET Construction

Figure 4.7 shows the basic construction of n-channel depletion type MOSFET. The Drain (D)
and Source (S) are connected to the n-doped regions. These N-doped regions are connected via
an n-channel. This n-channel is connected to the Gate (G) via a thin insulating layer of SiO2. The
n-doped material lies on a p-doped substrate that may have an additional terminal connection
called SS.

Figure 4.7: Construction of n channel Depletion type MOSFET

Operational Characteristics of Depletion-type MOSFET

Consider the circuit given in the figure 4.8. If the VGS is set to zero and VDS is made to increase,
the effect will be to establish a current similar to that established through the channel of the
JFET. But if VGS is increase negatively, it will tend to pressure electrons toward the p-type
substrate and attract holes from the p-type substrate as shown in Fig. 4.8. Depending on the
magnitude of the negative bias established by VGS, a level of recombination between electrons
and holes will occur that will reduce the number of free electrons in the n-channel available for
conduction.

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The more negative the bias, the higher the rate of recombination. The resulting level of drain
current is therefore reduced with increasing negative bias for VGS as shown. This is called
depletion mode operation.

For positive values of VGS, the positive gate will draw additional electrons (free carriers) from
the p-type substrate due to the reverse leakage current and establish new carriers through the
collisions resulting between accelerating particles. As the gate-to-source voltage continues to
increase in the positive direction. This is called enhancement mode operation.

Figure 4.8:Operation of depletion type MOSFETs Figure 4.9: Characteristics of n-channel

3.2 Enhancement-Type MOSFET Construction

The Drain (D) and Source (S) connect to the n-doped regions. The Gate (G) connects to the p-
doped substrate via a thin insulating layer of SiO2. There is no channel. The n-doped material
lies on a p-doped substrate that may have an additional terminal connection called SS.

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Basic Operation

The Enhancement-type MOSFET only operates in the enhancement mode. Hence, VGS is always
positive and as VGS increases, ID increases. But if VGS is kept constant and VDS is increased, then
ID saturates (IDSS) after the saturation level, VDSsat is reached.

To determine ID given VGS:

where ,VT is threshold voltage or voltage at which the MOSFET turns on.
k is a constant that can be determined by using the formula:

VDSsat can also be calculated as

P-type FET

The p-channel FET is similar to the n-channel except that the voltage polarities and current
directions are reversed. And regarding response time, as electrons are more mobile than holes,
there will be considerable delay of current in p-channels compared to n-channel FETs.

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MOSFET Handling

MOSFETs are very static sensitive. Because of the very thin SiO2 layer between the external
terminals and the layers of the device, any small electrical discharge can establish an unwanted
conduction.

Protection:
• Always transport in a static sensitive bag
• Always wear a static strap when handling MOSFETS
•Apply voltage limiting devices between the Gate and Source, such as back-to-
back Zeners to limit any transient voltage

4. Biasing Techniques

There are different biasing techniques for FET circuits: some of commonly used are fixed bias,
self bias and voltage divider bias.

Fixed-bias configuration

Consider the following simplest biasing configuration circuit for the n-channel JFET,

Figure 4.10 Fixed-bias configurations. Figure 4.11 Network for dc analysis.

The coupling capacitors (C1 and C2) are open circuits for the dc analysis as is shown in figure
4.11; it would be short circuit for the ac analysis. Attempting the circuit for dc analysis:

This is shown in the above figure replacing RG with short circuit.

Applying KVL in the clockwise direction of the indicated loop of Fig. 4.11 will result in

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Since VGG is a fixed dc supply, the voltage VGS is fixed in magnitude, resulting in the notation
“fixed-bias configuration.” And the drain current ID is controlled by:

The level of ID is simply determined from a vertical line drawn by taking the fixed level of VGS
which is superimposed as a vertical line at VGS= - VGG, which is shown in below figure.

Hence, the solution for a fixed bias configuration is the intersection of the two curves in the
above figure, and this is commonly referred to as quiescent point or simply Q-point. Note in the
figure that the q-point of ID is determined by drawing a horizontal line across the intersection
point of the two curves and crossing the ID axis.

The drain-to-source voltage of the output section can be determined by applying Kirchhof’s
voltage law as follows:

Note from figure 4.12 that, the values of the source, drain, and gate voltages with respect to
ground, in relation to VDS and VGS are given by:

But VDS is given by:

So

In addition, VGS is given by:

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Self-bias configuration

Here a resistor RS is introduced in the source leg of the configuration, which is used to determine
the controlling gate-to-source voltage (VGS). This is shown in the following figure.

Figure 4.12 JFET self-bias Configuration. Fig.4.13.for

DC analysis.

Replacing the capacitors (C1 and C2) with open circuit and RG with short circuit (since IG=0A),
will result in the network of dc analysis shown in figure 4.13 above.
The current through RS is the source current IS, but IS= ID and
. For the indicated loop of figure 4.12,

 VGS  VRS  0
VGS  VRS   I D RS

Note in this case that VGS is a function of the output current ID and not fixed in magnitude as
occurred for the fixed-bias configuration. The solution of a self bias configuration is obtained by
substituting VGS into the drain current equation as follows:

Solving this quadratic equation will result in appropriate solution of ID. The graphical analysis
can also be used to determine the operating point, which is the intersection point of the device
characteristic curve and a straight line curve drawn
using the equation VGS   I D RS , as shown
in the following figure.

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Applying Kirchhof’s voltage law to the output circuit, the level of VDS can also be determined:

In addition,

Voltage Divider Bias Configuration

Figure 4.14 Voltage-divider bias arrangements. Fig.4.15. For dc analysis

As shown in Fig.4.15, all the capacitors are replaced with open circuit and the voltage VDD is
separated in to two equivalent sources, which split the input and output regions of the network.
And since IG = 0A, R1 and R2 are in series and this will result in VG to be equal with VR2.

Now the voltage VG is given by using voltage divider rule:

Applying Kirchhof’s voltage law in the clockwise direction for the indicated loop of Fig. 4.15:

Substituting , we get:

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This is an equation of a straight line, and the intersection point of this curve with the device
transfer curve will result in the operating point and the corresponding levels of ID and VGS. It
looks like the following figure:

Once the quiescent values of IDQ and VGSQ are determined, the remaining network analysis can be
performed in the usual manner.

That is,

Example 4.1: Determine IDQ and VGSQ, VD, VS, VDS, and VDG for the following for circuit

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Solution:

To determine the operating point, first find the intercepts on the ID and VGS axes on which the
straight line passes.

The intersection point of this line and the transfer curve gives us the Q-point as shown below:

IDQ = 2.4mA and VGSQ= - 1.8V.This can also be determined using the quadratic equation obtained
by substituting the value of VGS into the i-v characteristics equation.

= 16V- 2.4mA (2.4KΩ) =10.24V

= (2.4mA)(1.5KΩ) = 3.6V

or

The voltage VDG is easily determined by:

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5. Small-Signal FET model

The small-signal h-parametric model of FET is represented as in the figure 4.16.

D
G D
+
G FET vgs gmvgs rd
-
S S
S

Figure 4.16 FET small signal model

Input impedance ( ri)
As the gate current (IG) is nearly zero, we can assume the input impedance of FET to be very
large.

Trans-admittance or Trans-conductance(gm)

For JFET’s

, let

For MOSFET’s

Output impedance (rd)

, where yos is defined as the output-admittance of the transistor

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Example 1

For the self-bias n-channel JFET shown in the following figure, calculate the

a) input and output impedances

b) voltage gain. Assume, yos=20μS

VDD =20V

RD 3.3KΩ
C2
v0
C1
IDSS=8mA Z0
vi VP= -6V

Zi

RG 1MΩ RS 1KΩ C3

DC Analysis;

, but from loop 1, we get

0 ,

Since ,

From loop 2,

And

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AC Analysis

= = 1.51mS

Ac equivalent circuit

Shorting all DC sources and capacitors

vi v0
+

RG vgs gmvgs rd RD

a) Input impedance,

b) Output impedance,

 1 
z o  RD rd  3.3K    3.3K
 20S 

c) Voltage gain,

  g m RD rd   1.5mS x 3.3K 50K   4.98

VO
AV 
Vin

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