FPGA Implementation of 32-bit RISC-V Processor

with Web-Based Assembler-Disassembler

Etki Gür, Zekiye Eda Sataner, Yusuf H. Durkaya, Salih Bayar
Dept. of Electrical and Electronics Engineering
Faculty of Engineering, Marmara University
Göztepe, 34722 Istanbul, Turkey

{etkigur, zekiyeeda.sataner, yusufdurkaya}@marun.edu.tr

[email protected]

Abstract—In this study, a pure structural implementation implementation is single core, in-order, non-bus based, single
based, 32-bit open source RISC-V processor is presented. The cycle architecture that supports RV32I base integer instruction
proposed processor is designed using Verilog and it is im- set fully functionally. One of our goals was to decrease the
plemented on Cyclone IV 4CE115 FPGA device available on
Altera DE2-115 Board. Additionally, web-based assembler and power needed and lower the cost. It is also targeted to create a
disassembler tools are developed and published as a part of non-complex algorithm. The scope of application differs from
this project. Before using the target RISC-V processor, the user embedded systems to signal processing, sensor technology and
can generate machine code using the web-based assembler tool. various other areas. After we noticed the lack of an instruction
Then, the generated machine code can be downloaded onto test system for RISC-V, we have decided to develop a web-
the RISC-V processor using UART. The web-based assembler
and disassembler tools are developed with technologies such as based assembler and disassembler. To the best of our knowl-
HTML5, CSS and JavaScript. The proposed processor is a fully edge, we are the first, who develop a web-based assembler
functional processor that uses RV32I base integer instructional and disassembler for RISC-V architecture. For the connection
set with 37 instructions. The amount of hardware resources used between web-based assembler-disassembler and the Field Pro-
by the whole processor circuit is about 43.7% of the Cyclone IV grammable Gate Array (FPGA), the Universal Asynchronous
4CE115 FPGA device and the maximum frequency achieved for
the processor is 150MHz without using any timing constraint. Receiver-Transmitter (UART) protocol was used.
This paper is presented as follows: Section II introduces
I. INTRODUCTION RISC-V(RV32I) instruction set and various basic instructions.
The integrated circuit technology has developed monumen- Section III explains the architecture and processor design.
tally in the last few decades. Thanks to these developments, Section IV gives insight on simulations and FPGA design.
there has been drastic changes in chip technology and imple- Last but not least, section V explains the conclusion and future
mentations in a single chip are widespread now. With these, work.
the significance of Instruction Set Architectures (ISAs) has
II. RV32I BASE I NTEGER I NSTRUCTION S ET
increased rapidly. Reduced Instruction Set Computer RISC
based ARM architectures already dominated the mobile sys- A. Characteristics
tems like Android and Apple and MIPS based architectures RV32I has four core instruction formats (R/I/S/U). All are
used by most gaming consoles RISC-V is a new open ISA a fixed 32 bits in length and must be aligned on a four-byte
based on RISC and it is developed to support research and boundary in memory. Immediate instruction type is split into
education [1]. Unlike other ISAs, RISC-V is an open source five different immediate types (I/S/B/U/J). Sign extension uses
instruction set architecture first developed by University of the left-most bit in instruction. There are a further two variants
California, Berkeley and everyone is allowed to design and of the instruction formats (SB/UJ) based on the handling of
manufacture. RISC-V is designed for modern devices like immediate values [5].
mobile phones, small embedded systems and cloud computers It contains 47 different and unique instructions. RV32I
[2]. It is also designed to support 32-bit, 64-bit and 128- contains 47 unique instructions, though an implementation
bit addresses. Compared to ARM microprocessors, RISC-V might cover the eight SCALL/SBREAK/RD [1] instructions
is faster and has small footprint size.With all these features, with a single SYSTEM hardware instruction that always traps,
RISC-V can replace ARM microprocessors [3]. reducing hardware instruction count to 40 total.
In this work, we represent a hardware design architecture for
RV32I base integer system for 32-bit addresses only. RV32I B. Register organization
is a form of RISC-V that was designed to be adequate for There are 31 general-purpose registers x1–x31, which hold
generating compiler targets and supporting modern system integer values. Register x0 is hardwired to the constant 0.
environments [4]. In addition, a minimal hardware required Standard software calling convention uses register x1 to hold
was taken into consideration while designing the ISA. The the return address on a call.

978-1-5386-7212-9/18/$31.00 ©2018 IEEE

 TABLE I III. DEVELOPMENT AND IMPLEMENTATION OF
INSTRUCTIONS FORMAT RISC-V ON FPGA
32-bit designs are sufficient for embedded applications that
do not require complex processing. A single cycle design was
deemed suitable for this study. In the following sections, the
design will be explained in detail.
A. Overview
There are various modules that make a single cycle datapath.
All modules run at the same time in a single cycle, the
control signals determine the progression that will produce
the required output. After the instruction is fetched from the
instruction memory, the process starts with decode and control
It is also possible to encode an ISA with 16 registers but stage [6].
it lowers the efficiency and increases the instruction count. To
avoid intermediate instruction sizes RV32I encoded with 32
registers.

C. Instructions
RV32I instructions are classified based on the following in-
struction bits; instruction[30], function3[14:12], Opcode[6:0].
It has 7 different instruction category and every category is
explained in Table I. Fig. 1. Processor Design

TABLE II Register file contains 32 registers from 0 to 31. The

INSTRUCTION TYPE, OPCODE AND DEFINITION zero register (0th register) has a constant value of 0. Also,
this module comprises the register addressing and read and
CATEGORY OPCODE INSTRUCTION DEFINITION write logic. ALU deals with arithmetic register-register and
Integer 0010011 addi, slti, sltiu, addi rd, rs1, imm register-immediate operations for this module. ALU does not
Register- ori, xori, andi, Adds rs1 and imm
Immediate slli, srli, srai and then it writes the calculate the address for jump and branch operations. For
Instructions answer to the rd branch instructions, ALU only calculates the condition. Sign-
(I-Type) Extension, Bit separate and Merge unit provides properly
Integer 0110011 add, sub, sll, slt, add rd , rs1, rs2
Register- sltu, xor, srl, sra, Adds rs1 and rs2 and reordered and sign extended immediate operands for ALU.
Register or, and then it writes the an- One of the operands comes from this unit whilst the other
Operations swer to the rd one comes from Register Bank. The value is selected in this
(R-Type)
Integer Com- 0110111 lui lui rd,imm
module according to the appropriate instruction. The memory
putational 0010111 auipc Load immediate into operation control logic module has been added to generate
Instructions upper bits of word various store/load instructions. Thanks to this module memory
(U-Type)
Unconditional 1101111 jal, jalr jal rd,imm
reading and recording is performed.
Jumps (UJ, Jumps to adress and
I-Type) place return adress to
B. Micro-Architecture
the rd In general, the system consists of fetch, decode and control
Conditional 1100011 beq, bne, blt, beq rs1,rs2,imm
Branches bltu, bge, bgeu If rs1 and rs2 is equal,
stage. Fetch stage calculates the current program counter and
(SB-Type) branchs into the im- predicts the next PC. It keeps the PC value in the 32-bit register
mediate value adress and calculates the next PC value as PC + 4. However, when
Load 0000011 lw, lh, lb, lhu, lbu lw rd,rs1,imm
Instruction Adds rs1 and imm
this process is performed, what is the instruction is examined,
(I-Type) and then writes the and if the jump and branch processes are performed, the PC
corresponding value value is adjusted accordingly. After the instruction is decoded,
from memory to rd
the control stage determines the progress.
Store 0100011 sw, sh, sb sw rs1,rs2,imm
Instruction Adds rs1 and imm During the decode stage, the instructions taken from the
(S-Type) and then writes the instruction memory are resolved. This analysis will determine
value of rd to the cor- the signals to go to the control process. They are the key
responding adress in
memory determinants of progress in a single cycle. The control signals
opcode(0 to 6 bits), funct3(12 to 14 bits) and the 30th bit of
the instruction are processed in the control stage. 12 signals
 Fig. 2. Micro architecture of RV32I ISA based RISC-V

are output from the control stage depending on the design. signals ALU output is written to the register file or used to
For example, the 4-bit X signal for ALU control specifies determine the address in the data memory or to determine the
the operations to be performed in the ALU connected to the address in the PC. The PC specifies the address of the next
instruction. The MemRead signal also specifies whether to instruction.
read from memory. It controls the modules by working in IV. SIMULATION AND FPGA IMPLEMENTATION
a similar way on the remaining signals.
Using the web-based assembler and disassembler that we
Depending on the instructions, the changed instantaneous have developed, we are giving inputs to the program. Com-
values are converted to 32-bit so that they can be processed munication between this system and FPGA provided by the
by the Sign-Extension module. It is transmitted to the relevant UART. The given input goes to FPGA and simulation works
module. The selected operation is performed by two 32 bit based on the input. The proposed processor is designed using
inputs to the ALU module by ALU control. The output is Verilog and it is implemented on Cyclone IV 4CE115 FPGA
either sent to the memory operations, or sent to the Register device available on Altera DE2-115 Board.
File for writing to the register depending on the control signals.
Memory operations load and store instructions transfer a value A. Web-Based Assembler-Disassembler
between the registers and memory. LW, LH, LB, LBU, LHU Due to the lack of a web-based RISC-V Assembler and
instructions load 8-bit, 16-bit and 32-bit value from memory Disassembler, people spend unnecessary time translating the
into rd. 8-bit and 16-bit values load from memory, then sign- assembly code to machine code. The application that takes
extends or zero extends to 32-bits before storing in rd. SW, the RISC-V Assembly Code as an input from a ’text area’
SH, SB instructions store 32-bit, 16-bit, and 8-bit values from in a Web-site then converts it to the Machine Code as an
the low bits of register rs2 to memory [7]. output was developed.This application sends the generated
If the operation is to be summarized, the PC calculates the machine code into the FPGA via USB using UART-serial
address of the instruction to be executed. The inputs required communication in local network. A website that completes
for the operation of the modules are found by the control bidirectional translation between machine code and assembly
unit. The values from the register file are reached to get language was published.
the register values to be used for instruction (rs1, rs2, rd).
The inputs required for ALU operations are selected from B. Simulation
the multiplexers. The input selection is again determined by All the simulation procedures have been done in Logisim.
the inputs provided by the control unit. According to control Logisim is an educational tool for designing and simulating