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Fifocntrl

This document describes a VHDL code for a FIFO controller. It contains the entity and architecture for the FIFO controller. The entity defines the inputs such as clock, reset, read and write signals. The architecture contains processes that handle the state logic for read and write pointers based on events like read, write or no operation. It uses pointers to track the read and write locations in the FIFO and generate control signals like full and empty based on pointer values.

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Jose Guillermo Gonzalez
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25 views2 pages

Fifocntrl

This document describes a VHDL code for a FIFO controller. It contains the entity and architecture for the FIFO controller. The entity defines the inputs such as clock, reset, read and write signals. The architecture contains processes that handle the state logic for read and write pointers based on events like read, write or no operation. It uses pointers to track the read and write locations in the FIFO and generate control signals like full and empty based on pointer values.

Uploaded by

Jose Guillermo Gonzalez
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Date: April 20, 2023 fifo_ctrl.

vhd Project: Lab06_fifo

1 LIBRARY IEEE;
2 USE ieee.std_logic_1164 .all;
3 USE ieee.numeric_std .all;
4 ------------------------------------------------------------------------------
5 ENTITY fifo_ctrl IS
6
7 GENERIC(addr_width : natural := 4);
8
9 PORT
10 (
11 clck : IN STD_LOGIC ;
12 reset : IN STD_LOGIC ;
13 rd : IN STD_LOGIC ;
14 wr : IN STD_LOGIC ;
15 empty : OUT STD_LOGIC ;
16 full : OUT STD_LOGIC ;
17 w_addr : OUT STD_LOGIC_VECTOR (addr_width -1 DOWNTO 0);
18 r_addr : OUT STD_LOGIC_VECTOR (addr_width -1 DOWNTO 0);
19 r_addr_next : OUT STD_LOGIC_VECTOR (addr_width -1 DOWNTO 0)
20 );
21
22 END ENTITY fifo_ctrl ;
23 ------------------------------------------------------------------------------
24
25 ARCHITECTURE arch OF fifo_ctrl IS
26
27 SIGNAL w_ptr_reg , w_ptr_next , w_ptr_succ : STD_LOGIC_VECTOR (addr_width -1
DOWNTO 0);
28 SIGNAL r_ptr_reg , r_ptr_next , r_ptr_succ : STD_LOGIC_VECTOR (addr_width -1
DOWNTO 0);
29 SIGNAL full_reg , full_next : STD_LOGIC ;
30 SIGNAL empty_reg , empty_next : STD_LOGIC ;
31 SIGNAL wr_op : STD_LOGIC_VECTOR (1 DOWNTO 0);
32 SIGNAL wr_en : STD_LOGIC ;
33
34 BEGIN
35
36 PROCESS(clck,reset)
37 BEGIN
38 IF(reset = '1') THEN
39 w_ptr_reg <= (OTHERS => '0');
40 r_ptr_reg <= (OTHERS => '0');
41 full_reg <= '0';
42 empty_reg <= '1';
43
44 ELSIF (rising_edge (clck)) THEN
45 w_ptr_reg <= w_ptr_next ;
46 r_ptr_reg <= r_ptr_next ;
47 full_reg <= full_next ;
48 empty_reg <= empty_next ;
49 END IF;
50 END PROCESS;
51
52 ----- sucesive pointer values
53 w_ptr_succ <= STD_LOGIC_VECTOR (unsigned (w_ptr_reg ) + 1);
54 r_ptr_succ <= STD_LOGIC_VECTOR (unsigned (r_ptr_reg ) + 1);
55
56 -- next state logic for read an write pointers
57 wr_op <= wr & rd;
58
59 PROCESS(w_ptr_reg , w_ptr_succ , r_ptr_reg , r_ptr_succ , full_reg ,empty_reg , wr_op)
60
61 BEGIN
62
63 CASE wr_op IS
64

Page 1 of 2 Revision: Lab06_fifo


Date: April 20, 2023 fifo_ctrl.vhd Project: Lab06_fifo

65 WHEN "00" => -- no op


66
67 w_ptr_next <= w_ptr_reg ;
68 r_ptr_next <= r_ptr_reg ;
69 full_next <= full_reg ;
70 empty_next <= empty_reg ;
71
72 WHEN "01" => -- read
73
74 w_ptr_next <= w_ptr_reg ;
75
76 IF(empty_reg /= '1') THEN
77 r_ptr_next <= r_ptr_succ ;
78 full_next <= '0';
79
80 IF(r_ptr_succ = w_ptr_reg ) THEN
81 empty_next <= '1';
82 ELSE
83 empty_next <= empty_reg ;
84 END IF;
85
86 ELSE
87 r_ptr_next <= r_ptr_reg ;
88 full_next <= full_reg;
89 empty_next <= empty_reg ;
90 END IF;
91
92 WHEN "10" => --write
93 r_ptr_next <= r_ptr_reg ;
94
95 IF(full_reg /= '1') THEN
96 w_ptr_next <= w_ptr_succ ;
97 empty_next <= '0';
98
99 IF(w_ptr_succ = r_ptr_reg ) THEN
100 full_next <= '1';
101 ELSE
102 full_next <= full_reg;
103 END IF;
104
105 ELSE
106 w_ptr_next <= w_ptr_reg ;
107 full_next <= full_reg;
108 empty_next <= empty_reg ;
109
110 END IF;
111
112 WHEN OTHERS => -- WRITE/READ
113 w_ptr_next <= w_ptr_succ ;
114 r_ptr_next <= r_ptr_succ ;
115 full_next <= full_reg ;
116 empty_next <= empty_reg ;
117
118 END CASE;
119
120 END PROCESS;
121
122 w_addr <= w_ptr_reg ;
123 r_addr <= r_ptr_reg ;
124 full <= full_reg ;
125 empty <= empty_reg ;
126 r_addr_next <= r_ptr_next ;
127
128 END ARCHITECTURE ;

Page 2 of 2 Revision: Lab06_fifo

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