ISSN 2321 3361 © 2017 IJESC

Research Article Volume 7 Issue No.8

Design and Implementation of Parallel Bit Reversal on FFT by

using Verilog HDL
Ravi L.S1, Chithra .C .P 2, Farzana Parveen B.C3
Assistant Professor1, 3, Student2
Department of ECE
RIT, Hassan, Karnataka, India1, 2
SJMIT, Chitradurga, Karnataka, India3

Abstract:
Bit-reversal is an essential part of the fast Fourier transform. However, compared to the amount of works on FFT architectures,
much fewer works are dedicated to bit-reversal circuits until recent years. In this brief, the minimum latency and memory required
for calculating the bit-reversal of continuous-flow parallel data are formulated. The proposed circuit is simple and efficient for
reordering the output samples of parallel pipelined FFT processors. The proposed approach can be Implemented using Verilog
HDL and Simulated by Modelsim 6.4 c. Finally it‟s synthesized by Xilinx tool.

Keywords: FFT, Commutators, S-box, memory, Buffer group, radix 2.

I.INTRODUCTION to calculate DFT efficiently. DSP processors have special

architectural provisions to implement FFT algorithms
The fast Fourier transform is one of the most important and efficiently. FFT is extensively utilized in the areas of DSP
fundamental algorithms in the digital signal processing such as filtering, spectral analysis, etc. FFT plays a significant
area. It is a fast computational algorithm to implement the task in present digital communication systems for instance
discrete Fourier transform and it has been widely used in DVB and OFDM systems. For the sequence x(n), N point DFT
various applications such as spectrum analysis, wireless can be expressed by equation
communications and imaging systems. Many variants of the
FFT algorithm have been developed, such as radix-2 and N−1

radix-4 FFT. Since arithmetic operations significantly XK = x n WNnk k = 0,1, … . N − 1

contribute to overall system power consumption, SRFFT is a n=0
good candidate for the implementation of a low-power FFT Where,
processor. The FFT computation requires an indexing scheme X (k) = frequency-domain sequences
at each stage to address input/output data and coefficient x (n) = time-domain sequence
multipliers properly. When the fast Fourier transforms is WNnk =Twiddle factor
2π
executed using an in-place method, the input or output data
WNnk = e−j N kn
must be accessed in a digit-reversed order. The reversal 2π 2π
procedure rearranges the address sequence used to access data = cos ( kn) – j sin ( kn)
N N
by reordering the bits of a binary representation of the address
according to the radix of the FFT. The bit reordering procedure The essential computational component of FFT is called
can be realized in firmware, software or hardware. butterfly. Every butterfly unit needs complex multiplications
and also complex additions. For the computation of FFT,
II.EXISTING SYSTEM decomposition of the N-point into repetitive micro operations
is done. This is known as butterfly operation. During hardware
Several bit-reversal circuits for parallel pipelined FFT 0 implementation of FFT, if a individual butterfly structures is
architectures have also been presented. A bit-reversal circuit implemented on the chip, this butterfly unit will perform all the
for 8-parallel data is proposed, but the complexity of the circuit computation recursively. The DFT calculation demands a
is high. For the P-parallel N-point FFT architecture, a total complex implementation. The 0size0 of butterfly is „r‟, the
memory of N x N=P is enough to carry out the reordering task. resulting FFT0is known as „radix-r‟ FFT. In the Fig 2.2 when
The reordering circuit is designed for a specific FFT and uses the inputs area and b the output is given by equation.
slightly more than N memory words. The first circuit
calculates the bit-reversal of parallel data using a total memory A=a + WʹNb
of N. However, none of the existing works have derived the
minimum latency and memory required for calculating the B=a - WʹNb
parallel bit-reversal.
The direct estimation of DFT is found to be especially very
III. PROPOSED SYSTEM complicated and because of this reason FFT algorithm is used.
To minimize the number of computation FFT algorithm uses a
FFT algorithms are basically called Fast Fourier Transform divide and conquer approach recursively.
algorithms and it is important in the area of DSP which is used

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 The P-Path input segments are switched to proper buffer banks
by the input commutator, and the P buffer banks‟ outputs are
switched to proper output paths by the output commutator.

Buffer Group

The buffer group consists of P buffer banks and one S-

generator. Each buffer bank reorders P segments according to
the S-generator. The buffer bank is composed of P -1 buffer
cells. The buffer length of each buffer cell is N/P 2, leading to a
total memory of N (P-1)/P2. The buffer cell bypasses the input
to the output when the signal S is greater than the cell number
n. Otherwise, it outputs the segment which is stored in the
buffer and stores the input segment. As a result, the buffer
bank outputs the segment stored in the buffer cell whose
number is equal to signal S. The buffer cells whose number is
less than the signal S remain the same, and the buffer cells
whose number n is greater than the signal S shifts segment to
the buffer cell (n - 1).

Figure.1. FFT Butterfly diagram

Selecting FFT radix is the first step of the algorithmic level. It

is mainly dependent on factors such as speed, power and area
designed for different number of transistors. Each of the
algorithms is identical in the structural arrangement but
differing merely in the core computation of butterfly. Radix-2
is an FFT algorithm within which divide and conquer method
is used. The simplest FFT algorithm is Radix-2 algorithm its
butterfly structure is shown in the Fig 2.3. The radix-2 Figure.2. Buffer Bank
algorithm implemented either in time or frequency domains are
considered to be one of the simplest algorithms. The value of S-GENERATOR
„N‟ be should be chosen so that N= .The resulting DFT As a result, the buffer bank outputs the segment stored in the
obtained after successive decomposition will be of size N=2. buffer cell whose number is equal to signal S. The buffer cells
Therefore this type of algorithms is known as radix-2 whose number is less than the signal S remain the same, and
Algorithm, or the radix of this algorithm is 2. The proposed the buffer cells whose number n is greater than the signal S
circuit is composed of a sub-bit reversal module, input and shifts segment to the buffer cell (n - 1). The overall
output commutator, and a group of P buffer banks. The bit- implementation is as shown in Figure 3
reversal permutation is accomplished by cascading two sub-
permutations, sub-bit-reversal and segments reordering, which
are realized by the sub-bit reversal module and buffer group,
respectively. These P x P segments are reordered by the P
buffer banks, each of which consists of P - 1 buffer cells
connected in series. The input and output commutator are also
adopted to access the P buffer banks efficiently.

Sub-Bit Reversal Module

The sub-bit-reversal module consists of P bit-reversal circuits,

each of which calculates N/P2-point bit-reversal. The circuit is
adopted to implement these N/P2-point bit-reversal circuits,
except that the P circuits share the same multiplexer generator.
The N/P2-point bit reversal circuit is composed by cascading
[m/2] basic circuits.

Input and Output Commutators

After been processed by the sub-bit-reversal module, every

N/P2 samples in each path are organized into a segment. As
one buffer bank can only accept one input and generate one Figure.3.Efficient circuit for P-parallel bit-reversal
output at a time, the input and output commutator are adopted.

International Journal of Engineering Science and Computing, August 2017 14644 http://ijesc.org/
IV. RESULTS BUFFER GROUP

PARALLEL BIT-REVERSAL Buffer group is the combination of buffer cells. The buffer
group consists of 8 inputs, 8 outputs, 4 bit selection line i.e. Sel
The overall output waveform of the parallel bit-reversal and the output of buffer group are shown in Figure 6.
architecture is shown in Figure 2. Clk and Rst are the control
signals. In0 – In7 are the inputs that are given and Out0 - Out7
are the main outputs.

Figure .6. Output snapshot of Buffer group

The buffer group uses S-generator to generate the data and it is

Figure.4. Output snapshot of parallel bit-reversal circuit then connected to the buffer bank. The RTL schematic of
buffer group is shown in Figure 7.
The RTL schematic is generated after the optimization and
technology targeting phase of the synthesis process. The
schematic shows a representation of the design in terms of
logic elements optimized to the target Xilinx device or
"technology"; for example, in terms of of LUTs, carry logic,
I/O buffers, and other technology-specific components.
Viewing this schematic allows you to see a technology-level
representation of your HDL optimized for a specific Xilinx
architecture, which might help you discover design issues early
in the design process. The Figure 5 shows the technology
schematic of parallel bit-reversal circuit.

Figure.7. RTL Schematic of Buffer group

SUB-BIT REVERSAL MODULE

The sub-bit reversal module consists of P bit-reversal circuits,

each of which calculates N/P2- point bit reversal. The data
which is given should be transferred to the next block which is
done in Initial block. The waveform is shown in Figure 8.
Figure.5. RTL schematic of parallel bit-reversal circuit

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 V. ADVANTAGES AND APPLICATIONS

ADVANTAGES
 It uses the minimum memory that is required for
calculating the parallel bit-reversal.
 The circuit achieves the minimum latency.
APPLICATIONS

 Spectrum analysis:
The analysis of electrical signals, otherwise known as signal
analysis, is a fundamental challenge for virtually all electronic
design engineers and scientists. While it provides valuable
insight into a signal‟s properties, signal analysis is only as
good as the instrument with which it is performed. To fully
understand the performance of a system, a signal must also be
analyzed in the frequency domain. This is exactly what the
spectrum analyzer does.

 Wireless communications:
Figure. 8. Output snapshot of point bit-reversal Orthogonal Frequency Division Multiplexing is a popular
scheme for high data rate wireless transmission. OFDM may
Sub-bit reversal is the initial block which consists of 8 buffer combine with antenna array at the transmitter and receiver to
units. The RTL schematic of the sub-bit reversal module is improve the system capacity on frequency selective and time
shown in the Figure 9. variant channel, resulting in a Multiple Input Multiple Output
configuration.

 Imaging systems:
The Fourier Transform is an important image processing tool
which is used to decompose an image into its sine and cosine
components.

V. CONCLUSION

This brief formulates the minimum latency and memory

required for calculating the bit-reversal of continuous-flow
parallel data. An efficient circuit for parallel bit-reversal is also
proposed. The circuit not only achieves the lowest latency but
also uses the minimum memory. The proposed architecture is
Figure.9.RTL schematic of Sub-bit reversal module simple and generic. Moreover, the circuit supports continuous
flow data and is very suitable for reordering the samples of
S-GENERATOR parallel pipelined FFT processors.
S-generator is the selection line generator for the buffer group.
The S-generator has input, selection line and buffer bank as A. Future Work
shown in the Figure 10.
Along with the minimum latency and memory required for
calculating the bit-reversal of continuous-flow parallel data,
this design can be further enhanced to reduce the area.

VI. REFERENCES

[1]. Y.-N. Chang, “An efficient VLSI architecture for normal

I/O order pipeline FFT design,” Circuits and Systems II:
Express Briefs, IEEE Trans., vol. 55, no. 12, pp.1234–1238,
2008.

[2]. F. Kristensen, P. Nilsson, and A. Olsson, “Flexible

baseband transmitter for OFDM, ”in Proceedings of the
IASTED International Conference on Circuits, Signals, and
Systems (Cancun, Mexico), 2003.

[3]. W. Gao, S. Kwong, and H. Sang, “Low-cost memory data

scheduling method for reconfigurable FFT bit-reversal
circuits,” Electronics Letters, vol. 51, no. 3, pp. 217– 219,
Figure.10.Output snapshot of S-generator 2015.

International Journal of Engineering Science and Computing, August 2017 14646 http://ijesc.org/
[4] T. S. Chakraborty and S. Chakrabarti, “On output reorder
buffer design of bit reversed pipelined continuous data FFT
architecture,” in Proc. IEEE Asia Pac. Conf. Circuits Syst.
(APCCAS), 2008, pp. 1132–1135.

[5]. C. Yu, “Flexible and low-complexity bit-reversal scheme

for serial-data FFT processors,” Electronics Letters, vol. 51,
no. 4, pp. 328–330, 2015.

[6]. M. Garrido, J. Grajal, and O. Gustafsson, “Optimum

circuits for bit reversal,” Circuits and Systems II: Express
Briefs, IEEE Trans., vol. 58 no. 10, pp. 657–661, 2011.

[7]. S. Yoshizawa, A. Orikasa, and Y. Miyanaga, “An area and

power efficient pipeline FFT processor for 8x8 MIMO-OFDM
systems,” in Proc. IEEE int. Symp. CircuitsbSyst., 2011, pp.
2705–2708.

[8]. M. Garrido, J. Grajal, M. Sanchez, and O. Gustafsson,

“Pipelined radix- 2k feed forward FFT architectures,” Very
Large Scale Integration (VLSI) Systems, IEEE Trans., vol. 21,
no. 1, pp. 23–32, Jan 2013.

[9]. K.-J. Yang, S.-H. Tsai, and G. C. Chuang, “MDC

FFT/IFFT processor with variable length for MIMO-OFDM
systems,” Very Large Scale Integr. (VLSI) Syst., IEEE Trans.,
vol. 21, no. 4, pp. 720–731, 2013.

[10]. S.-G. Chen, S.-J.Huang, M. Garrido, and S.-J.Jou,

“Continuous-flow parallel bit-reversal circuit for MDF and
MDC FFT architectures,” Circuits and Systems I: Regular
Papers, IEEE Trans., vol. 61, no. 10,pp. 2869–2877, Oct 2014.

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