DESIGN OF ANALOG: DIGITAL VLSI CHRCUITS FOR TELECOM MUNICATIONS AND SIGNAL PROCESSING Je ERA | VANES TST, EarsDESIGN OF ANALOG-DIGITAL VLSI CIRCUITS FOR TELECOMMUNICATIONS AND SIGNAL PROCESSING Second Edition José E. Franca and Yannis Tsividis, editors Prentice Hall, Englewood Cliffs, New Jersey 07632What LSI did for computers in the 1970's, VLSI is doing for telecommunications and signal processing in the 1990's. Entire systems of high complexity, often incorporating both analog and digital functions, are being put on a single chip, thus attaining reduced size, cost, and power dissipation, while at the same time improving performance or even enabling new applications. This volume is devoted to techniques that make this possible. It is divided into two parts, one devoted to circuits, and another devoted to systems. Many representative applications will be found in the systems part. The precursor of this book, entitled Design of MOS VLSI Circuits for Telecommunications and edited by Tsividis and Antognetti in 1985, reflected the contents of a course by the same title, offered for the first time in Italy in 1985. Since then, the course was offered four more times (in Italy, Spain, Finland, and Portugal), with the lectures each time being updated to reflect new advances, and new lectures being introduced. By the time the course was offered in 1990 at the Instituto Superior Técnico in Lisboa, Portugal, it had changed to such an extent that the publication of a new book was in order. This volume reflects the contents of this latest offering, and in fact includes further updating changes made by the authors all the way to early 1992. Reflecting the advanced nature of the course and its attendees, the book is addressed to experienced readers. We want to thank our authors for making available their expertise to the course attendees and our readers. We also want to thank the course attendees for helping shape the course and the book. Finally, we want to thank Miss Ana Marcelino and Miss Salvina Ribeiro whose tireless work made possible a professional appearance without sacrificing the timeliness of the volume. J.E. Franca Y. TsividisContributors ADAMS, P.S., BT Laboratories, Ipswich, England FRANCA, J.E., Instituto Superior Técnico, Lisboa, Portugal GOPINATHAN, V., Texas Instruments, Dallas, Texas, U.S.A. GRAY, P.R., University of California, Berkeley, California, U.S.A. GRUGER, K., Deutsche Thomson Brandt GmbH, Villingen, Germany HEATLEY, DJ.T., . BT Laboratories, Ipswich, England KLAASSEN, F.M., Philips Research Laboratories, Eidhoven, The Netherlands MALOBERTI, F., University of Pavia, Pavia, Italy MARTINS, R.P., Instituto Superior Técnico, Lisboa, Portugal NEFF, R.R., University of California, Berkeley, California, U.S.A. PIRSCH, P., University of Hannover, Hannover, Germany RAPELI, J., Nokia Mobile Phones, Ouw, Finland ROTHERMEL, A., Deutsche Thomson Brandt GmbH, Villingen, Germany SCHEMANN, H., Deutsche Thomson Brandt GmbH, Villingen, Germany SCHWEER, R., Deutsche Thomson Brandt GmbH, Villingen, Germany SEDRA, A., University of Toronto, Ontario, Canada SENDEROWICZ, D., Synchrodesign Inc., Berkeley, California, U.S.A. SNELGROVE, M., University of Toronto, Ontario, Canada TEMES, G.C., Oregon State University, Corvallis, Oregon, U.S.A. TSIVIDIS, Y., National Technical University of Athens, Athens, Greece VITTOZ, E.A., Centre Suisse d'Electronique et de Microtechnique (CSEM), Neuchatel, Switzerland WEHBERG, T., University of Hannover, Hannover, Germany WEINBERGER, G., Siemens A.G., Munich, Germany vicove CONTENS vse: 1, Circuit-Level Models for VLSI Components EM. Klaassen Introduction 1 1. MOSFET Modelling, 1 1.1. Threshold voltage, 1 1.2. Drain current at strong inversion, 4 1.3. Subthreshold current, 6 1.4. Saturation mode, 7 1.5. Charges and capacitances, 9 1.6. Parasitics and model extensions, 0 2. Bipolar Modelling, 11 2.1. Carrier transport, 11 2.2. Collector current, 12 2.2.1. Charge control approach, 12 2.2.2. Carrier control approach, 13 2.3, Base current, 14 2.4. Charges and capacitances, 14 2.5. Quasi-saturation, 16 2.6. Parasitics and model extensions, 7 3. Parameters, 20 3.1. Parameter acquisition, 20 3.2. Geometry and process dependence, 21 3.3. Statistics of parameters, 22 References, 23 viiviii Contents 2. CMOS Operational Amplifiers 21 Daniel Senderowicz de 2. 6. 7. General Considerations for VLSI of Amp Design, 27 ‘The Differential Circuit Approach, 28 ‘The Number of Internal Stages, 31 Cascode Op Amps, 31 4.1. The folded-cascode OTA, 34 4.2. The telescopic-cascode OTA, 35 4.3. Comparisons between the folded and telescopic cascode OTAs, 36 43.1. Simulations, 37 4,4, Single-ended versions of the cascode OTAs, 38 Multiple Stage Op Amps, 39 5.1. The differential class-A two stage op amp, 40 5.2. The resistor driving class-AB op amp, version I, 42 5.3. The resistor driving class-AB op amp, version II, 44 Bias Circuits, 47 Layout Techniques, 49 References, 51 3. Micropower Techniques 53 Eric A. Vittoz iy 2. Introduction, 53 Technology, 54 Devices, 55 3.1. MOS transistors, 55 3.2. CMOS compatible bipolar transistors, 67 3.3. Passive devices, 69Contents ee ee 3.4, Parasitic effects, 70 4. Basic Circuit Techniques, 70 4.1, Current mirrors, 70 4.2. Differential pair, 71 4.3. Voltage gain cells, 72 4.4. Low-voltage cascoding, 75 4.5. Current references, 77 4.6. Voltage references, 78 4.7. Analog switches, 79 4.8. Dynamic CMOS gates, 80 5. Examples of Building Blocks, 81 5.1. Operational transconductance amplifiers (OTAs), 81 5.2. Quartz crystal oscillators, 87 5.3. Sequential logic building blocks, 91 6. Conclusions, 92 7. References, 93 4, Dynamic Analog Techniques 97 Eric A. Vittoz 1, Introduction, 97 2. Sample-and-Hold, 97 2.1. Principle, 97 2.2. Transfer function, 98 2.3. Noise sampling, 99 2.4. Charge injection by the switch, 101 2.5. Sample-and-hold used as a time differentiator (autozero circuit), 105 3. Offset Compensation of Operational Amplifiers, 108 3.1. First order compensation, 108 3.2. Compensation by a low-sensitivity auxiliary input, 108 4. Dynamic Biasing of CMOS Inverter-Amplifiers, 112x Contents —— 5. Dynamic Comparators, 114 5.1. Basic circuit, 114 5.2. Multistage comparators, 117 6. Dynamic Current Mirrors, 118 6.1. Principle and limitations, 118 6.2. Examples of practical implementations, 120 7. Conclusion, 122 8. References, 122 5. Optical Receivers 125 David J.T. Heatley 1, Introduction, 125 2. Receiver Design, 126 3. Receiver bandwidth, 127 3.1. Low impedance receiver, 127 3.2. High impedance receiver, 128 3.3. Transimpedance receiver, 130 4, Receiver Noise, 132 4.1. Photodiode noise, 132 4.2. Resistor noise, 133 4.3. Amplifier noise, 134 4.4, 2nd Stage noise, 136 4.5. Total noise power spectral density, 136 45.1. Low impedance receiver, 137 45.2. High impedance receiver, 140 45.3. Transimpedance receiver, 143 4.5.4. Comparison of all receiver configurations, 144 5. Signal-to-Noise Ratio, 147 5.1. SNR from the low impedance receiver, 148 5.2. SNR from the high impedance receiver, 151Contents at es 5.3. SNR from the transimpedance receiver, 151 5.4. Comparison of SNRs, 152 6. Receiver Sensitivity, 155 6.1. Analogue transmission system, 155 6.2. Digital transmission system, 156 6.3, Transmission distances, 161 7. Dynamic Range, 164 8. Developments in Receiver Design, 166 8.1. Coherent detection receivers, 167 8.2. Optically pre-amplified direct detection receivers, 170 8.3. The transmission engineer's dream, 171 References, 171 Appendix A, 175 6. Continuous-Time Filters 7 Yannis Tsividis and Venugopal Gopinathan L, Introduction, 177 2. MOSFET-C Filters, 179 2.1. The MOSFET as a voltage-controlled resistor, 179 2.2. Cancellation of nonlinearities, 181 2.3. MOSFET-capacitor filters based on balanced structures, 183 2.3.1. Principle, 183 2.3.2, Filter synthesis, 185 2.3.3, Accuracy, 188 2.3.4, Distortion and dynamic range, 189 2.3.5. Parasitic capacitance, 189 2.4. Worst-case design, 191 Transconductor-C Filters, 192 3.1, Introduction, 192 3.2. Transconductor design, 193xii Contents Ee 3.2.1. Designs that are based on MOSFET characteristics in the saturation region, 194 3.2.2. Designs that are based on MOSFET characteristics in the non-saturation region, 196 3.3, Gm-C filter synthesis, 199 4. MOSFET-C vs Transconductor-C Filters, 201 5. On-Chip Tuning Schemes, 202 6. A Warning Concerning Computer Simulations, 206 7. Conclusion, 206 References, 207 7. Switched-Capacitor Filter Synthesis 213 Adel S. Sedra and Martin Snelgrove 1, Introduction, 213 2. First-Order Building Blocks, 215 2.1. Basic operation, 215 2.2. Exact transfer functions and the LDI variable, 217 2.3. Damped integrators, 221 2.4. General form of the first-order building block, 223 2.5. Switch design, 224 2.6. Differential circuits, 225 3. Biquadratic Sections and Cascade Design, 225 3.1. Circuit generation via equivalent resistors, 226 3.2. Exact transfer function: LDI design, 228 3.3. Capacitive damping, 230 3.4. Biquads for exact design: the bilinear variable, 231 3.5. Biquad circuits for exact design, 232 3.6. Differential biquads, 234 3.7. Cascade design, 236 4. Ladder Filters, 237Contents . ait 4.1. Circuit generation, 238 4.2. Design, 241 4.3. A general exact design method, 242 5. Concluding Remarks, 246 6. References, 247 8. Multirate Switched-Capacitor Filters 251 José E, Franca and R.P. Martins 1. Introduction, 251 2. FIR SC Decimators and Interpolators, 252 2.1. Direct-form polyphase SC structure for decimation, 252 2.2. Direct-form polyphase SC structure for interpolation, 258 2.3. Multi-amplifier FIR SC decimators, 262 3. IIR SC Decimator Building Blocks, 266 3.1. First-order SC decimator building block, 268 3.2. Second-order SC decimator building block, 271 3.3. Nth.-order SC decimator building block, 277 4. TIR SC Interpolator Building Blocks, 281 5. Conclusions, 285 References, 286 Paul Gray and Robert R. Nepp 1, Introduction, 289 2. The Role of A/D Converters in Telecommunications Systems, 290 3. Classification of A/D Conversion Techniques, 292xiv Contents 4. Circuit Building Blocks for A/D Converters, 296 4.1, High-speed DACs in MOS technology, 296 4.1.1, Current-switched MOS DACs, 296 4.1.2. Resistor-string DACs, 297 4.1.3. Charge-redistribution DACs, 297 4.1.4. Component mismatch effects in monolithic DACs, 302 4.2. Monolithic sample/hold amplifiers, 307 4.3. Monolithic voltage comparators, 309 Summary, 313 References, 314 10. Delta-Sigma Data Converters 317 Gabor C. Temes 1, Introduction, 317 2. Noise-Shaping A/D Converters, 320 2.1. Quantization noise, 320 2.2. The delta-sigma modulator, 322 2.3. Higher-order single-stage converters, 325 2.4. Multi-stage (cascade) converters, 327 2.5. Modulators with multibit quantizers, 329 3. Noise-Shaping D/A Converters, 335 4. Conclusions, 337 Acknowledgement, 338 5. References, 338 11. Layout of Analog and Mixed Analog-Digital Circuits 341 Franco Maloberti 1, Introduction, 341 2, Differences Between Layout and Circuit, 342Contents 8. 9 Absolute and Relative Accuracies, 343 Layout of MOS Transistors, 344 Layout of Resistor, 348 Layout of Capacitors, 351 Stacked Layout for Analog Cells, 354 Digital Noise Coupling, 356 Floor Planning of Mixed Analog-Digital Blocks, 363 10. Concluding Remarks, 366 11. References, 366 12. System Architectures and VLSI Circuits for Telecommunications 369 Guenter Weinberger 1 2. 3. Introduction, 369 System Structure, 370 Communication ICs for Digital Exchange Systems, 371 3.1. PCM switching network components, 371 3.2. Serial communication controllers, 372 3.3. Line card functions and architectures, 374 3.3.1. Line card functions, 375 3.3.2. Line card architectures, 375 3.4. Line card controller, 376 3.5. Analog subscriber line card devices, 378 3.5.1. Line card functions, 378 3.5.2 Codec and filter devices, 380 3.5.3. Subscriber line interface circuit (SLIC), 384 3.6. Digital subscriber line card devices, 386 3.6.1. Line card functions, 386 3.6.2. ISDN transceiver devices, 387xvi Contents 4, Analog Telephone Sets, 387 5. ISDN Subscriber Equipment, 390 5.1, ISDN terminals and terminal adaptors, 391 5.1.1. ISDN layer-2 terminal controller, 391 5.1.2. ISDN codec filter, 392 5.1.3, ISDN terminal adaptors, 392 5.2, ISDN network terminations (NT1), 393 6. DSP in Telecommunications, 394 6.1. Introduction, 394 6.2. DSP design methodology, 396 7. Conclusion, 397 8. References, 398 13. Integrated Circuits for the ISDN 401 Peter Adams 1, Introduction, 401 2. ISDN Fundamentals, 401 2.1, ISDN access functional blocks, 403 3. S/T-Bus Transceivers, 404 4. D-Channel Controllers, 405 5. Digital Subscriber Loop Transceivers, 406 5.1. Key loop characteristics, 408 5.2. 2-wire duplex operation, 410 5.3. Choice of line code, 410 5.4. Transceiver architecture, 411 5.5. Transmitter implementation, 413 5.6, Receiver implementation, 414 5.7. Echo canceller implementation, 418 5.8. DSP implementation issues, 421 5.9. Transceiver examples, 423Contents xvii See ee ee ene neon eee eee e ee ee 6. Conclusion, 425 7, References, 425 14. VLSI Architectures and Circuits for Visual Communications 429 P. Pirsch and T. Wehberg Ly 2, Introduction, 429 Source Coding Algorithms, 430 2.1. Algorithms for redundancy reduction, 430 2.2. Quantization, 433 2.3. Variable word length coding, 434 2.4. Source coding for different applications, 435 VLSI Implementation Strategies, 437 Programmable Multiprocessor Systems, 441 4,1, Architecture of SIMD and MIMD multiprocessors, 442 4.2, SIMD system based on multiprocessor IC, 443 4.3. MIMD system based on multiprocessor IC, 445 Key Components for Functional Blocks, 450 5.1. Dedicated realizations of discrete cosine transform, 451 5.2. Dedicated realizations of block matching, 455 References, 459 15. Digital Television 463 A. Rothermel 1 2. Introduction, 463 TV Tuner, 464 Audio Processing, 467 Video Signal Processing, 470 4.1, Coding principles, 470xviii Contents 4.2. Implementation issues, 473 4.2.1. The luminance channel, 475 4.2.2. The chrominance channel, 477 Scan Control Processing, 481 5.1. Tasks and problems, 481 5.2. Deflection processor, 482 5.3, Picture geometry correction, 483 Quality Improvements, 484 6.1. Improved luma/chroma separation, 484 6.2. Flicker reduction, 487 6.3. Format control, 490 Conclusion, 492 References, 493 16. VLSI Architectures and Circuits for Digital Coding of High Definition Television 495 P. Pirsch and K. Griiger Introduction, 495 2. Source Coding Algorithms for HDTV, 496 2.1. HD-MAC coding, 496 2.2. DPCM coding, 498 2.3. DCT coding, 499 2.4, Subband coding, 500 VLSI Implementation Aspects, 502 VLSI Architecture for 2D DPCM, 502 4.1. Implementation problems of DPCM, 502 4.2. Parallel DPCM processors, 503 4.3. Modified DPCM structure, 505 4.4, Parallel processing and delayed decision, 506 4.5. Comparison of DPCM architectures, 507 4.6. CMOS circuit technique for DPCM, 508Contents xix ey 4.6.1, Adder realization, 508 46.2. Realization of XOR, 509 4.7. Table look-up realization, 509 4,8. Realization of line delay, 511 4,9. Example of a DPCM processing element for HDTV, 514 5, Subband Filterbanks, 515 5.1, Hardware requirements, 515 5.2. Nonrecursive wave digital filter (NRWDF), 516 5.3. Transversal FIR filter, 517 5.4, Polyphase structure, 517 5.5. Expansion in time by subsampling, 520 5.6. Architectures for quadrature mirror filterbanks (QMFs), 521 5.6.1. Filter characteristics, 521 5.6.2. Filter structures for QMFs, 521 5.7. Realization of arithmetic blocks, 522 5.7.1, Realization of multipliers, 522 5.7.2. Multioperand adders for FIR-filter, 524 5.8, Complexity of filterbank VLSI-implementation, 525 6. References, 525 17. IC Solutions for Mobile Telephones 529 Juha Rapeli 1, Introduction, 529 2. Mobile Communication Systems, 529 3. Functional Blocks of a Cellular Telephone, 533 3.1. Receiving Function (RX), 537 3.2. Frequency synthesis, 539 3,3. TX-function, 547 3.4. Signalling function, 548 3.5. Speech and audio processing, 548 3.6. Control functions, 548 4, Digital Mobile Phones, 549Contents we 4.1. Speech coding, 549 4.2. Modulation, 550. 4.3. Symbol decoder (demodulator) and channel codec, 552 5. Future developments in mobile communication, 556 5.1. CDMA technology, 558 5.2. 2-GHz development, 561 5.3. Integration of new features into mobile phones, 563 6.IC Technology, 564 6.1. FDMA, TDMA and CDMA ftom integrations points of view, 564 6,2, Integration technologies, 565 6.3. ASICs versus Standard ICs, 566 7. Conclusions, 566 References, 567 Index 569RR see Chapter 1= Circuit-Level Models for VLSI Components FM. Klaassen Philips Research Laboratories, P.O. Box 80000, 5600 JA Eindhoven, The Netherlands Introduction Essentially compact or circuit-level models give a description of the currents and charges of electronic devices in terms of the applied terminal voltages. Generally three different types can be distinguished: physics-based models, empirical models and table look-up models. In the first type the above relations are analytical expressions, which have been derived via an in-depth understanding of the physical mechanisms underlying current transport, etc. In the second type the relations are of a curve fitting nature and in the last type the characteristics are reconstructed via tables of measured or simulated data. Usually in physics-based models the relations are of a type Ip=Ip(Vi,P)), etc., where Vj is a terminal voltage and P, is a parameter. Owing to its physical base, the parameters obey geometrical scaling rules, when the device dimensions are altered. Furthermore realistic statistical modelling of circuit properties is feasible. Naturally, in order to avoid excessive CPU-time, a trade-off between complexity and accuracy has to be made. Despite their short development time, owing to the huge data storage required for the description of small devices, until now table models have not realized a breakthrough. In addition this approach has no predicting, scaling or statistics capability. Obviously, the latter facts also apply to empirical models. This review is limited to physics-based modelling. The modelling of the MOSFET, the modelling of the bipolar transistor and the acquisition, process dependence and statistics of parameters are discussed in turn. In addition mainly basic approaches are given. For detailed formulae we refer to [1]. 1. MOSFET Modelling 11, Threshold voltage Since the threshold voltage has a pivot function in MOSFET characteristics, its description is discussed first. In order to understand the approach in Figure 1, the cross section of a small n-type MOSFET is given in a direction parallel and perpendicular to current flow. Practically the onset of inversion occurs in this2 Circuit-Level Models for VLSI Components structure, if a voltage drop across the depleted substrate layer is induced, which approximately equals the diffusion voltage op (Np). Under this condition the threshold voltage Vy is determined from a balance of the applied gate charge QG = Cox ZL(VT - VEB - oF) qd) and the depletion charge 0 QB = Cox(Z + 282) (L- 28L) qj Ney) dy. 2) ya In these equations Vpg is the flatband voltage, Cox is the unit area gate capacitance, Np(y) is the substrate doping, ya(r) is the depletion width and L,Z are the actual channel length and width, respectively. Fig. la: Shape of the depletion region _—‘Fig. Ib: Shape of the depletion region in a short-channel MOSFET at in a narrow-width MOSFET at zero and high drain bias. The zero and high back-bias. The grey areas indicate the charge grey areas indicate excess shared by the gate and the charge, which is formed under junctions at zero drain bias. the LOCOS region. The Qg expression can be evaluated using several simplifying assumptions. Since Vy is the result of an integration, the implanted Gaussian-type doping profile Np(y) is replaced by an equivalent box profile [2]. The increase Z of the depletion layer width is attributed to its spreading into the channel stop area under the field insulator. Finally the decrease in length L is associated with charge sharing by the junctions and the channel area. The latter effects have been calculated either by assuming trapezoidal forms of the depletion region [3] or by making use of pseudo-2D solutions of Poisson's equation [4,5]. Naturally according to the above approach Vr is expressed in terms of the substrate doping [2]. Since however the latter quantity cannot be extracted directly from the I-V characteristics, it is more practical [1] to rewrite the result in terms of the substrate coefficients yj and y, which are the asymptotic values ofFM, Klaassen 3 ee OV7/2Vs (compare Figure 2) Vr= Vr0-% 02? + wUs = (Vs + OF) 12), 8) 0 ¥, (4,7) becomes more complicated fi). Substituting the above approximation and eq. (6) in eq. (5), we finally obtain zZ (Vc-V1) Vos - 3 (148) Vig Ios =f Hs Coxit 5 @q(VG-Vin) + On Vel (140 Vos) * where @c=(LE,)1. Usually, the product [so Cox is considered as a parameter Bo- Since for higher drain bias current saturation is induced by reversal of the normal field at the drain end of the channel, formally the saturated drain current can be written E, Ipsat = Z Cox [Ve-Vr-(1+8) Vosatl teak : )FM. Klaassen 5 where Exq is the actual lateral field and Vpsat is the saturation voltage. By equating eqs. (5) and (8) for this saturation condition, Ipsat and Vpsat are obtained from a square-law equation. 2 a — Ioss/ZCu% Vor 2 g 8 % t 2 3 t aN Fig. 3: Modelled value of saturated drain current as a function of normalized gate driving, voltage at several values of short-channel parameter Exg/Ec- The broken line represents values calculated numerically using a 2-D device simulator. Since Exq is not known exactly, MOSFET models have been based on the assumption Exd=Ec [10, 11] or Exd>>Ee [12, 13]. In reality as shown by Figure 3 the truth lies somewhere in between. In this figure the normalized saturation current according to the above approaches has been compared with results of 2- D numerical device simulation [14]. Since in practice @c Vor < 1.5 and 8, = (LE,)"1 is a measurable parameter, the error of both models can be made sufficiently small. Finally Figure 4 gives a comparison between the modelled and measured characteristics of a submicron n-channel MOSFET. In order to obtain a good fit of the drain conductance in the saturation region, the above model has been extended. This is discussed in section 14. 1.3, Subthreshold current When a gate bias well below threshold is applied, a potential barrier exists between the channel area and the source. In this case current flow is possible by means of carriers which are able to pass the above barrier, and transport takes place by diffusion rather than by drift. Therefore the current can be written in the simple form Ip=ZqDn n(o)/L, where Dp is a diffusion constant and n(o) is the number of carriers that can pass the above barrier. By solving the charge6 Circuit-Level Models for VLSI Components balance equation discussed in 1.1, it can be provided that Zz (VcG-Vr) =, ber Yer °) in which Ig is a current constant and the slope factor M is given by M=1+m(Vs + ogy 1/2, Unfortunately for short-channel devices the value of the underlying potential barrier is affected by an increase of drain bias. Since an accurate analysis of this so-called DIBL effect requires a 2-D solution of Poisson's equation, several approximations have been proposed [15, 16]. aanamememeneme 3 ea ro Fig. 4: Measured and mocilled characteristics of 0.5 um r-type MOSFET. Relevant parameter values are V9=0.70 V, B = 2.45 mA/V2, y=0.20 V1/2, 04 = 0.40 V-1, 65 =0.040 V-1, 6c=0.36 V1, 6p=0.019 V2, f=0.095. Following the latter one, in which the effect of the drain-induced field is transformed into an apparent decrease of the substrate doping, it can be shown [1] that the DIBL effect can be expressed as a decrease of threshold voltage AV = -s(Vs) Vps (10) In the case of a uniformly doped substrate s(Vs) ~ s(Vs+or)!/2, For the weak inversion region around V7 transport by drift and diffusion equally contribute to the current [17]. Therefore presently no satisfactory analytical results are available. However the expressions for strong inversion and subthreshold mode can be successfully merged either by adding eq. (9) afterFM. Klaassen 7 ee multiplication with a limiting function to eq. (5) [12, 13] or by defining a generalized gate driving voltage [9]. Figure 5 gives a comparison of the measured and modelled characteristics below inversion. Note the increase of the DIBL effect at higher values of back bias. 0 10 onl _f 7 10970 039 058 077 096 115 134 153 172 191 210 —> Vos (VI Fig. 5: Subthreshold characteristics for 0.7 tm n-type MOSFET. Relevant parameter values are V79=0.95 V, 7=0.49 V1/2, B=1.70 mA/V2, m=0.57 V1/2, s=0.014. 14. Saturation mode As already shown in Figure 4, the drain current increases slightly in the saturation region. Generally this is caused by three physical mechanisms. First an increase of drain bias causes the point of normal field reversal to shift towards the source, next for shorter channels near the same point excess mobile charge is induced and finally for very short channels weak avalanche multiplication will occur. The first effect, which can be interpreted as modulation of effective channel length, has to be calculated via a 2-D solution of Poisson's equation, including mobile carrier space charge (compare Figure 6). Therefore few published analytical models sustain a comparison with experimental results [1]. After a slight adaptation satisfactory results are obtained [16] for a model [15], which expresses the effective length by <1 Z Yp- Vpsar\ a) Leg ufi+an[r ae :8 Circuit-Level Models for VLSI Components eee where a and Vp are parameters. The second effect, which is known as static feedback, can successfully be taken into account by adding a term to the gate drive [12] Vot = Vo - Vr + f(Vps) - (12) WIN OU Ll Fig. 6: Illustration of physical mechanisms affecting the value of the drain conductance. For digital applications a first-order approach f(Vps) = fVps is sufficient, but for an accurate description of the drain conductance in analog applications a more refined approach is necessary [16]. Figure 7 gives a comparison of the modelled and measured characteristics of the drain conductance of a submicron p- channel MOSFET. 6 Oo 06 12 18 26 30 36 42 48 54 60 —> Viv) Fig. 7: Drain conductance characteristics of 0.8 yum p-type MOSFET. Relevant parameters: B=0.45 mA/V2, f=0.11, 0=0.038, Vp=4.0 V.FM. Klaassen 9 esse 1.5, Charges and capacitances Compared with the notice given to the MOSFET current, the modelling of charges and capacitances lags behind. For a long time models have been used taking only a few small signal capacitances derived for a long channel device. This approach not only leads to errors in some capacitances of short-channel devices, but generally the charge conservation principle Qc + Qs + Qn + Qp=0 a3) is violated [17, 18]. In order to maintain the latter a model has to be based on three independent terminal charges and, since such charges depend on other node voltages too, nine independent capacitances have to be taken into account. For the calculation of the charges Qs and Qp a physical partitioning of the charge in the channel is required. Such a split has been derived along two different lines of approach [19, 20]. For Qp then we have 0 Qp =-42 J nb) Fax. (14) L Similarly for Qs a weighting factor (1-x/L) has to be used. In order to simplify the evaluation of (14) quasi-static operation is assumed, which means that n(x,t) only depends on the instantaneous value of node voltages. In practice this implies that the application is limited to transients in a time step larger than twice the channel transit time [1]. Since n is known only as a function of the potential V, the variable x has to be replaced by V. This can be achieved via the current relation (5). For a short-channel device the expression for Qs and Qp, although complicated, can be given in a closed form [21]. In addition, effects of velocity saturation, static feedback, etc., can be taken into account and the continuity of the resulting capacitances across boundaries between possible modes of operation is assured. As an example Figure 8 gives a plot of CpG=9Qp/dVG for all possible modes. Generally, the capacitances are non- reciprocal. Finally similar to the Vy calculation, the bulk charge is obtained from a solution of Poisson's equation for a box-type doping profile.10 Circuit-Level Models for VLSI Components fader Mii 1] HY 1] ee Vira LG Fig. 8: The normalized drain-gate capacitance vs drain and source bias at a fixed value of gate bias. 1.6. Parasitics and model extensions In addition to the intrinsic properties discussed previously, modelling of parasitics becomes increasingly important. Within the limited scope of this review, only a few remarks are made. Owing to the necessity to reduce hot carrier effects via graded junction or offset gate structures, series resistances have a large impact on the characteristics of submicron MOSFETS. Although these resistances can be added to a circuit model, it is more practical to avoid the use of additional nodes and to include the resistance effect implicitly in the model equations. Generally this is achieved by generalizing the 6-parameters [22]. Since the gate-junction and the bulk-junction capacitance do not scale in the same manner as the intrinsic parts and additionally their voltage dependence becomes more complicated, an accurate description is required [1]. A complete MOSFET model is shown in Figure 9 [39]. For wide applications such a model has to be extended with a description of the geometry and temperature dependence of parameters, the weak-avalanche induced substrate current and the noise sources [1]. -FM. Klaassen 1 Fig. 9: Equivalent circuit of a MOSFET, showing all intrinsic capacitances (with fully drawn interconnections) and parasitic capacitances (with dashed interconnections). 2. Bipolar Modelling 2.1, Carrier transport In addition to a diffusion current, owing to the built-in field associated with doping gradients, in bipolar devices transport by drift has to be taken into account as well. Consequently the electron current density is given by Jn = hin nE + qDn Vrn (a5) with a similar equation for holes. Furthermore under transient conditions the continuity equation applies: a oe q' Vr-In=GR, (16) where G and R are the generation and recombination rate, respectively. Generally the above equations can only be solved numerically. However with almost no loss in accuracy, analytic solutions are possible under the following2 Circuit-Level Models for VLSI Components almost no loss in accuracy, analytic solutions are possible under the following assumptions: current flow is 1-D and for the base region exclusively controlled by minority carriers; outside depleted regions quasi-neutrality exists; the right- hand side of eq. (16) is determined by recombination with a single time constant. Using these assumptions the field is eliminated from eq. (15) yielding the result d jn ee (17a) Finally at the boundaries of depleted regions the condition applies 2 pn =n; exp(Vj/Ur), (17b) where nj is the intrinsic carrier density, Vj is the applied junction voltage and Ur=kp T/q. 2.2. Collector current 2.2.1. Charge control approach By integrating eq. (17a) from emitter to collector and using the boundary condition (17b), the electron current density in an npn transistor (compare Figure 10) is given by [23] Jn=ane, Gy fexp(VBe/Un) - exp(Vec/Un)}, (as) in which the Gummel number (x) (Rio Go= [Bye Gre In these equations Vpe, Vac are the applied junction voltages and nj; is considered to be subject to bandgap narrowing [24]. Fortunately in the latter integral Dy(nj/njo)? = 25 cm? s"! in a wide range of doping densities [1]. Therefore the collector current is inversely proportional to the total hole charge Qp between emitter and collector. Consequently the above current is written as Ic = Is (Qbo/Qp) [exp(VBE/Un) - exp(Vac/Ur)I, (19a) where I, is a process-related current constant. In principle Qp can be divided into parts: Qb = Qho + QTe + Ate + Qhe + Qe « (19b)FM. Klaassen 13 collector — log {net imp conc) Ib — distance (x) Fig. 10: Typical doping profile in an npn transistor. Hatched areas denote depletion regions. The dashed line gives the doping profile approximation of eq. (21). Qbo is the zero bias base charge. Qre and Qre are the depletion charges of the junctions, and Qpe and Qpc are the stored charges of the minority carriers, injected from the emitter and collector, respectively. Disregarding all charges except Qbo in the denominator, eq. (19a) forms the base for the well-known Ebers-Moll model [25]. In order to describe better the characteristics at higher currents, Qp is further evaluated in the current Gummel Poon model [26]. Then the depletion charges are calculated by integration of a bias-dependent depletion capacitance (see 2.4) and the stored charges are related to the injected currents by means of the charge control principle, e.g., I¢=I5 lexp(Vpe/Ut)- 1) = Que § (20) where t¢ is called the forward base transit time. For Qpc a similar relation can be given. In the above concept stored charge moving across the base is considered as the driving force of current. Since all charges in (19b) are now modelled in terms of junction voltages, Qp can be eliminated from eq. (19a) and a closed form expression Tc = Ic(VBE, VBE, Qhor Is, tf, tr) is obtained, which is claimed to be valid for all operation modes. In spite of its wide use, the G-P model poorly describes the characteristics under4 Circuit-Level Models for VLSI Components In spite of its wide use, the G-P model poorly describes the characteristics under high current, low bias conditions (compare Figs. 14 and 15). Generally this is caused by the neglect of quasi-saturation and the fact that t¢ and t, are not constants. Although the latter can be cured by making them bias dependent [27], a basic new approach is preferred. This is discussed next. 2.2.2. Carrier control approach An alternative approach to the description of currents and charges is to relate them to the injected minority carrier densities in the base, which in turn depend on the applied junction voltage [28, 29, 30]. In this approach the hole density p is eliminated from eq. (17a) by approximating the base doping profile (see Figure 10) Np(x) = Ngo expnx/Wp), (21) where the parameter 1 also is a measure for the built-in field. In this way for the neutral base region from eq. (17a) the basic equation 2n+Npdn, dNp Ine aDn Peas tae} 2) is obtained. Generally this equation can be solved analytically for the low injection case (n<>Ng). By writing I,=I¢(VBE) - Ir(Vpc), for instance in the latter case we have Ig = (Ig x)1/2 lexp(Vee/2U7) - 11, (23) where the parameter Ix (onset current value of high injection) is determined by 1x=4 Dn Wp Qbo- For the general case, where no closed form solution is possible, an accurate fit formula is obtained by smoothly merging both asymptotic solutions [28]. In this way the bias dependence of the transit time parameters is obtained naturally. Figure 11 gives the normalized value of t¢ as a function of injected current, clearly showing the asymptotic values. 2.3. Base current By integrating the continuity equation (16) between emitter and collector and interpreting the resulting terms, the base current is expressed in three parts Q-Qho dQ tj * dt’ Ip(t) = Ipp +FM. Klaassen 15 a8 Fig. 11: Current dependence of the forward (¢,) base transit time. where Tp is the hole lifetime and the hole current Igp arriving at the emitter contact has a form similar to eq. (18) with a characteristic Gummel number (Ge) for the emitter. Owing to surface recombination in the depletion regions, usually the second right-hand side term dominates at low forward bias. On the other hand Igp becomes dominant at higher bias conditions. Therefore, introducing a current gain parameter Br and a nonideality factor mg, the dc base current is satisfactorily described by In(Vo) = ex TEE) 1] + ts {ex arty): (24) with a similar equation for the collector bias dependent part. 24. Charges and capacitances Since the total stored base charge is proportional to the integrated minority carrier density n(x) and the latter is obtained by solving eq. (22), the charge QpE and Qgc can be calculated in principle [28]. Here we give only the high injection result Qn = tt = (Wy/4Dn) It Similar to the current, the general charge stores are obtained by merging the low-injection and high-injection solutions. As tf, t¢ are not suitable parameters (compare Figure 11), in the practical model Ic, Qpg and Qpc are expressed in terms of the current constants Is, Ik, the zero-bias base charge Qpo and the parameter 1, €.g.,16 Circuit-Level Models for VLSI Components QseE = Qpe(VBE, Is, Ik, Qbo, 1) - Usually the depletion charges are calculated by integrating the junction depletion capacitance expression Cr=Co [1-(Vj/oF)?], where the parameter p is the grading coefficient. Since the resulting expression Sete Or =e O-Vi/on)1 (25) has a singularity at Vj=9r, in practice a slight modification is applied [1]. Under high forward injected current conditions a complication arises at the collector junction. First the moving minority carrier space charge modulates Qtc and secondly charge may be injected in the collector. This is further discussed in the next section. 2.5. Quasi-saturation Due to an internal voltage drop in the collector region, the base-collector junction may become forward biased at high currents although the external voltage constitutes a reverse bias. This effect, which occurs mainly under the emitter, is called quasi-saturation. The locally forward biased junction causes an increase of reverse current I; and the injection of an excess charge Qepi i in the collector epilayer (base push-out effect). As a result the current gain and the cut- off frequency will decrease. However, depending on the combination of current injected and applied collector bias, a number of different cases have to be considered [31]. This is illustrated in Figure 12, where the typical field and electron density distribution are given. The main effect on the model described previously is that the boundary condition (17b) at the collector-side is changed and that the charge Qepi has to be taken into account. Using the same assumptions as in section 2.1, the current in the quasi-neutral collector region is controlled by af) Se os with the approximate boundary condition (see Figure 12b) p(xi) = nj. (26b) Solving this equation, the charge Qepi can be expressed explicitly in terms of the injected carrier density p(o) at the junction [31]. Since however p(o) according to (26b) depends on xj and the latter, via the voltage drop, on Ic and Vcg, finally Ic and the product Qepi*Ic become an implicit function of the external VCBFM. Klaassen 7 UU UENE EEE voltage. In practice Qepj and Ic are solved in a few steps using first an estimated value of Ic. electric field nlx) —-# |. a} saturated velocity case 4 >Jne Fig. 12: The field and electron density in the collector epilayer (n-type) for the various depletion and injection conditions. 2.6. Parasitics and model extensions Since an increase of depletion charge occurs at the cost of the neutral base width, the currents If, etc., are affected via a modulation of the zero bias base charge Quo (Early effect). Usually this effect is taken into account by putting Qbo + Qrc = Qpo (1+L) instead of Qpo. It is easily shown that in the forward mode € = (VBE/Vear) - (VCB/Veat), 27) where the parameters Vear, Veaf are called Early voltages. As with the above correction the most important intrinsic properties have been discussed. Next an equivalent circuit [32] is given in Figure 13. However in this18 Circuit-Level Models for VLSI Components scheme already parasitic elements such as series resistances and the substrate transistor have already been added. Usually the base resistance is split in a part below and adjacent to the emitter. To account for current crowding a diode has to be put in parallel to the first resistor [33, 34]. In contrast to the Gummel-Poon model the above MEXTRAM model describes well the characteristics under high current-low voltage conditions. This is illustrated in Figure 14 for the common emitter de characteristics and in Figure 15 for the cut-off frequency. Naturally for wider applications the above model has been extended [1]. Without further discussion we mention here temperature effects, charge storage in the emitter, avalanche multiplication, nonlinear Early effect, noise sources and non-quasi static charge behaviour [35, 36]. Fig, 13: Equivalent circuit diagram of the MEXTRAM model.FM. Klaassen eas measured — Mextram model —> Ve [V) Fig. 14: Measured and modelled de characteristics of bipolar transistor. 5 ea measured — Mextram model -— GP model — F; (Ghz) — 1, (A) Fig. 15: Measured and modelled cut-off frequency of bipolar transistor.20 Circuit-Level Models for VLSI Components 3. Parameters 3.1, Parameter acquisition Although the number of electrical parameters of the above models is large (typically > 20), usually their effect on the characteristics is limited to a specific range. Therefore it is practical to determine the parameters in characteristic groups. Tables I and II give the split for MOSFETS and bipolar transistors, respectively. For MOSFETS the given groups are characteristic for the channel conductance in strong inversion, the saturated Ip-Vps characteristics, the subthreshold characteristics, the weak avalanche induced substrate current and the intrinsic capacitances, successively. Similarly, for bipolar transistors the groups of Table II represent the depletion capacitances, the Early effects, the forward and reverse Gummel plots, the quasi-saturation region and the cut-off frequency. Table I: ~MOSFET parameters Table I: Bipolar parameters 0 1 Iv Vv VI Coes Per Vie Quo Is, Br Iss, Brx Repi 1 Coe Pe Vae Xeje Ips, Vit lpr, Vir The thes Mr Cos, Ps, Vas (xgje) Ik Tks (Vae) 1 ReFM. Klaassen aL 3.2, Geometry and process dependence Owing to junction sidewall effects or MOSFET short-channel effects (compare section 1.1), most electrical parameters are geometry dependent. Usually simple geometrical rules apply such as [1] P=ppZL+pilL+pzZ (28) ar P=po+piLt+pz2Z1, 9) in which pp, p1, etc. are called unity parameters. The electrical length (L) and width (Z), which generally differ from the drawn values Lm and Zy owing to process deficiencies, can be measured via a specific parameter, like for instance the MOSFET gain factor Z_, ZMAZ B=Bo{.-BoTscar (30) As an example, Figure 16 illustrates this for a 0.5 um CMOS process. Once AL and AZ are known, the unity parameters of eqs. (18) or (29) can be determined from a set of devices with different Zy, Lm values. E-5566 Z=hum tox = 125m — 118 (V7IlmA} 0 05 15 15 2 —> Lipm) Fig. 16: Determination of channel length correction by plotting the (inverse) gain factor as a function of drawn gate length. In addition to the geometry, the parameters also may depend on specific process quantities. For instance, the bipolar current constant Is will depend on the active base sheet resistance pp1. Figure 17 gives the result for the bottom part22 Circuit-Level Models for VLSI Components SSeS and the oxide sidewall part. For other reasons the MOSFET threshold voltage may depend on the gate insulator thickness and the threshold implantation dose. Using the above dependences on geometry and process quantities, the electrical parameters can be calculated from process data [1]. 0 — Jy (AAum*) —> Oy (0) Fig. 17: The bottom (jp) and oxide wall (Jox) unity parameters of the model parameter Is as a function of the sheet resistance of the pinched base. Jsi=0. 3.3, Statistics of parameters Owing to their relation with process variables, compact model parameters can be regarded as statistical variables with mean values and variances as a measure of their spread. Formally the variance of a parameter P is given by 2 2 (oP 2 aP» /aP: op = Bon (pi) + 22055 pj (pi) (5; G1) Since the process parameters pj, etc., may be correlated, the covariance is not necessarily zero. For bipolar devices the major process variables to characterize spread are the geometry corrections (AL, AZ), the active and non active base sheet resistances (Pb1.Pb2) and the breakdown voltage Vebo [1]. For MOSFETS in addition to AL, AZ, the gain factor Bo and the threshold voltage Vo of a large area device and the unit area interconnect capacitance Cint have been used [38]. In the latter caseFM. Klaassen 3 —_— Sess ogV To ~ -1. As an example Figure 18 gives the measured probability density of the collector current parameter Is together with a curve calculated from process spread data. Since the agreement for other parameters is satisfactory too, the above calculation can be further extended to predict the spread of a designed electronic function via circuit simulation [37, 38]. Subilo n30 npn transistor Emitter area 2x20 um? Fig. 18: Propability density curve for collector current constant Is. References a H.C. de Graaf and F.M. Klaassen, Compact transistor modelling for circuit design, Springer Verlag, Vienna (1990). E. Demoulin, F. v.d. Wiele, Process and Device Modelling for IC Design, Noordhoff, Leyden, 617-675 (1977). L.D. Yau, Solid State Electronics 17, 1059-1063 (1974). K.N. Ratnakumar et al., IEEE Journ. SSC-17, 937-947 (1982). T. Skotnicki et al., Proc. ESSDERC 87, North Holland, Amsterdam, 543-546 (1987). EM. Klaassen et al., Solid State Electronics 28, 359-373 (1985). T. Ando et al., Rev. Modern Physics 54, 437-672 (1982).24 ee 8 o fio] tu) (2) (13) [4] (15) {16} 07] [18] U9] (20) Qu (2) (23) [24] [5] (26) 7” 8] [29] (30) Bl (32) (3) (34) [35] Circuit-Level Models for VLSI Components G. Merckel et al., IEEE Trans. ED-19, 681-690 (1972). G.T. Wright, IEEE Trans. ED-34, 823-833 (1987). B. Hoeflinger et al., IEEE Trans. ED-26, 513-520 (1979). T. Porter et al., Solid State Electronics 23, 765-772 (1980). FM. Klaassen et al., Solid State Electronics 23, 237-242 (1980). BJ. Sheu et al., IEEE Journ. SSC-22, 558-566 (1987), CURRY, Proprietary Philips 2-D Simulation Program. PK. Ko et al., Technical Digest IEDM 81, 600-603 (1981). FM. Klaassen et al., Proc. ESSDERC 89, Springer Verlag, 418-422 (1989). P. Yang et al., IEEE Journ. SSC-18, 128-138 (1983). DE. Ward et al., IEEE Journ. SSC-13, 703-707 (1978). SY, Oh et al., IEEE Journ. SSC-15, 636-643 (1980). M.F. Sevat, Digest ICCAD87, 208-210 (1987). T. Smedes et al., Proc. ESSDERC 90 EM. Klaassen et al., Proc. ESSDERC 88, Journ. Physique C4, 257-260 (1988). H.K. Gummel, Bell Syst. Techn. J. 49, 115-122 (1970). J.W. Slotboom et al., Solid State Electronics 19, 857-862 (1976). JJ. Bbers, J.L. Moll, Proc. IRE 42, 1761-1771 (1954). H.K. Gummel, H.C. Poon, Bell Syst. Techn. J. 49, 827-844 (1970). HM. Rein et al., IEEE Trans. ED-34, 1741-1761 (1987). H.C. de Graaff et al., IEEE Trans. ED-32, 2415-2419 (1985). J.G. Fossum, Proc. IEEE Bip. Circuits and Technology Meeting, 234-241 (1989). K.W. Michaels, AJ. Strojwas, Bip. Circuits and Technology Meeting, 242- 244 (1989). H.C. de Graaf, in Process and Device Modelling for IC Design, Noordhoff, Leyden, 419-442 (1977). H.C. de Graaff et al., 18th Conf. Solid St. Devices, Tokyo, 287 (1986). G. Rey, Solid State Electronics 12, 645-655 (1969). H. Groendijk, IEEE Trans. ED-20, 329-333 (1973). J. te Winkel, Adv. Electronics/Electron Physics 39, 253-289 (1976).FM. Klaassen 25 Ee (36] J.G. Fossum et al., IEEE EDL-7, 652-654 (1986). {371 P. Yang et al., Techn. Digest IEDM 82, 286-289 (1982). [38] MJB. Bolt et al., ISMSS 90, 1989. [39] Y.P. Tsividis, Operation and Modeling of the MOS Transistor, McGraw- Hill, 1987.« Chapter 2 CMOS Operational Amplifiers Daniel Senderowicz SynchroDesign Inc., 2140 Shattuck Ave, Suite 605, Berkeley, CA 94704-1210 1. General Considerations for VLSI of Amp Design Until the availability of very-large-scale integrated circuits, analog-system designers had very little interaction with integrated op amp designers. Because of this, IC manufacturers kept the number of types within reasonable bounds by designing op amps capable of performing under a wide range of configurations, eg., inverting, noninverting, with high and low gain, etc. The current trend in VLSI implementation of assembling the system with the aid of a cell library also dictates guidelines restricting the number of different types. In principle, it is also possible to follow similar strategies in the design of op amps to suit cases with broad applications. However, there is a fundamental cost difference between the former discrete and highly integrated systems. The impact on the incremental cost of an discrete system for a slightly larger op amp is not as significant as in the case of a VLSI in which the die area, and in turn, yield play crucial roles in determining the cost. The small area criterion becomes of high priority, even at the expense of sacrificing the functional scope of the cells. In the process of cell simplification, some of the burdens assigned to discrete op amp designers are shifted to the system designers. The latter have to understand not only the capabilities of the simplified cells, but also the performance limitations of ICs, such as power-supply noise rejection (PSRR), reduced power-supply voltages, etc. Treatment methods for PSRR improvement differ substantially between discrete and integrated systems. In the former, power lines are decoupled between critical points by means of RC filters, but for integrated circuits the low value of capacitance achievable makes this approach impractical. On the other hand, techniques such as differential circuitry can help to alleviate some of the impairments found in integrated versions. These differential techniques however are not practical in discrete designs, which aim at reducing the component count. For those undertaking the task of designing an analog subsystem, it is very useful to follow a small set of guidelines in choosing the configurations, restricting them to those optimizing the utilization of the simple op amps, which can be regarded as the fundamental cells. Listed below is a set of such rules. The reasons for some of these rules may not appear obvious at this point, but will later become evident after further insight into the transistor level circuitry.28 CMOS Operational Amplifiers SSS (1) Avoid the use of internal resistors. These can appear as op amp loads, forcing the need for complex buffer stages. (2) Constrain the function around an op amp to an inverting configuration, avoiding such functions as voltage followers. The noninverting configuration requires an amplifier with large input common-mode range. (3) Avoid configurations which use MOS switches around the feedback path of an op amp. This restriction is based on similar arguments as those applying to rule (2). (4) Design the systems in such a way as to accommodate for a wide spread in the DC voltage gain. This uncertainty is mostly due to inaccuracies in the modelling of the MOS transistors in the simulators. (5) In the case of analog-to-digital (ADC) or digital-to-analog converters (DAC), choose sequential techniques whenever possible. This approach, which is somehow opposed to the idea of parallelism, generally simplifies the amount of analog circuitry at the expense of some added digital complexity and reduced speed of operation. (©) Design the systems using differential circuitry whenever possible. The op amps will be simpler, and most importantly, this may be the only way to achieve the desired specifications of dynamic range. The cost for this is an increased amount of internal elements and busing. 2. The Differential Circuit Approach Digital circuitry generates a large arnount of switching noise which appears in the power lines, the common substrate, and as parasitic capacitive coupling between the internal interconnections. This scenario imposes as one of the main goals for the designer that all the necessary precautions be taken in order to make the analog circuit highly immune to this noise coupling. Differential circuitry is.a technique which provides a way to achieve this immunity. Furthermore, differential circuitry doubles the effective signal swing which increases the dynamic range, a very important feature in high-density technology where the maximum operating supply is limited to 5 volts or less. The use of differential circuits for the analog paths generally implies a larger number of components and interconnections. However, as will be seen later, op amps with comparable functionality are considerably simpler. AnotherDaniel Senderowicz 29 ee advantage of differential circuits is that the signal is immune to noise in the internal reference node (e.g., 1/2(Vpp - Vss), a feature which is very important in single supply systems. For certain applications such as those requiring the processing of an input current (or charge), the use of differential circuitry cannot be easily implemented. In these cases, single-ended circuitry is the only practical alternative. However, if there is a significant amount of signal post-processing, one can always implement a single-ended to differential conversion as close to the input as possible, aiming at keeping the amount of single-ended circuitry to a minimum. With this consideration in mind, the need for single-ended op amps also arises, which in general will have to be subject to similar minimization arguments as those applying to their differential counterparts. Ina differential amplifier there is an additional degree of freedom over a single- ended amplifier. While the differential output should be proportional to a differential input signal, the average voltage of these two outputs should also be controllable with another input signal. This is usually referred to as the common-mode input. Fig. 1 shows a representation of a differential op amp where the inner amplifier represents the common-mode path. Fig, 1: Differential op amp. In most applications, the common-mode input is fed with a signal derived from the average of the two outputs However, it could also be possible to superimpose another signal to that average which may or may not be directly related to the differential signal. Fig. 2 shows a differential switched-capacitor integrator with the averaging of the two outputs implemented by means of an additional set of switched-capacitors. Cy is usually the unit capacitor, while Cx has to be large enough to keep the common-mode switching noise within acceptable levels.30 CMOS Operational Amplifiers Vin ¢ Veo Win Cr Fig. 2: Differential switched-capacitor integrator. It should be noted that in Fig. 2 the bias point of the differential switched- capacitors can be chosen arbitrarely. In fact, Vg2 and Vg do not have to be the same, and they can both be different from Vp1, the bias point for the common- mode switched-capacitors. This flexibility in choosing these bias points results in the possibility of superimposing DC voltages to the signal in order to avoid level-shifting operations inside the op amp. A numerical example can illustrate this idea: Vg is chosen to maximize the swing; therefore, for a single voltage supply of 5 volts, Vg=2.5V. This implies that the differential voltage Vout will have an average value of 2.5 volts. The bias voltages Vpi and Vp2 can be chosen in such a way as to fit the internal characteristics of the amplifier or other requirements. At this point it becomes obvious that one of the main goals of level-shifting with the external capacitors is to allow for op amps with limited input common-range. The penalty for having this diversity of bias voltages precludes certain configurations, such as reset switches in parallel with capacitors, which is found in the case of an offset-compensated amplification- module (Fig. 3). Fig. 3: Amplifier with MOS reset switch.Daniel Senderowicz 31 Fig. 4 describes a simplified schematic for an alternative solution that avoids the use of MOS switches while still performing the discharging of the feedback capacitor Cp. After examining the characteristics of different amplifiers, the reasons for avoiding certain configurations will become more obvious. Ce e—OVe Fig. 4: Feedback reset without switch. 3. The Number of Internal Stages Most switched-capacitor integrators operate under a condition in which Cp>>C] (Fig. 2). This implies that the gain-bandwidth products of the integrator and the op amp are essentially the same. In this case, a single voltage-gain stage is recommended. This type of op amp is sometimes referred to as an operational transconductance amplifier (OTA). OTAs do not require additional compensation capacitors, thus leading to very compact circuits. On the other hand, when the feedback configuration is such that Cp<4 cl 2) where it is assumed that gwgri>>1 and gwiri>>1. The significance of (2) is that the settling time can be minimized by dimensioning gy3 and/or cy. Furthermore, since cj is essentially the gate capacitance of Ma, the variation of the left member of (2) can be achieved by simply varying the channel length of this transistor. However, if the value of c, is too large, it might not be practical to try to achieve critical dumping, mainly because of the resulting large value of cy. Furthermore, additional parasitics, mainly the source capacitance of Ms (Fig. 5), increase the number of poles impeding the approach. Therefore, in most practical cases c1 is minimized and gm is made equal to gm. 4.1. The folded-cascode OTA An implementation of the folded-cascode OTA is depicted in Fig. 7. The higher the biasing voltage of the gates of M3 and Mg, the larger the output voltage swing will be. Therefore, this voltage is set so as to keep the current sources Mg and Mio biased just above their saturation voltage. It turns out that in this operating condition, the common-mode input range is also maximized. The same idea applies to the cascode loads Ms, M7 and Mg, Mg. That is, the gates of Ms and M¢ should be biased at a voltage that will maintain M7 and Mg biased at their saturation voltage. Given the normally low operating voltages of today's MOS technologies, it is desirable to have this saturation voltage as low as possible. The saturation voltage is: Vpsat = Vos - VT. @) Fig. 7: Folded-cascode OTA.Daniel Senderowicz 35 Noise considerations in the design dictate that the transistors used as loads should have significantly lower transductance than the ones used for the input stage. Complying with this precept implies a trade-off with the output dynamic range, as the following expressions will show. The saturation voltage can also be expressed as: 2h VDsAT = 4 : : @ where B is the gain constant of the transistor and Ips is the DC operating current. The transductance gm expressed as a function of Ips is: gm= V2B lps. @) The product of equations (4) and (5) yields the following expression: 2Ips VpsAT = “py ° 6) Equation (6) shows that the maximizing the dynamic range implies degrading the noise performance and vice versa. The best choice of parameters will depend on the design targets. These considerations apply to the dimensioning of transistors pairs Mz, Mg and Mg, Mjo. In the folded-cascode op amp, the common-mode input can be implemented by transistor Mo, or alternatively by the pair M7, Mg, or by the parallel combination of Mo and the pair Mz, Mg. 4.2. The telescopic-cascode OTA This amplifier, depicted in Fig. 8, has a configuration that is a straightforward differential implementation of the single-cascode stage shown in Fig. 5. As in the previous case, designing for maximum output swing also implies proper biasing of the cascode stages. The main difference with the folded-cascode is that there is a trade-off between the input common-range and the output swing. To achieve the maximum output swing, the pair M3, Mg has to be biased in such a way as to leave the input pair Mi, Mz and the common-mode amplifier Mo biased just above their saturation voltage. This condition limits the common- mode compliance at the input of the op amp to zero. If the operation of the op amp forces any common-mode input signal, some output swing has to be sacrified by increasing the value of Vp3.36 CMOS Operational Amplifiers 4.3, Comparisons between the folded and telescopic cascode OTAs Although the two configurations are essentially similar in operating principles, they have some advantages and disadvantages over each other. From the capabilities standpoint, the folded-cascode is more flexible than its telescopic- cascode counterpart. Its large input common-mode range makes the biasing of the input stage not as restrictive as in the case of the telescopic-cascode. Therefore, any existing voltage between Vp2 and Vpp can be used for this purpose. Furthermore, the output swing is slightly larger because there is one fewer transistor in the lower part of the amplifier. Nevertheless, if one is willing to sacrifice these two features, simulations show that the performance is essentially similar. Fig, 8: Telescopic-cascode OTA. The main basis for the evaluation comparisons is that the input pairs (M1, M2) and the common-mode transistor (Mo) have the same dimensions and carry the same bias current in both types of amplifiers; e.g., Ipg, = Id,,, where fe and tc are suffixes indicating the folded and telescopic cascodes, respectively. Power dissipation: In the folded-cascode, the pair Mg, Mig has to carry at least 2Ig. Otherwise one of the transistors in the pair M3, Mg may turn off under large input signal conditions, thus increasing the recovery time during 4 transient. Die area: The mobility, and therefore the B ratio between PMOS and NMOS transistors is approximately one-third. Based on (5),Daniel Senderowicz 37 ee the gm ratio can be approximated at one-half. Assuming that similar dynamic characteristics are to be achieved between the two types of amplifiers, the transistors in the pair Ms, Mg of the folded-cascode have to be twice as wide as the corresponding ones Ms, Mg of the telescopic-cascode. The power dissipation condition requiring the pair Mg, Mio to carry 2Ig has to be satisfied at the expense of doubling the width of this pair. Otherwise the saturation voltage will increase (see (4)). Using the argument of the gain difference between the N- and P-channel transistors, the pairs Ms, Mg and M7, Mg of the folded-cascode can be one-half the width of the corresponding pairs in the telescopic-cascode counter- part. Table 1 summarizes typical size differences of equivalent transistors in the cases of folded and telescopic cascode amplifiers. The numbers in the table indicate normalized values relative to one transistor unit (1 U). Table 1 on between OTA: == ee Pao ee [Tear eerorpaer [HU | T] 43.1, Simulations The Spice simulation setup is shown in Fig. 9, with the transistor sizes as given in Table 1 for a basic transistor unit of 1U = (100 1)/(2u) and the current Ip= 100 pA. Figs. 10 and 11 show, respectively, the input and output nodes of the transient response.38 CMOS Operational Amplifiers Fig. 9: Simulation setup. waisai” ~ vaso Fig. 10: Input voltage of transient response. It can be observed that the input and output from the telescopic-cascode [variables v(15)-v(16)] are almost identical to the corresponding variables of the folded-cascode [variables v(115)-v(116)]. 4.4. Single-ended versions of the cascode OTAs The differential telescopic and the folded cascode OTAs can be modified to operate with a single-ended output by simply converting the loads to current mirrors as shown in Figs. 12 and 13 respectively. It should be noted that theDaniel Senderowicz 39 —— same restrictions for the output swing are in effect for the single-ended versions. ~ainwaiy” wana Fig. 11: Fig. 12: Single-ended telescopic-cascode OTA. 5. Multiple Stage Op Amps As was mentioned before, when the application requires that the gain for the stage be much larger than unity (e.g., 10 times), multiple voltage-gain stages0 CMOS Operational Amplifiers may be introduced. More than one stage may also be needed if the application requires driving a resistive load, such as in the case of an analog off-chip driver. In this latter case, the second stage has to work in class-AB to keep the quiescent power consumption to a minimum. Fig. 13: Single-ended folded-cascode OTA. 5.1, The differential class-A two stage op amp This op amp is simply a cascade of two simple differential inverters (Fig. 14). The phase compensation is implemented by capacitors Cry and Cr2 and the resistors Rc1 and Rc? are used to cancel the right half-plane zero. It is worth reiterating here that the value of these capacitors should be calculated based on the actual gain setup for the stage rather than a hypothetical worst case of unity gain. This amplifier, as shown in Fig. 14, is not optimal in terms of the output swing. The local common-mode feedback implemented with transistor Mg imposes an operating voltage for the drain of M7 equal to Vgs,, which is considerably larger than the saturation voltage of M7 (e.g. 1V vs. 0.3V). Therefore the most negative voltage that any of the outputs can reach is Vsg + VGso + VDSATs,9- This limitation can be corrected by inserting a switched-capacitor level shifter between the drain of M7 and the gate of Mo, as shown in Fig. 15.Daniel Senderowicz 41 Fig. 15: Extended range Class-A, two-tage op amp.2 CMOS Operational Amplifiers ——— Shhh 5.2. The resistor driving class-AB op amp, version I One design philosophy for multi-stage op amps is to cascade a unity-gain buffer to the output of a high gain stage. Such an approach is very efficient in bipolar technology where this buffer is implemented by a pair of emitter followers. These emitter followers have a bandwidth which is considerably larger than the preceding stages; therefore, they introduce very little degradation of the phase response. Furthermore, they can help to improve the situation by buffering the capacitive load. In the case of MOS technology, an equivalent version can be derived from the bipolar case, as Fig. 16 shows. However, when low-voltage power supplies are used, this configuration is far from optimal. The amount of gate-to-source drive for each of the followers will be directly substracted from the voltage swing, with its maximum given by Vpp - Vss - VGSn - VGSp- The two components of the Vcs's, the VrHo and the overdrive can have large magnitudes — the threshold of the N-channel transistor in an N-well technology due to the body bias variation, and the overdrive due to a high output current. For a reasonable W/L ratio for M3 and Mg (<200), the output voltage can be made to reach 1.5V from each supply. Yop O Vs Fig. 16: Source follower stage. Based on the previous consideration, it becomes more convenient to use the common-source configuration for the output transistors, which limits the output swing to only the saturation voltage of the transistors (equal to the overdrive). This changes the picture of the design approach, since cascading theDaniel Senderowicz 43 ete e eee preceding high-gain portion with these common-source transistors can no longer be considered as adding a wide bandwidth stage. Thus the design of the amplifier has to be carried out as a whole, taking into account the frequency/phase characteristics of each composing stage with the estimated worst-case output loading. Probably the most critical aspect of designing a class-AB output stage using a common-source stage is the definition of the quiescent output current. Both complementary transistors in the output have to be biased with a signal which establishes the desired operating current. If this current is too low, then the bandwidth will be degraded; if it is too high, the power consumption can become unacceptable. Fig. 17 shows a single-ended amplifier with a class-AB output stage where the output quiescent current is defined by transistor ratios. Fig. 17: The resistor driving op amp — Type I. The operation of the amplifier can be better understood assuming no loading current, so that only the quiescent current flows through Mg and Mio. This also implies that the differential input is zero. Otherwise some driving signal would develop at the gates of the two above-mentioned transistors, thus forcing an output current other than zero. It is also given that M3, Ma, Ms and Mg are all identical, and M7 is identical to Mg. Under these conditions, Ips6=IDs3, to which Ipsg must match (otherwise the op amp will not be in the stable quiescent condition) Ips5=Ips6 because of the mirror Mz, Mg; and lastly, the absence of44 CMOS Operational Amplifiers a LE signal establishes the following equality: Ips6=Ips3=l0/2. Since the gates of Mg and Mg are driven by the same voltage, their currents will have the same proportional ratio as their geometries. This amplifier uses Miller compensation which is implemented by capacitors Cy and C2. 5.3. The resistor driving class-AB op amp, version II Many applications require a true-ground voltage for the inverting input of the op amp. This imposes design challenges if the chip containing the op amp has to operate off a single 5V supply and yet have an input common-mode range that encompasses OV. Furthermore, these applications generally require the driving of off-chip resistive and capacitive loads. Fig. 18 shows a folded-cascode op amp that meets these requirements. Fig. 18: Resistor driving op amp — Type II. This op amp achieves the desired input common-mode range by biasing the drains of M3, Mg just above their saturation voltage. If the inputs are connected to ground, VTH1,2 is the maximum voltage that the drains of Mj, M2 can sustain with respect to ground while still remaining in the saturation region. This voltage is generally larger than VpsaT3,4-Daniel Senderowicz 45 sess The output stage also operates in class-AB, although using a different configuration than in version I. The constant Ipsi1 bias when applied to Mi3 establishes the operating voltage at its gate by means of the feedback through Mz. Its mirror Mg will have the same voltage at its source and therefore the bias of the gate of M14 will be the same as in the gate of Mj3. Thus the current Ipsi4 will be the quiescent output current. Under large signal conditions, the two following cases are valid: (1) For positive going signals, the gate of Mj2 will be strongly driven towards the negative direction while the drive for Mj4 decreases, (2) For negative going signals, most of Ipsi9 will flow through Mis pulling the gate of M4 in the positive direction. This op amp requires a single compensation capacitor Ci because its feedback current is simultaneously applied to Mig or Mj2 through the common-gate Mg. It is interesting to note the nonlinear behavior of the stage; i.e., for small signals the pair Mz, Mg acts as a differential to single-ended converter, while for large positive going signals Mg is turned off. This nonlinearity usually causes zero- crossing distortion which can be reduced by adjusting the bias voltage Vpa to the gate of My5. This in turn rises the gates Mi2 and Muu, leading to a higher quiescent current — a situation quite common in class-AB amplifiers. This adjustment changes the phase response of the amplifier. So the optimum compromise will depend on the particular operating condition. Fig. 19 shows a simulation setup where the quiescent current is changed by adjusting the bias voltage of Mj5. Iv Vour osv | ik 30 pF ov | Fig. 19: Driver simulation. Figs. 20 and 21 show, respectively, the output for the cases where Ipsi5=0 and Ipsis=Ipsi0/2.7 CMOS Operational Amplifiers SEnESEEESASAGS=nEESERESSRESESSEOoSSEO== == Lan SEAEEEEBSEEENEERESEREEAEEE > way a2 20 : 20 27 Fig, 20: Transient response with Ipsis = 0. > vay 00 on oz os o4 os Fig. 21: Transient response with Ips215 = Ipsi0/2.Daniel Senderowicz 47 6. Bias Circuits The op amps previously described do not show the required bias circuitry. This circuitry when properly designed can be far more complex than the op amp itself, adding a significant amount of die area and power consumption. However, the voltages generated by the bias circuit can be shared by several amplifiers in the chip, diminishing the impact of the increase in area and power. In the telescopic-cascode amplifier five different bias voltages are required: Vpi through Vgs. Their values are as follows: Vapi: One Vcsy above Vs, V2: One VpsaTy above Vpi, Vp3: Two Vpsaty above Vai, Vs: One Ves, below Vpp, Vea: One Vspatp below Vps, Vi is generated simply by forcing the desired bias current over a diode- connected transistor with dimensions identical to that of Mo in the op amp circuit. Some current scaling can be applied in order to reduce the output impedance of this bias generator. This scaling is done by geometry and bias current rationing. Vg is produced by properly changing the current density on another transistor according to the method described next. Fig. 22 shows two transistors, My and M2, biased with the same current. Yop 1G Ol Vss Fig. 22: Vz and Vp1 generation.8 CMOS Operational Amplifiers The following two expressions are derived from the simplified second order model: 2] Ves, -V at VrH | ” Ves) = e + VTH Vas, can be set to be the desired V2; therefore by definition VGs-VGs|=VDsAT- Subtracting the first expression from the second and combining the result with (4), we finally obtain: B2=Bi/4 (8) Equation (8) simply states that the channel length of Mz has to be four times longer than that of Mi. Vg5 and Vpq are implemented similarly to Vpi and Vp2, respectively, by changing the polarities of the transistors and bias currents. The method for generating Vg2 is not exact even assuming an ideal second order model. In Fig. 8, the sources of Mi and M2 have nonzero bias with respect to the substrate (or well, depending on the technology). The derivation of (8) was based on identical theshold voltages for all the transistors regardless of their bias potential. However, since this body bias is equal to only one Vpsat, this error can be neglected. Furthermore, some safety factor can be applied to (8) to avoid having a situation in which Vgz results in a value smaller than required. To generate Vp3 the same design strategy for generating Vpz could be used, where Vcs3-Vcsi would be equal to 2Vpsar for deriving the new B ratio. The problem associated with this method for generating Vp3, however, are as follows: (1) The body bias of the pair M3,Mg as shown in Fig. 8 is 2VpsaT which further increases the error of the method, and (2) This method does not take into account the actual generated value of Vp2. This can lead to a low differential Vp3-Vp2, thus setting the pair My,Mp in the triode region. Fig. 23 shows a circuit which resembles the telescopic-cascode op amp. Vp3 appears at the drain of Mg, which when combined with Mz forms the equivalent of Mz of Fig. 22, here referred to the potential at the drain of Mg. Therefore the sum of the channel lengths of Mz and Mg has to be four times longer than Mg, or if Mg matches Mig, M7 has to be three times longer. It is important to note that this circuit combines both negative and positive feedback, a situation that can lead to two different stable points: a correct one