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Lecture 06 - Programmable Logic

The document discusses the evolution of programmable logic devices from PLA and PAL to CPLD and FPGA. It describes the basic architecture of an FPGA including logic blocks, interconnects, configuration memory, and input/output blocks. The document also provides details on the specific MAX10 FPGA and I/O components included on the DE10-Lite development board.

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Oluwole Abraham Fajuyi
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
12 views

Lecture 06 - Programmable Logic

The document discusses the evolution of programmable logic devices from PLA and PAL to CPLD and FPGA. It describes the basic architecture of an FPGA including logic blocks, interconnects, configuration memory, and input/output blocks. The document also provides details on the specific MAX10 FPGA and I/O components included on the DE10-Lite development board.

Uploaded by

Oluwole Abraham Fajuyi
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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EEE308 – Digital Circuit Analysis and Design

Programmable Logic (Chapter 11 of Brock


J. LaMeres & DE10-Lite Manuals)
Olawale B. Akinwale
Dept. of Electronic & Electrical Engineering,
Obafemi Awolowo University,
Ile-Ife, Osun State, Nigeria
EEE308 - Digital Circuit Analsis
and Design 2

Programmable Logic Array (PLA)


• In 1970, Texas
Instrument
introduced the PLA
for sum of products
logic expressions.
• Has an AND plane
and an OR plane.
• SOP implemented
by creating
connections
between the inputs
• OR plane caused
significant
propagation delays
EEE308 - Digital Circuit Analsis
and Design 3

Example
EEE308 - Digital Circuit Analsis
and Design 4

Programmable Array Logic (PAL)


• Introduced in 1978.
• Programmable AND plane
and a fixed-OR plane.
• Reduced flexibility
• Programmed using fuses.
An external programmer
was used to blow fuses in
order to disconnect the
inputs from the AND
gates, i.e. ability to
configure the logic post-
fabrication
EEE308 - Digital Circuit Analsis
and Design 5

Generic Array Logic (GAL)


• Addition of an output logic
macrocell (OLMC) to the PAL.
• An OLMC provided a D-flip-flop
and a selectable mux enabled the
implementation of sequential
logic and finite-state machines.
• The OLMC could also be used to
route the I/O pin back into the
PAL to increase the number of
inputs possible in the SOP
expressions.
EEE308 - Digital Circuit Analsis
and Design 6

Complex Programmable Logic Devices


• PAL couldn’t scale efficiently:
▫ as size increased, the PAL had
fan-in issues;
▫ for each input that was added to
the PAL, the amount of circuitry
needed on the chip grew
geometrically
▫ This led to a new PLD
architecture in which the on-
chip interconnect was
partitioned across multiple PALs
on a single chip = CPLD
• The term simple programmable
logic device (SPLD) was created
for previous PLD architectures
(i.e., PLA, PAL, GAL, and HAL).
EEE308 - Digital Circuit Analsis
and Design 7

Field Programmable Gate Array (FPGA)


• Developed by Xilinx Inc. in 1985.
• Array of programmable logic blocks
or logic elements and a network of
programmable interconnects.
• Each logic block = combinational
logic circuits + D-flip-flop and
multiplexer
• FPGAs are the most commonly used
programmable logic device, with
Intel Inc. (formerly Altera Inc.) and
Xilinx Inc. being the two largest
manufacturers.
EEE308 - Digital Circuit Analsis
and Design 8

CLB or LE
• Comprises a look-up table
(LUT) and a DFF and a MUX.

• LUT = multiplexers + SRAM


EEE308 - Digital Circuit Analsis
and Design 9

LUT - Example

A B X
0 0 010
0 1 011
1 0 101
1 1 111
EEE308 - Digital Circuit Analsis
and Design 10

IO Blocks
• Notice the tristate buffer at
the output.
• Any signal from the input
pad will not get into the
circuit until a clock signal
comes.
EEE308 - Digital Circuit Analsis
and Design 11

Configuration Memory
• The configuration memory for the LUTs is in a static RAM i.e. in
volatile memory: the FPGA will lose its configuration when
power is removed.
▫ The FPGA must be programmed with its configuration data every
time it is powered up.
▫ The FPGA board must a nonvolatile memory (ROM) on it so that the
FPGA can be booted up from there.
EEE308 - Digital Circuit Analsis
and Design 12

MAX10 Logic Array Block (LAB) Architecture


• In the DE10-Lite, 16
Logic Elements blocks
are put together to
make up one logic
array block (LAB)
EEE308 - Digital Circuit Analsis
and Design 13

MAX10 LAB Floorplan


EEE308 - Digital Circuit Analsis
and Design 14

The DE10-Lite Board


EEE308 - Digital Circuit Analsis
and Design 15

The DE10-Lite Board Architecture


EEE308 - Digital Circuit Analsis
and Design 16

The Push Buttons


EEE308 - Digital Circuit Analsis
and Design 17

The LEDs
EEE308 - Digital Circuit Analsis
and Design 18

The Seven-Segment Displays


EEE308 - Digital Circuit Analsis
and Design 19

The Arduino Header


EEE308 - Digital Circuit Analsis
and Design 20

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