Scribd
Upload
55 views13 pages

Analog Lab 2

The document describes the process of designing and simulating an inverter circuit. It involves determining the PMOS width for symmetry, analyzing noise margins and power consumption through DC analysis. Transient analysis is performed before and after layout to compare rise, fall and delay times. The layout is verified against the schematic through DRC and LVS checks. Post-layout simulation accounts for parasitic capacitances during transient analysis.

Uploaded by

Ajay Naik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
55 views13 pages

Analog Lab 2

The document describes the process of designing and simulating an inverter circuit. It involves determining the PMOS width for symmetry, analyzing noise margins and power consumption through DC analysis. Transient analysis is performed before and after layout to compare rise, fall and delay times. The layout is verified against the schematic through DRC and LVS checks. Post-layout simulation accounts for parasitic capacitances during transient analysis.

Uploaded by

Ajay Naik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 13

SYMBOLIC VIEW OF INVERTER

DC ANALYSIS
DESIGN
Schematic of inverter for dc analysis
width selection of pmos such that we get symmetric rise and fall time

PROCEDURE FOR DC ANALYSIS


Connect a DC voltage source to input of inverter structure. Give DC voltage as variable Vin Choose
NMOS width to be 1um PMOS width as w and Vdd=1.8V
Launch ADEL -Run DC analysis. Sweep Vin
Steps to determine pmos width:
width is kept as w for pmos.
Vin is varied from 0 to 1.8v.
Vin v/s Vout is plotted for various values of w(parametric analysis)

For the above graph identify that w for which Vout=Vin=Vth=VDD/2=1.8/2=0.9 V.


We get w as 3.28µm.
Fix this width for pmos so as to get symmetric rise and fall time.
FIXED WIDTH
FINDING NOISE MARGIN
Procedure
From the DC analysis Vout Vs Vin curve, Select Vout trace send it to calculator and then select
derivative function from function panel and send to ADE-L.
Then run again to get derivative of vout.
From this find VIL and VIH.

VOL=0V VOH=1.8V
From dc analysis we have found VIL=0.758V and VIH=1.0658V(slope equal to -1)
NML=VIL-VOL
=0.758V
NMH=VOH-VIH
=0.73V
FINDING POWER CONSUMED
Procedure
Select Outputs Save all in ADE-L, and check all in save options window
Run DC analysis. From Tool Results browser->dcop-> pwr. Send it to calculator and then to ADEL and
run again, we get the below window with the power consumed.

Theoretically power consumed = supply voltage*total current through the device

The power consumed is 53.06µW


TRANSIENT ANALYSIS
Inverter schematic
INVERTER LAYOUT
DRC CHECK

No drc error found for our layout of inverter.


LVS

The layout and the schematic of the inverter matches.


AV extracted view of inverter
PROCEDURE
Creating layout
Create the schematic of the inverter,
Add pins to schematic. Vin as input pin ,vout as output pin ,vdd and ground as input output
pins

From schematic window launch layout -XL


1.In the edit window of the layout change x and y snap to 0.01 to get more flexibility while
doing layout.
2.Click Connectivity->Generate->All from Source to get all instances and pins from the
schematic.
3.We will get auto generated NMOS and PMOS transistors as defined by us in the layout.
4.Do the connections similar to the schematic but using appropriate layers, pins and via
5.Keep in mind to give the label name for the pins which have the same label name in the
schematic.

NOTE: shift+f displays the inner layout of pmos, nmos


Pressing k brings up a ruler, while r is used to draw polygons.

Running DRC
Load Assura technology library file path is
/home/cadence/libkits/UMC_18/MIXED_MODE/Designkits/assura_tech.lib
After this select run DRC from the assura tab and then load the DRC rule file to check for
errors.
DRC check will tell if any design rules are violated by referring the DRC rule file and
comparing with our layout design.
If our layout follows all the rules no drc pop up will be displayed.

Run LVS
Run LVS (Layout VS Schematic check), Load LVS rule file
Check for LVS errors, if layout matches with schematic -Schematic and layout match message
will be obtained
If LVS is not error free debug window will pop up where we can debug the errors.
To get LVS free the important thing is to give same names and type of signal in both schematic
and layout.

RC extraction
Set up for RC extraction ->Quartus
 Setup Quartus QRC (only changes to be made mentioned)
1.in Quartus QRC setup tab, select set as default as extracted view.
2.in net listing options of QRC setup select do not include for the options.
3.in extraction tab select reference node as either vdd or gnd
.
 RUN QRC (close and open virtuoso if run QRC doesn’t appear)
1.Assura QRC Filtering tab, in this enter power net and ground net.
2.Once it is complete Av extracted view will be available in library manager
corresponding to the cell view
Creating a test inverter using inverter symbol
Using the symbol generated earlier give the appropriate inputs to perform transient analysis on
the inverter.

Voltage 1:0v
voltage 2:1.8v
Rise time=25ps
Fall time=25ps
Delay=0s
Pulse width=2ns
Pulse period=4ns
(Same values as before)

To create config view for test file


1.From Library manager select the test file. Click on file-> new cell view-Config and cell name same
the test file. This will create a config view for the test file through which we can give the rc
extracted view
2.In the config dialog box-Set view as schematic and Template as Spectre.
3.Go to tree view. Select inverter instance load Av extracted view. Save it and close it
4.After this open the test inverter and run ADE-L and run the transient analysis and calculate
the post layout rise, fall and delay values
5.As the symbol is loaded with RC_extracted view, the obtained result is post-layout
simulation result.
6.Next test file schematic with configuration set up for schematic view is loaded.
7. As the symbol is loaded with schematic view, the obtained result is pre-layout simulation
result.
PRE-LAYOUT SIMULATION RESULTS
Schematic of the transient analysis
VIN V/S VOUT (PRE-LAYOUT SIMULATION)

RISE, FALL AND PROPOGATION DELAY OF THE OUTPUT (PRE-


LAYOUT SIMULATION)

Fall time=21.63 ps
Propagation delay =18.92 ps
Rise time=21.63 ps
POST LAYOUT SIMULATION RESULTS
Vin v/s vout (post layout simulation)

RISE, FALL AND PROPOGATION DELAY OF THE OUTPUT (POST-


LAYOUT SIMULATION)

Rise time=17.72ps
Fall time=17.72 ps
Propagation delay=16.03ps
COMPARISON TABLE
Pre layout simulation Post layout simulation
Rise time=21.63 ps Rise time=17.72ps
Fall time=21.63 ps Fall time=17.72ps
Propagation delay=18.92 ps Propagation delay=16.03ps

You might also like