UNIT II

1. List system verilog introduces new data types with the following benefits.
2. "bit" and "logic" data types: These are new data types that allow for efficient
modeling of single-bit signals and multi-bit buses. They provide better
modeling capabilities than using simple integer types.
3. "enum" data type: This data type allows you to define a set of named values,
which makes it easier to create and maintain complex state machines. It also
provides better readability of code.
4. "struct" and "union" data types: These data types allow you to group related
variables together, which makes your code easier to read and understand. They
also provide a more flexible way to define data structures.
5. "packed" and "unpacked" arrays: These data types provide a way to define arrays
of different dimensions and types. Packed arrays are used for efficient
modeling of multi-bit buses, while unpacked arrays are used for more complex
data structures.
6. "interface" data type: This data type allows you to define a set of signals and
operations that can be used to communicate between different modules or
blocks. This makes it easier to create reusable and modular code.

Overall, these new data types provided by SystemVerilog allow for more efficient and
flexible modeling, improved code readability, and easier verification.

7. What do you mean by procedural statements? describe them in brief.

8. Explain the concept of procedural statements with suitable example in systemverilog.
SystemVerilog adopts many operators and statements from C and C++.
You can declare a loop variable inside a for loop that then restricts the scope
of the loop variable and can prevent some coding bugs. The increment ++ and
decrement -- operators are available in both pre- and post- form. If you have
a label on a begin or fork statement, you can put the same label on the
matching end or join statement. This makes it easier to match the start and
finish of a block. You can also put a label on other SystemVerilog end
statements such as endmodule, endtask, endfunction, and others that
you will learn in this book. Example 3-1 demonstrates some of the new
constructs.
Example 3-1 New procedural statements and operators
initial
begin : example
integer array[10], sum, j;
// Declare i in for statement
 for (int i=0; i<10; i++) // Increment i
array[i] = i;
// Add up values in the array
sum = array[9];
j=8;
do // do...while loop
sum += array[j]; // Accumulate
while (j--); // Test if j=0
$display("Sum=%4d", sum); // %4d - specify width
end : example // End label

9. List system verilog introduces new data types with the following benefits.
SystemVerilog introduces a new data type, the queue, which provides easy
searching and sorting in a structure that is as fast as a fixed-size array but as
versatile as a linked list.
Like a dynamic array, queues can grow and shrink, but with a queue you
can easily add and remove elements anywhere. Example 2-17 adds and
removes values from a queue.
Example 2-17 Queue operations
int j = 1,
b[$] = {3,4},
q[$] = {0,2,5}; // {0,2,5} Initial queue
initial begin
q.insert(1, j); // {0,1,2,5} Insert 1 before 2
q.insert(3, b); // {0,1,2,3,4,5} Insert whole q.
q.delete(1); // {0,2,3,4,5} Delete elem. #1
// The rest of these are fast
q.push_front(6); // {6,0,2,3,4,5} Insert at front
j = q.pop_back; // {6,0,2,3,4} j = 5
q.push_back(8); // {6,0,2,3,4,8} Insert at back
j = q.pop_front; // {0,2,3,4,8} j = 6
foreach (q[i])
$display(q[i]);
end
When you create a queue, SystemVerilog actually allocates extra space so
you can quickly add extra elements. Note that you do not need to call the
new[] operator for a queue. If you add enough elements so that the queue
runs out of space, SystemVerilog automatically allocates additional space. As
a result, you can grow and shrink a queue without the performance penalty of
a dynamic array.
 It is very efficient to push and pop elements from the front and back of a
queue, taking a fixed amount of time no matter how large the queue. Adding

10. Using break statement in systemverilog, write a program for the following output:
Iteration [0] to Iteration [5].
11. Differentiate between functions and task in systemverilog with a suitable example.
In SystemVerilog, a task and a function are both procedural blocks that allow you to
group a set of statements together and give them a name. However, there are some
key differences between tasks and functions:

1. Return Type: A task does not return any value while a function must have a
return type.
2. Arguments: Both tasks and functions can take arguments, but tasks can have
output and inout arguments, while functions can only have input arguments.
3. Blocking vs Non-Blocking: A task executes in a blocking manner, meaning that
it will complete all of its statements before control returns to the calling
process. On the other hand, a function can be either blocking or non-blocking,
depending on whether it uses the "automatic" keyword or not.
4. Control Flow: Tasks are generally used for controlling the overall flow of a
simulation, such as initializing variables or starting and stopping processes.
Functions are used for calculations or operations that need to return a value.

In summary, tasks and functions both provide a way to group a set of statements
together, but they differ in their return types, arguments, blocking vs non-blocking
execution, and usage.

12. Describe and distinguish the following?

a) Tasks
b) Functions
13. Explain program as an example
a) The Array Literal
b) typedef
14. Describe with suitable example the array literal and typedef.
You can initialize an array using an array literal that is an apostrophe and
curly braces.1 You can set some or all elements at once. You can replicate values
by putting a count before the curly braces.
Example 2-7 Initializing an array
int ascend[4] = ’{0,1,2,3}; // Initialize 4 elements
int decend[5];
int md[2][3] = ’{’{0,1,2}, ’{3,4,5}};
descend = ’{4,3,2,1,0}; // Set 5 elements
 descend[0:2] = ’{5,6,7}; // Set first 3 elements
ascend = ’{4{8}}; // Four values of 8

You can create new types using the typedef statement. For example, you
may have an ALU that can be configured at compile-time to use on 8, 16, 24,
or 32-bit operands. In Verilog you would define a macro for the operand
width and another for the type.
Example 2-24 User-defined type-macro in Verilog
// Old Verilog style
`define OPSIZE 8
`define OPREG reg [`OPSIZE-1:0]
`OPREG op_a, op_b;
You are not really creating a new type; you are just performing text substitution.
In SystemVerilog you create a new type with the following code. This
book uses the convention that user-defined types use the suffix “_t.”
Example 2-25 User-defined type in SystemVerilog
// New SystemVerilog style
parameter OPSIZE = 8;
typedef reg [OPSIZE-1:0] opreg_t;
opreg_t op_a, op_b;

15. Discuss the nonblocking assignment of system Verilog and write a system Verilog code
to perform sum of two variables using nonblocking statements.
Nonblocking assignments are used in System Verilog to model the behavior of
synchronous digital circuits. They are used to model sequential logic in the form of
flip-flops, registers, and other sequential elements. Nonblocking assignments are
executed after all blocking assignments in a given time step and are scheduled for the
next time step.

The syntax for a nonblocking assignment in System Verilog is:

a <= b + c;
In this example, a is assigned the value of b + c nonblockingly. This means that
the value of a will not be updated until the next time step. Nonblocking
assignments are used to model sequential logic, where the output of a flip-flop
or register is only updated on the positive edge of the clock.
 module non_blocking_example(input logic [7:0] a, b, output logic
[8:0] sum);

always @ (posedge clk) begin

sum <= #1 a + b;
end

endmodule

In this example, the input variables a and b are added together using the + operator and
the result is assigned to the output variable sum. The always block is triggered on the
positive edge of the clock (posedge clk), and the nonblocking delay #1 is used to
delay the update of sum until the next time step.

It's important to note that nonblocking assignments should be used when modeling
sequential logic, while blocking assignments should be used for combinational logic.
Using blocking assignments to model sequential logic can lead to race conditions and
other unexpected behavior.

16. Develop a verilog code for time literals and $timeformat.

module timing;
timeunit 1ns;
timeprecision 1ps;
initial begin
$timeformat(-9, 3, "ns", 8);
#1 $display("@%t", $realtime); // @1.000ns
#2ns $display("@%t", $realtime); // @3.000ns
#0.1ns $display("@%t", $realtime); // @3.100ns
#41ps $display("@%t, $realtime); // @3.141ns
end
endmodule

17. Describe the purpose of Break and continue statements with an example.
In SystemVerilog, the break and continue statements can be used while reading a file
to alter the flow of execution within loops.

When reading a file, we typically use a while or for loop to read each line of the file until
the end of the file is reached. Within these loops, we can use break and continue
statements to control the flow of execution under certain conditions.
The break statement can be used to immediately terminate the loop and exit the loop's
block of code when a certain condition is met. For example, if we are reading a file line
by line and we want to stop reading the file once we encounter a certain string, we can
use the break statement to terminate the loop as soon as that string is found.

On the other hand, the continue statement can be used to skip over certain lines
of the file under certain conditions. For example, if we want to skip over lines that
start with a certain character or string, we can use the continue statement to skip
over those lines and continue reading the rest of the file.

Two new statements help with loops. First, if you are in a loop, but want to
skip over rest of the statements and do the next iteration, use continue. If
you want to leave the loop immediately, use break.
The following loop reads commands from a file using the amazing file I/O
code that is part of Verilog-2001. If the command is just a blank line, the code
just does a continue and skips any further processing of the command. If the
command is “done,” the code does a break to terminate the loop.

18. Describe the purpose of break and continue while reading a file in systemverilog.

Example 3-2 Using break and continue while reading a file

initial begin
logic [127:0] cmd;
integer file, c;
file = $fopen("commands.txt", "r");
while (!$feof(file)) begin
c = $fscanf(file, "%s", cmd);
case (cmd)
"": continue; // Blank line - skip to loop end
"done": break; // Done - leave loop
// Process other commands here
...
endcase // case(cmd)
end
$fclose(file);
end

19. Write a short note on task and functions in system verilog with the help of an example
Verilog makes a very clear differentiation between tasks and functions.
The most important difference is that a task can consume time while a
function cannot. A function cannot have a delay, #100, a blocking statement
such as @(posedge clock) or wait(ready), or call a task. Additionally, a
Verilog function must return a value, and the value must be used, as in an
assignment statement.
In SystemVerilog, if you want to call a function and ignore its return
value, cast the result to void. This might be done if you are calling the
function to use a side effect.
If you have a SystemVerilog task that does not consume time,
you should make it a void function that is a function that
does not return a value. Now it can be called from any task or
function. For maximum flexibility, any debug routine should
be a void function rather than a task so that it can be called
from any task or function.

function void print_sum (const ref int a[]);

int sum = 0;
for (int i=0; i<a.size; i++) begin
sum += a[i];
$display("The sum of the arrays is ", sum);
endfunction
—--
task load_array(int len, ref int array[]);
if (len <= 0) begin
$display("Bad len");
return;
end
// Code for the rest of the task
...
endtask
—-
task multiple_lines;
$display("First line");
$display("Second line");
endtask : multiple_lines
20. Explain procedural statements. And write a program to declare x, y, a, b. Initialize a
and b variables with 10 and 20 respectively. And to display the values of x<=a+b and
y<=a+b+10+x.
Procedural statements in SystemVerilog are used to describe the behavior of a digital
circuit. These statements are executed sequentially, and each statement represents an
operation or action that is performed on the circuit. There are several types of
procedural statements, including assignment statements, conditional statements, and
looping statements.

An assignment statement in SystemVerilog is used to assign a value to a variable or

register. The syntax for an assignment statement is:

variable = expression;

where "variable" is the name of the variable or register, and "expression" is a

mathematical expression that evaluates to the value to be assigned.

module procedural_example;

// Declare variables
logic [31:0] x, y, a = 10, b = 20;

initial begin
// Calculate x <= a+b
x = a + b;
// Calculate y <= a+b+10+x
y = a + b + 10 + x;

// Display the values of x and y

$display("x = %d", x);
$display("y = %d", y);
end

Endmodule
x = 30
y = 70
21. Write a systemverilog code to print numbers from 1 to 10 using loop statements
module print_numbers;

initial begin
for (int i = 1; i <= 10; i++) begin
$display("Number %0d", i);
end
end
 endmodule
22. Discuss the nonblocking assignment of system Verilog and write a system Verilog code
to perform sum of two variables using nonblocking statements.

Nonblocking assignment in SystemVerilog is used to schedule assignments to

occur at the same time, without any ordering or sequencing. Nonblocking
assignments are used to model the behavior of registers in a digital circuit. In a
nonblocking assignment, the value on the right-hand side of the assignment is
evaluated and scheduled to be assigned to the left-hand side variable, but the
actual assignment does not happen until all other nonblocking assignments
have been evaluated.
module nonblocking_example;

// Declare variables
logic [7:0] a = 4;
logic [7:0] b = 7;
logic [7:0] sum_reg;

always @* begin
sum_reg <= a + b;
end

initial begin
$display("Sum of %d and %d is %d", a, b, sum_reg);
end
endmodule

23. Write a systemverilog code for pass by value and pass by reference argument passing.

Example 9-41 Simple parameter

bit [2:0] port; // Values: 0:7
covergroup CoverPort (int mid);
coverpoint port
{bins lo = {[0:mid-1]};
bins hi = {[mid:$]};
}
endgroup
CoverPort cp;
initial
cp = new(5); // lo=0:4, hi=5:7
 Example 9-42 Pass-by-reference
bit [2:0] port_a, port_b;
covergroup CoverPort (ref bit [2:0] port, int mid);
coverpoint port {
bins lo = {[0:mid-1]};
bins hi = {[mid:$]};
}
endgroup
CoverPort cpa, cpb;
initial
begin
cpa = new(port_a, 4); // port_a, lo=0:4, hi=5:7
cpb = new(port_b, 2); // port_b, lo=0:1, hi=3:7
end

24. Explain the new jump statements and operators in system Verilog.

SystemVerilog has several new jump statements and operators that provide additional
functionality for controlling the flow of code. These new statements and operators
include:

1. Jump statements:
● return statement: The return statement is used to exit a function or
task and return a value to the caller. It can also be used to exit a void
function or task without returning a value.
● break statement: The break statement is used to exit a loop or switch
statement. It is typically used in conjunction with a conditional statement
to control when the loop or switch is exited.
● continue statement: The continue statement is used to skip to the next
iteration of a loop. It is typically used in conjunction with a conditional
statement to control when the loop is skipped.
2. Operators:
● ++ and -- operators: The ++ and -- operators are used to increment or
decrement a variable by one. They can be used as a prefix or postfix
operator.
● ?: operator: The ?: operator is a ternary operator that allows for
conditional expressions. It evaluates a condition and returns one value if
the condition is true and another value if the condition is false.
● inside operator: The inside operator is used to test if a value is within a
range of values. It is typically used in conjunction with a case or if
statement to test if a value is within a certain range.

module jump_and_operator_example;

// Define function with return statement

function int add(int a, int b);

return a + b;

endfunction

// Define task with loop and break statement

task loop_with_break(int n);

int i;

for (i = 0; i < n; i++) begin

if (i == 5) begin

$display("Exiting loop at i = %0d", i);

break;

end

$display("Loop iteration %0d", i);

end

endtask

// Define task with loop and continue statement

task loop_with_continue(int n);

int i;

for (i = 0; i < n; i++) begin

 if (i % 2 == 0) continue;

$display("Odd number: %0d", i);

End

endtask

// Test the functions and tasks

initial begin

// Test return statement

int sum = add(3, 4);

$display("Sum of 3 and 4 is %0d", sum);

// Test break statement

$display("Testing break statement:");

loop_with_break(10);

// Test continue statement

$display("Testing continue statement:");

loop_with_continue(10);

// Test ?: operator

int a = 5, b = 7, max;

max = (a > b) ? a : b;

$display("Max of %0d and %0d is %0d", a, b, max);

// Test inside operator

int value = 8;

if (value inside {0:10}) $display("%0d is within the range

0-10", value);
 else $display("%0d is outside the range 0-10", value);

end

endmodule

25. Using break statement in system verilog ,write the program for the following output:
Iteration [0]
Iteration [1]
Iteration [2]
Iteration [3]
Iteration [4]
Iteration [5]

module break_example;

initial begin
for (int i = 0; i < 10; i++) begin
$display("Iteration [%0d]", i);
if (i == 5) begin
$display("Breaking out of loop");
break;
end
end
end

endmodule

26. Using continue statement in system verilog , write the program for the following
output
Current value of a = 0
Current value of a = 1
Current value of a = 2
Current value of a = 3
Current value of a = 4
Current value of a = 5
Current value of a = 6
Current value of a = 7
Current value of a = 8
Current value of a = 9

module continue_example;
 initial begin
for (int a = 0; a < 10; a++) begin
if (a == 5) begin
$display("Skipping a = 5");
continue;
end
$display("Current value of a = %0d", a);
end
end

endmodule