11 MULTIPLIERS AND DIVIDERS Baines #50 this is everything that is necessary for men concen Having completed this, we now begin to di ion, and the extraction of roots, if God so wills.” bu Jafar Muhammad al-Khwarizmi, Arithmetic ca. 830 ning the division and multiplication with an liscuss the multiplication of fractions and their _ “Atleast one good reason for studying multiplication and division is that there is an infinite _number of ways of performing these operations and hence there is an infinite number of PhOs (or ‘expenses-paid visits to conferences in the USA) to be won from inventing new forms of multiplier.” —Alan Clements, The Principles of Computer Hardware, 1986 i 2 Hardware Multipliers cation and division are extensively used, even in applications that are not commonly ted with numerical computation. Prime examples include data encryption for privacy/ ty, certain image compression methods, and graphic rendering, Hardware multipliers and dividers have thus become virtual requirements for all but the most limited processors. In P iter, beginning with the shift-add binary multiplication algorithm, we show how the is mapped to hardware and how the speed of the resulting unit is further improved. Iso show how the shift-add multiplication algorithm can be programmed on a machine oes not have a multiplication instruction. Our discussion of division follows the same shift-subtract binary algorithm, hardware realization, speedup methods, and pro- ned division. Multiplication iplest machine multipliers are designed to follow a variant of the pencil-and-paper where each row of dots in the partial prod-Chapter 11 / Multipliers and Dividers Multiplican Multiplier al products bitsmatrix Sit yix2 e yox y3x2 Figure 11.1 Multiplication of 4-bie Numb z notation. "iy Product a | we perform a k x k multiplication manually, we form all of the k resulting k numbers to obtain the product p For machine execution, itis easier if a cumulative partial product is initialized tg 9 cach row of the bit-matrix added to it as the corresponding term is generated, and the reg. addition shifted to the right by one bit to achieve proper alignment with the NEXt term, a Picted in Figure 11.1. In fact, this is exactly how programmed multiplication iS perfor, fot machine that does not have a hardware multiply unit. The recurrence equation describing process is: Partial products and ay dt 20) = (2) 4 y,x94)2-1 with 2 = and 2 =, | \— add —j | shift right | Because by the time we are done, the right shifts will have caused the fist partial Produ be multiplied by 2-*, we premultiply x by 2 to offset the effect of these Tight shifts, Ths pot an actual multiplication but is done by aligning x with the upper half of the 2-bit come lative partial product in the addition steps. This shiftsadd ‘multiplication algorithm can beg. rectly realized in hardware, as we will see in Section 11.2. The shifting Of the partial prix: need not be done in a separate Step but can be incorporated in the connecting wires that rt from the adder output to the doublewidth register holding the cumulative partial product (ee Figure 11.5). After k iterations, the multiplication recurrence leads to: : ka 2 = 242 4G, x2/) = xy 2-420) = ‘ cost in Comparison to plain shift-add multiplication. Radix-r multiplication is quite similar to the foregoing, except that all occurrences of number 2 in the equations are replaced by r, Example 11.1: Binary and decimal multiplication a. Assuming unsigned operands, Perform the binary multiplication 1010 x 0011, showil8 all algorittim steps and intermediate cumulative partial products, seed b, Repeat part a for the decimal multiplication 3528 x 4067.11.1 Shift-Add Multiplication 199 = 2%) +.¥/x2%is computed with one extra digit at i is ext as been right shified, Tt “it moves into the 8-| /$v0 (Hi partofz) | svi (eo pan of) I H Se | Also, holds SEO (Carry-out) VSB of ui 7 | during shift Sti biti of) i 1 1 1 i 1 1 i i 1 $€2 (counter) — Partofthe ‘Sub control in oe hardware Figure 11.8 Register usage for programmed multi block diagram fora hardware multiplier. ition superimposed on the shamu: move $v0,$zero # initialize Hi to 0 move $v1,$zero # initialize Lo to 0 addi $t2,$zero,32 # initialize repetition counter to 32206 Chapter 11 / Multipliers and Dividers nese bb, Seare # set carry-out to 0 in eng, ti, ga # copy (Sal) into gt4 Ene aa rl gal t the unsigned vai, ' subu $ti, $t1,$al fs t (Sal) from ( A gy Sun Sti, set, gad # obtain 168 of (Sai), or), tm beqe gti,noadd ¥ ho addition needed 4¢ yyy addu §v0,$v0,$ad # add x to upper part o¢ .? situ sto, a0 # form carry-out of agai, noadd: move $t1,§v0 # copy ($v0) into sey se 1 # halve the unsigned value , subu $v0 # subtract ($¥0) from (gt1) ,." $v subu §t1, $t1,$v0 # obtain LSB of Hi in guy "ie, > sll $t0,$t0,31 # carry-out converted to 1 in M8 o¢ addu $v0,$v0,$t0 # right-shifted $v0 corre, eq srl $v1,1 # halve the unsigned value 7 sll $t1,$t1,31 # LSB of Hi converted to 1 4, MB of « addu $v, $v1,$t1 # right-shitted $v1 correctes addi §t2,$t2,-1 } decrenent repetition counter , bne $t2,$zero,mloop # if counter > 0, repeat muj, IDLY to jr $ra # return to the calling Gran Note that because the carry-out of addition is not recorded in MiniMIPS, we have ering scheme to derive it in $t 0 by noting that the carry-out is I (an unsigned addition oversoys) id the sum is less than either operand, When a multiplicand x is to be multiplied by a constant multi Struction, or its software version in Example 11.4, may not be the best option, Maltpcs tion by a power of 2 can obviously be done through shifting, which is faster and more eff. cient than a full-blown multiply instruction. Less obviously, multiplication by other smal constants can also be performed through shift and add instructions. For example, to com Pute 5x, one can form 4x by a left-shift instruction and then add x to the result. On many m chines, one shift and one add instruction take less time than a multiply instruction. 4: another example, 7x can be computed as 8x — x, although in this case there is a dangerdl encountering overflow in computing 8x even though 7x itself is within the representation range of our machine. Most modern compil lers are smart enough to avoid spewing. out mu uply instructions when a short sequence of add/subtract/shift instructions can accompliit the same goal, plier a, using the multiply, @ 11.4 Shift-Subtract Division Like multipliers, the simplest machine dividers are designed to follow a variant of the ea and-paper division algorithm depicted in igure 11.9, Each row of dots in the subtre matrix of Figure 11,9 is either all Os (if the corresponding y, = 0) or the same as « (if ae When we perform a 2k/k division manually, we form the subtracted terms one at ® ; itl “guessing” the value of the next quotient digit, subtract the appropriate term (0 ofS114 Shift-Subtract Division —- 207 % ¥ Quotient tees 2 Dividend { Sees yond subt { eeee yon? Bitematrix } eee in 8 ee 442 Cee © Remainder FI9UTE 11.9 Division of an &-bit number by 4 A-bit number in dot notation. shifted version of x) from the partial remainder, wii ’ 1 which “ or dend z, and proceed until all k bits of 5 isaltan mameaieie eeemeene the quotient y hav ‘ aril remainder becomes the final emlates ct) MAME been determined. At this time, the For hardw above is used are oF software T software implementation, a recurrence equation describing the process 2) = 220-0 yak with 2 = ” Ishi 7 one |— subtract —} Because by the time we are done, multiplied by 2", the true remaind 2+ (shifting it to the right by k bit the left shifts will have caused the Partial remainder to be ler is obtained by multiplying the final partial remainder by ts). This is justified as follows: k 20 = Az — MH (y x28) = Hk =xy) = 25 iat As in the case of partial products for multiplication, the shifting of the partial remainder need not be performed in a separate step but can be incorporated in the connecting wires that g0 from the adder output to the double-width register holding the partial. remainder (see Section 11.5). Radix-r division is quite similar to binary division except that all occurrences of the number 2 in the equations are replaced by r. Example 11.5: Integer and fractional division 4. Assuming unsigned operands, perform the binary division 0111 0101/1010, showing all algorithm steps and partial remainders, », Repeat part a for the fractional decimal division .1435 1502/.4067. Solution: In the following, the term 22'!) is formed with one extra digit at the left end to avoid Josing the additional digit created by doubling, a, See Figure 11.10a, We verify the results by noting that they represent 117 = 10 x LL +7) b, See Figure 11.10b, The only differences from the binary division of part a are that the div- idend xis not premultiplied by a power of the radix and the subtracted terms yx need one extra digit. Thus, if we were to draw the dot-notation diagram of Figure 11.9 for this ex- ample, each row of the subtracted bit-matrix would contain 5 dots./ Multipliers and Dividers 7654 32129 Position (a) Integer binary (b) Fractional decimal | Figure 11.10 Step-by-step division examples for 8/4-digit unsigned binary integers ay, decimal fractional numbers. — Example 11.6: Division with same-width operands Often, the division z/xis performsi with operands of the same width rather than z being twice as wide as x. The algorithm, bow ever, remains the same. | a, Assuming unsigned operands, perform the binary division 1101/0101, showing a rithm steps and partial remainders. b, Repeat part a for the fractional binary division .0101/.1101. | Solution a, See Figure 11.11a. Note that because z is 4 bits Wide, left shifting can never product! nonzero bit in position 8; so unlike the example in Figure 11.10, an extra bit in postin is not needed, We verify the results by noting that they represent 13 = Byars b, See Figure 11.11b, The only differences from the binary division of part a are that bed idend x is not premultiplied by a power of the radix’ and that both the shifted remainders and the subtracted terms y_)x need one extra bit at the left (position ®)- a ify the results by noting that they represent 5/16 = (13/16) x (6/16) + 2/256. C a ing Figures 11.11b and 11,10b, we note that in Figure 11,11b, positions 5 aid not used, except in the final remainder s, Given that in fractional division the remain aUsually not of interest, positions to the right of the operands’ LSB can be completely ignored, both in manual computation and in hardware implementation. Position 11.4 Shift-Subtract Division 209 7654 3210 Position —1—2-3—4—5 6-7-8 z 0000 1101 ie 1 at 0101 1 2 0000 1101 o Le z o101 2 | 0001 104 AO Wit HO =ysx2 000 %=0 -yix 0.0 0 0 6 y-1=0 Au) 0001 101 o) Ei 2 1010 220 0011 01 OO OO yax2# -yx2* 0000 WSO =yox 0.1 101 ce 0011 01 20) FO he bea lige 2a Ria Os UEIONpt 220) OSES =x 0101 wl -ysx 0.1 101 yea 2 00011 2 0001 22 0011 22) "0.00 10) —yox2* 0000 yw=0 -yyx 0.0 00 0 y-4=0 co) 0011 2 0010 s 0011 s 0000 0 y 0010 y Oo (@) Integer binary (b) Fractional binary Figure 11.11. Step-by-step division examples for 4/4-digit unsigned binary integers and fractional numbers. Because the quotient of dividing a 2k-digit number by a k-digit number may not fit in k digits, division can lead to overflow. Fortunately, there exist simple tests for overflow detection prior to division. In integer division, overflow will not occur iff z < 2'x, since this will guarantee y < 24; that is, we require that x be strictly greater than the upper half of z. In fractional divi- sion, avoiding overflow requires z < x. So, in either case, the upper half of the double-width dividend z must be less than the divisor x. When dividing signed numbers, the remainder s is defined to have the same sign as the dividend z and a magnitude that is less than |x|. Consider the following examples of integer division with all possible combinations of signs for z and.x: Dividend z=5 Divisor yyuy Quotient y=l yer] y=-l y=l Remainder210 Chapter 11 / Multipliers and Dividers We see from the preceding examples that the magnitudes of the lunaffected by the input signs and that the signs of y and s are i of z and x, Hence, one way to do signed division is through an indirect Algorithm thy sig’ the operands into unsigned values and atthe end accounts forthe signs by aqnnt on bits or via complementation. This is the method of choice with the Festoring divi Piel Fithm, discussed in this section, Direct division of signed numbers is quite pes’! ay nonrestoring division algorithm, whose discussion is beyond the scope of ibe yi, ssion is this book. tn. thy readers can refer to any book on computer arithmetic (Parh00} Mere Quotient y and, em, easily derivable frost @ 11.5 Hardware Dividers The shift-subtract algorithm of Section 11.4.can be directly converted into the har vider shown in Figure 11.12, There are keycles for 2k/k or k/k division, Inthe jo subtracted from the upper half of the double- width partial remainder The result, noo trial difference, is loaded into the partial remainder register only if tis positive, ponte the wal difference essentially els us whether Lis the correct choice forthe nex ques 2 215 oris too large (Oi the correct choice), Note that thera difference is postive tig of the previous partial remainder is 1, making the shifted partial remainder large cacti guarantee positive difference, or else ifthe cay ofthe adder is I. Ths isthe reason po plying these two bits to the quotient digit selector block, Ls The multiplexer in Figure 11.12 allows either addition or subtraction to b each cycle, Addition of x is never required for the restoring division algorith Section 11.4, The qualifier “restoring” means that whenever the trial differenc ative, itis taken tobe an indication that the next quotient digit is O and the trial aifewnet not loaded into the partial remainder register, causing the original value to remain intact at ie ene ofthe eycle. In nonrestoring division, which we do not cover inthis book, the compu difference, whether postive or negative, i stored asthe partial remainder, which i than iy © Performed jy im Presented iy € becomes nes Shift Quotienty —e- ue Quotient | align selector | (Always Trial difference subtract) Figure 11.12 Hardware divider based on the shift-subtract algorithm.11.5 Hardware Dividers 217 From adder r Figure 11.13 Shifting incorporated in the “rOladder connections to the partial remainder reg- ister rather than as a separate phase. restored to its correct value when it goes negative, However, appropriate actions in subsequent steps will Iead to the correct result. These corrective actions require that x be added to, rather than subtracted from, the partial remainder. The nonrestoring approach makes the control cir- cuits simpler and also has the side benefit of rendering direct signed division possible Rather than inserting the bits of y into a separate register, as shown in Figure 11.12, we can insert them into the lower half of the partial remainder register. This is because as the partial remainder is shifted to the left, bit positions atthe right end of the register are freed up and can be used to store the quotient bits as they are developed. The division examples in Figure 11.10 clearly show how the lower half of the partial remainder register, which is fully occupied 0 and can be obtained as s + |x| when s <0. div $s3,$s7 # remainder formed in Hi mEhi $t2 # copy remainder into $t2 bgez $t2,done # positive remainder is the residue move $t1,$s7 # copy x into $t1; this is Ix! if x20 bgez $s7,noneg # |x| is in stl; no negation needed sub $t1,$zero,$s7 # put -x into $t1; this is Ix! if x < 0 add $t2,$t2,$t1 # residue is computed as s + |x| On machines that do not have a hardware-supported divide instruction, division can be per- formed in software by means of the shift-subtract algorithm discussed in Section 11.4. It is instructive to develop such a program for MiniMIPS because it helps us understand the algo- rithm better. In what follows, we consider unsigned division and leave it to the reader to de~ velop the signed version./ Multipliers and Dividers Example 11,8: Shift-subtract division of unsigned numbers Use the Shift-subtea, xample 11.8: : , ta define a MiniMIPS procedure that performs the unsigned division z/,, i "lp ea rithm i Sis registers $a2-$.a3 (upper and lower halves of the double-width intege nd passed to it in re; $$ $a0, respectiv he results should be re} $v0 (remainder) and ¢ 2) any be returned in $v0 (ret a : vely, The results shoul 0, respectively. “shsdi” for “‘shift-subtract division” ¥ cedure, named “shsdi” for “s! nN” Uses, | Solution: The following ae see hee nl S)nelulag Ne Upper ata Towa ‘ic structions and pseudoinstruc' Heseyeeoenieel respectively. The divisor x Fe Sf the i 5 z, are represe & vag partial eet “lin Ga, The (k-— {)th bit of yis formed in $1 andis then addeg yis ¢ oa pe insefting the next quotient bit as the LSB of gai Register « I 1, effectively i : i Sty kk See ali the MSB of Lo so that it can be shifted into #14 during left ship, po. | also used to isola ( 7 fis O holds the MSB of Hi during left shift, so that it can be used in choosing the nex okey e t, Register $t 2 is used as a counter that is initialized to 32 aa decremented by Lin each | e ian ea it reaches 0. Register usage in this example is depicted in Figure 11.15 foe, | eral s 0. eady reference. Shift 1 $a (quotient y) a siseva (Hi part of z) | $va (Lo part of 2) iM Shift 4 ->| Quotient digit selector | ! | ' | | Part of the (Always \ control in subtract) H hardware 1 Figure 11.15 Register usage for programmed division superimposed on the block diagram for a hardware divider. shsdi: move $v0,$a2 move $v1,$a3 addi $t2,$zero,32 Gloop: slt $t0,$v0,$zero sll $v0,$v0,1 slt $ti,$v1,$zero or $v0,$v0,$t1 sll $v1,$v1,1 sge $t1,$v0,$a0 Or $t1,$t1,$to imitialize Hi to ($a2) | initialize Lo to ($a3) initialize repetition counter to 32 Copy MSB of Hi into sto left-shift the Hi part of z copy MSB of Lo into $t1 move MSB of Lo into LSB of Hi left-shift the Lo part of 2 quotient digit is 1 if (Hi) >x, or if MSB of Hi was 1 before shifting eee ee ee eeProblems 215 ny it divisor x from Hi part of z | repeat divide loop | ne calling program Note that in the subtraction of x from the Hi part of. partial remainder which is in $3 We ignore the most significant bit of the ss This does not create a problem because subtraction is per- formed only if the partial remainder z (including its hidden MSB) is no less than the divisor x Division by powers of 2 can be done through shifting, which tends to be a much faster operation than division on virtually any computer, Just as one can avoid using a multiply in- struction or software routine for certain small constant multipliers (see the last paragraph in Section 11.3), one can divide numbers by small constant divisors using a handful of shifVadd/subtract instructions. The theory for deriving the required steps is somewhat more complicated than that used for multiplication and is thus not discussed in this book. Most modern compilers are smart enough to recognize opportunities for avoiding the use of a slow divide instruction. Optimizations that avoid division operations are even more important than those that eliminate multiplications. This is because on modern microprocessors, division is typically 4-10 times slower than multiplication [Etie02]. PROBLEMS TL Multiplication algorithm 11.3 Unsigned multiplication Draw dot diagrams similar to Figure 11.1 forthe ‘Multiply the following 4-bit unsigned decimal flloningvaritio numbers. Present your work in the format of Figure 11.2. 4 Integer 8x 4-digit unsigned decimal multiplication. Hint: Number of dots will change. a. x = 8765 and y = 4321 Fractional 8x 4-bit unsigned binary b. x = 1234 and y Slipleton, Hint: Alignment of dots will c. x = 8765 and y = 4321 change, pe FOOS Sl ee I eiose 8x 4-digit unsigned decimal 11.4 Two’s-complement multiplication. : Multiplication, Represent the following signed-magnitude binary numbers in 5-bit 2's-complement format and then Unsigned multiplication ‘multiply them, Present your work in the format of a ‘he following 4-bit unsigned binary numbers, Figure 11.3. *tYour Work in the format of Figure 11.2a. a, x = +.1001 and y = +.0101 +.1001 and y = —.0101 —.1001 and y = +.0101 =.1001 and y = —.0101 001 and y =