Materials Science and Engineering C 19 Ž2002.

363–368
www.elsevier.comrlocatermsec

The end of the CMOS roadmap—new landscape beyond

L. Risch )
Infineon Technologies Corporate Research, D-81730 Munich, Germany

Abstract

Reduction of feature sizes for semiconductor devices continues according to Moore’s law in order to achieve higher integration
densities, higher speed, lower power consumption and lower costs. The latest ITRS roadmap 99 describes in detail the target values for
scaling of CMOS down to 35 nm in the year 2014, which is the mainstream technology for logic and memory. Many challenges have to
be addressed for the CMOS nodes below 100 nm regarding lithography, metallisation, power dissipation, circuit design and also for the
device, but this is more a performance issue than a limitation from basic physical laws.
Therefore, novel architectures for MOSFETs are needed, to improve again the electrical characteristics and thus pave the way to much
smaller transistors than expected in the past. The 25-nm CMOS seems to be feasible using very thin silicon substrates on insulator.
Further improvements down to 10 nm are very likely with two gates for the control of the charge carriers. Thus, it is predicted that CMOS
will not end with today’s roadmap at 35 nm or even before, but will continue with non-bulk devices and fully depleted channels. Finally,
these ultimate MOSFETs are compared with single electronics. Both have a similar device structure and seem to converge for nanometer
channel length and width. But for circuit applications the small MOSFET operating with few electrons will be preferred, due to faster
switching speed and less tolerances. q 2002 Elsevier Science B.V. All rights reserved.

Keywords: MOSFET; Silicon; CMOS; Limits; Single electron devices

1. CMOS scaling regarding the scaling of the MOSFET many serious device
challenges like gate oxide thickness and junction depth are
Right from the beginning, limitations for the progress of
indicated by red brick walls in the ITRS roadmap w3x
microelectronics have been discussed, e.g. from material,
already for 70 nm. According to the scaling laws for the
process technology, design complexity, economy and from
35-nm technology, the oxide thickness of the transistors
fundamental physical laws w1,2x. Nevertheless, scientists,
should be 0.5 nm, the junction depth 11 nm, the doping
engineers and designers succeeded up to now, to solve or
concentration 2 E19 cmy3 and the supply voltage as low
surmount all these barriers by optimisation and new ideas.
as 0.35 V, see Fig. 2.
Today, 180-nm CMOS is in high volume production
All of these values are seemingly difficult to achieve
worldwide with a yield close to 100% and the 130-nm
and will result in a degradation of the on- and off-currents,
generation will be introduced soon, see Fig. 1.
leading to a slowdown of the intrinsic switching speed,
The current-gate voltage characteristics demonstrates
which is in the range of several picoseconds and given
the unique performance of MOSFETs. The off-current is in
simplified by the gate capacitance times power-supply
the range of nArmm channel width and the on-current is
voltage divided by the on-current. Nevertheless, these are
in the range of 500–750 mArmm. Moreover, CMOS
not fundamental limits arising from quantum mechanical
technology uses both n-channel and p-channel devices
effects like the wave nature of the electron, which is about
often in series, so the on-current is flowing only during
5 nm in Si, see Fig. 3. The same is true for energy
switching and the off-current is low in stand by. Also a
quantization with a few meV at 10-nm size, or the ultimate
critical point is that CMOS provides always the full signal
limit of miniaturization, which is the distance of the atoms
levels, 0 V or the power-supply voltage.
in the crystal lattice with 0.4 nm. These effects are still
But now, approaching sub 100-nm dimensions, the
insignificant or far ahead and do not really pose limitations
discussion about the end of CMOS rears up again. Indeed,
for the next 10–20 years.
Another critical issue often discussed for further scaling
)
Tel.:q49-89-234-44406; fax:q49-89-234-47069. of CMOS, is the RC time constant of the metal wires. This
E-mail address: [email protected] ŽL. Risch.. is argued to prevent further increase in switching speed w4x.

0928-4931r02r$ - see front matter q 2002 Elsevier Science B.V. All rights reserved.
PII: S 0 9 2 8 - 4 9 3 1 Ž 0 1 . 0 0 4 1 9 - 2
364 L. Risch r Materials Science and Engineering C 19 (2002) 363–368

Fig. 1. Experimental 130-nm n-MOSFET with current-gate voltage characteristics, tox s 2.8 nm.

Reducing the cross-section of the wires increases the resis- experimental bulk Si MOSFETs w5x with gate lengths
tance and reduces the capacitance in the best case. As a below 20 nm, corresponding to effective channel lengths
consequence, the length of fine wires is also to be limited. down to 4 nm, can operate in principle. But the key issue
As can be seen in Fig. 4, for short wires, which are used is the degradation in performance. Due to short channel
for local interconnects, the switching speed is clearly effects, the off-currents in the range of nArmm together
dominated by the device. Regarding global interconnects with high on-currents of about 750 mArmm are real
with long distances, usually larger wires are used to de- challenges at the power-supply voltages of the roadmap,
crease the resistance. To achieve the required switching given in Fig. 2. To improve switching speed, circuit
speed in a complex logic chip, typically up to 10 metal designers rely for all technology generations on the same
layers are used with fine wires in the lower and larger on-current, despite the decreasing voltages.
wires in the upper layers. Moreover, it should be kept in The basic trade-off is shown here for a 50-nm vertical
mind that wiring is not a specific CMOS problem but is transistor w6x, see Fig. 5, but this behaviour is also typical
relevant for all other devices. Generally, the device should for planar devices which are mainstream. An advantage of
be able to provide high on-currents at low voltages to the vertical transistor is that very short channel lengths can
charge and discharge speedily the capacitances of the be processed without advanced lithography. The current is
wires and of the next input stages. flowing at a silicon sidewall defined by etching of a
Consequently, in the following, several new approaches shallow trench and is controlled by a polysilicon spacer
for MOSFETs with channel lengths below 50 nm and high gate. The implantations for source and drain and the wiring
on-currents will be discussed. are very similar to planar devices.
The bulk doping concentration of the transistor shown
in Fig. 5 is 2E18 cmy3 . At 1.2 V power supply voltage, a
2. Novel MOSFETs below 50 nm high on-current of 700mArmm was measured, but due to
short channel effects the device cannot be turned off
2.1. Vertical transistors

Focussing on the MOSFET and the field effect, it has

already been demonstrated, using e-beam lithography, that

Fig. 2. ITRS 99 device parameter requirements of the roadmap. Fig. 3. De Broglie wavelength of an electron at 300 K.
 L. Risch r Materials Science and Engineering C 19 (2002) 363–368 365

w7x, see Fig. 6. Now the device turns off properly at low
drain voltages, but for higher drain voltages Zener tunnel-
ing currents from channel to drain appear and increase the
off-currents again. Moreover, the on-current is reduced due
to the high channel doping concentration as well as the
subthreshold slope.
Therefore, new device concepts for MOSFETs are
needed to overcome these obstacles.

2.2. Fully depleted SOI

A promising approach to solve many of the device

problems is offered by silicon on insulator ŽSOI. w8x, and
Fig. 4. Delay time of an ideal CMOS inverter compared as a function of
interconnect length for different feature sizes. Speed of light is also wafers of this material are now available in high quality at
indicated. lower prices. Many semiconductor companies already offer
SOI chips mainly for high performance logic or low power
applications. But the thickness of the Si layer is in the
properly down to nA. Thus, higher doping concentrations
will be needed for the channel. Transistors with doping
concentrations up to 1E19 cmy3 have been investigated

Fig. 5. Cross-section and layout of a 50-nm vertical transistor and

measured I – V characteristics of an n-MOSFET Žtox s 3 nm, N s 2E18 Fig. 6. Transfer and output characteristics of a 50-nm vertical n-MOSFET
cmy3 .. with high channel doping concentrations.
366 L. Risch r Materials Science and Engineering C 19 (2002) 363–368

range of about 100 nm and also the buried oxide is

relatively thick. For short channel transistors, thinner Si
layers for fully depleted channels are of interest. The
influence of the decreasing Si thickness on the off-current
is shown by simulation in Fig. 7 for 50-nm gate length.
The device with 40-nm Si thickness and tox s 2 nm,
considered here also as bulk device or partially depleted
SOI, cannot be turned off at 1-V drain voltage, similar to
the 50-nm vertical transistor with the doping concentration
of 2E18 cmy3 . Reducing Si thickness down to 10 nm, the
off-current reaches very low values, even with an undoped
channel. Undoped channels are not feasible in bulk Si Fig. 8. Schematical device structure of 25-nm SOI-n-MOSFET.
devices, because of punch through from source to drain.
They avoid the Zener tunneling currents and reduce electri-
tors in parallel. The challenge for double gate transistors
cal parameter variations due to statistical fluctuations of
will be to develop a reliable process with self-aligned
the doping atoms in the channel.
gates, which is not easy to achieve.
For 5-nm Si thickness, an excellent subthreshold slope
Recently, the Fin FET w9x, which can realise this struc-
of about 60 mVrdec is obtained. Due to the inherently
ture with relatively simple processing, was proposed. The
shallow junctions and good control of the low doped
two gates are located vertically at the sidewalls of a thin Si
channel with high mobility by the gate field, SOI will
channel and the current flows laterally, see Fig. 9.
probably allow for the reduction of the channel length
Another technological approach for double gate transis-
down to 25 nm. A cross-section of such an SOI-MOSFET
tors is based on the vertical sidewall transistor discussed in
with ultra thin body is given in Fig. 8. Elevated source
Section 2.1. Using an additional spacer as a self-aligned
drain regions grown with Si epitaxy will be implemented
mask, most of the Si source region is removed by etching
to reduce the resistance of the junctions and the contact
holes. Due to the thin body and the limited number of
doping atoms in the channel, the off-current has to be
adjusted with the work function of the gate material.

2.3. Double gate transistors

Further reduction of the channel length will become

possible using two gates for the control of the channel
together with thin Si layers instead of only a single gate.
The advantage of the two gates is to suppress the drain
field much more effectively. Moreover, Si thickness can be
relaxed and on-current is doubled, due to the two transis-

Fig. 7. Simulated ŽATLAS. influence of decreasing Si thickness Ž40, 20, Fig. 9. FinFET-type w9x double gate transistor with two channels at the
10 and 5 nm. of an SOI MOSFET on the transfer characteristics Žtox s 2 SOI layer and a device under processing after etching of a 50-nm high Si
nm, Lg s 50 nm.. active region Žtransistor width..
 L. Risch r Materials Science and Engineering C 19 (2002) 363–368 367

Fig. 12. Single electron transistor on SOI with tunnel junctions.

diffusion model and neglecting quantum mechanical ef-

Fig. 10. SEM cross section of a vertical double gate transistor.
fects. Gate oxide thickness is 2 nm to avoid tunneling, the
channel is undoped and threshold voltage is adjusted by
and only a thin Si layer remains, which forms now a the gate material, which is p-doped SiGe. The Si thickness
double gate transistor with vertical current flow w7x. The of the fin is also 10 nm. The off-current of the device is
current flows between the top contact, used as drain to the excellent and as low as 100 pArmm, while the on-current
bottom contact, which acts as source. A SEM cross-section is about 1 mArmm at 1 V, due to the high mobility in the
through the transistor is given in Fig. 10. undoped channel and the two gates.
A first simulation of the expected I–V characteristics of
a 10-nm MOSFET is shown in Fig. 11 still using the drift
3. Single electron devices

While in these ultimate MOSFETs pn junctions are

used for the isolation of the source and drain regions and
many charge carriers flow in the channel a similar device
structure leads to single electron devices w10x. These are
also three terminal devices with source, drain and a gate,
which controls the current electrostatically like in MOS-
FETs. The substrate can be SOI or a metal, but the pn
junctions are replaced by high-resistivity tunnel junctions,
see Fig. 12. The channel region should be made much
smaller, since room temperature operation about 1 nm in
size is needed for length and width. This yields capaci-
tances in the range of 0.1 aF, corresponding to a Coulomb

Fig. 11. ATLAS simulation of 10-nm double gate n-MOS transistor with Fig. 13. Simulated output characteristics of SET at 385 K. ŽRt s100 k V,
tox s 2 nm and Si thickness of 10 nm. Cg s 0.032 aF, Ct s 0.064 aF..
368 L. Risch r Materials Science and Engineering C 19 (2002) 363–368

become an issue for ultimate MOSFETs with few electrons

in the channel.

4. Perspectives

Regarding the device performance, it is very likely that

CMOS can operate down to 10 nm or even lower and that
the technological progress in microelectronics will con-
tinue. It is assumed that lithography tools like EUV,
parallel e-beam or ion beam for such small feature sizes
will be eventually available. Also, wiring of the devices
does not seem to be the limiting problem because design-
ers use multi-level metallisation with different sizes and
lengths of wires. As indicated in the roadmap, bulk CMOS
Fig. 14. Simulated transfer characteristics of a SET at 300 K. ŽRt s1 may run into performance constraints at 70 nm and below.
M V, Cg s 0.08 aF, Ct s 0.01 aF.. But thin film SOI can take over and will allow further
downscaling. Finally, double gate transistors with undoped
channel are considered to be the best nano devices with
energy of ; 1 eV for one electron to enter the channel.
respect to Ioff , Ion , switching speed and integration den-
After one additional electron is in the channel, due to its
sity. They approach the regime of single electron transis-
negative charge, the next electron cannot enter from source
tors which need 1-nm sizes for room temperature opera-
until the first electron has tunneled to drain. So, at any
tion. These devices demonstrate that even one electron can
given time, a single electron is always in the channel. As
be controlled in principle. However, due to more electrons
can be seen in the simulation of the I–V characteristics in
in the channel, MOSFETs switch faster, and are more
Fig. 13, using the orthodox theory the current is low for
reliable and are easier to optimise. Thus, with focus on the
drain voltages below erCs s 1 V and can be turned on
device, the end of the roadmap does not seem to be in
with the gate voltage.
sight for at least the next 10–20 years and the new
The maximum current, which can flow, depends on the
landscape can be reached realistically through the exten-
tunnel resistance and must be smaller than the Klitzing
sion of CMOS to very thin isolated channels and double
resistance hre 2 , which is 26 k V. In the simulation, 100
gate control.
k V was assumed, so the current is in the range of several
mA.
In contrast to MOSFET, the transfer characteristic is
References
periodically with gate voltage, but for half a period of the
gate voltage it behaves similarly as a MOSFET, see Fig. w1x J.T. Wallmark, Fundamental physical limitations in integrated elec-
14. tronic circuits, Solid State Devices, 1974 Conf. Ser. 25 Ž1975. 133.
The subthreshold slope of the single electron transistor w2x R.W. Keyes, Physical limits in digital electronics, Proc. IEEE 63 Ž5.
shown in Fig. 14 is 80 mVrdec, like in a MOSFET. This Ž1975. 740.
w3x The International Roadmap for Semiconductors, 1999.
is related to the energy distribution of the charge carriers
w4x T.N. Theis, The future of interconnection technology, IBM J. Res.
and can only be influenced by temperature. Dev. 44 Ž3. Ž2000. 379.
Even a stronger dependence on drain voltage than in a w5x S. Deleonibus et al., A 20 nm physical gate length NMOSFET
MOSFET is observed, due to the fact, that for SETs it is featuring 1.2 nm gate oxide, shallow implanted source an drain and
much more difficult to optimize the ratio of gaterchannel BF2 pockets, IEEE Electron Device Lett. 21 Ž4. Ž2000. 173.
w6x T. Schulz et al., Vertical sidewall transistors with 50 nm channel
to drainrchannel capacitances. See also the extremely
length, Proc. ESSDERC Ž2000. 552.
small capacitance of 0.01 aF, assumed in the simulation. w7x T. Schulz et al., 50 nm vertical sidewall transistors with high doping
Because only one electron is in the channel, these devices concentrations, Tech. Dig. - Int. Electron Devices Meet. Ž2000. 61.
are also very sensitive to offset charges, are much slower w8x J.P. Colinge, SOI Technology: Materials to VLSI, 2nd edn., Kluwer
in switching speed than CMOS and demand extreme tech- Academic Publishing, Boston, MA, 1997.
w9x X. Huang et al., Sub 50 nm FinFET, Tech. Dig. - Int. Electron
nology requirements. These are far beyond the reach of
Devices Meet. Ž1999. 67.
today’s processing capabilities. w10x Y. Takahashi et al., Size dependence of the characteristics of Si
Nevertheless, it is exciting to see that the charge of one single electron transistors on SIMOX substrates, IEEE Trans. Elec-
electron in a device and Coulomb blockade will also tron Devices 43 Ž8. Ž1996. 1213.