Von Neumann Architecture

Main
Memory

Input Output
Devices Devices

Backing
Storage
The Processor
Arithmetic and Logic Unit (ALU)

Carries out calculations e.g.

10110011
+ 11110010

Performs logical operations e.g.

ALU
AND, OR, NOT
The Processor
Control Unit

Manages the
fetching
decoding
and
executing
of instructions

Control
ALU Unit
The Processor
Registers
Memory
Very fast temporary storage locations which Address
hold: Other Register
Registers
• data being processed Memory
Data
• instructions being executed
Register
• addresses of memory locations to be accessed
Control
ALU Unit
The Processor
Internal Buses
Memory
Used to transmit information Address
Other Register
Registers
Memory
Data
Register

Control
ALU Unit
The Processor & Main Memory
Processor Main Memory Address
00001001
Memory Address Bus 00001000
00000111
Address 00000110
32 Lines
Other Register 00000101
Registers 00000100
Data Bus 00000011
Memory 00000010
Data 16 Lines 00000001
Register 00000000

Control
ALU Unit Control Bus
6 Lines

Each memory location is represented by a unique address.

The Address Bus
Processor Main Memory Address
00001001
Memory Address Bus 00001000
00000111
Address 00000110
Register 00000101
00000100
00000011
00000010
00000001
00000000

• information is carried from the processor to the main memory

• this informs the main memory which memory location will be read or used to store data

• each wire on the bus carries one bit of information at a time

The Address Bus
Processor Main Memory Address
00001001
Memory Address Bus 00001000
00000111
Address 00000110
Register 00000101
00000100
00000011
00000010
00000001
00000000

• the number of wires in this bus determines the number of memory locations
8 lines will allow 256 memory locations
32 lines will allow 68,719,476,736 memory locations

• increasing the width of this bus, increases the number of memory locations that it is possible to
address
The Data Bus
Processor Main Memory Address
00001001
Memory Data Bus 00001000
00000111
Data 00000110
Register 11110011 00000101
00000100
00000011
00000010
00000001
00000000

• information is carried to and from the processor and main memory

• this stores data in a memory location and reads data from a memory location

• each wire on the bus carries one bit of information at a time

The Data Bus
Processor Main Memory Address
00001001
Memory Data Bus 00001000
00000111
Data 00000110
Register 11110011 00000101
00000100
00000011
00000010
00000001
00000000

• the description of the computer informs the user of the number of wires in this bus
a 32 bit computer has 32 wires on the bus

• increasing the width of this bus, increases the quantity of data that can be carried at one time and
so increases the performance of the computer system
The Control Bus
Processor Main Memory Address
00001001
Control Bus 00001000
Control 00000111
Unit 00000110
00000101
00000100
00000011
00000010
Each wire on the bus has its own separate function and is 00000001
activated independently of the others 00000000

Read
Informs the memory that data is to be sent to the processor from a particular memory location

Write
Informs the memory that data is to be stored in a particular memory location

Clock
Generates a constant pulse which regulates the flow of information
A clock of 600MHz (megahertz) generates a pulse 600,000,000 times a second
The Control Bus
Processor Main Memory Address
00001001
Control Bus 00001000
Control 00000111
Unit 00000110
00000101
00000100
00000011
00000010
Each wire on the bus has its own separate function and is 00000001
activated independently of the others 00000000

Interrupt
A message from a peripheral device causes the processor to stop processing the current task. Current data
is stored in a temporary area called the stack. The processor deals with the interrupt. The data is then
retrieved from the stack and the task is resumed

Reset
Clears all internal processor registers and returns the computer to its initial switched on state
The Fetch-Execute Cycle
To execute a program you must first load the program and any relevant data in
to the computer’s memory (RAM) from disk.

The program and data is stored in memory until needed by the processor (the
stored program concept).

A program may contain thousands of instructions but the processor can only
execute one instruction at a time.

The first instruction is fetched from memory in to the processor where it is

decoded and executed.

Then the second instruction is fetched and then executed and so on until the
program ends.

This is known as the FETCH – EXECUTE CYCLE.

Memory Read Operation
Processor Main Memory Address
00001001
Memory Address Bus 00001000
00000111
Address 00000110
Other Register 00000101
Registers 00000100
Data Bus 00000011
Memory 00000010
Data 00000001
Register 00000000

Control
ALU Unit Control Bus

1. The processor sets up the address bus with the required memory address by
placing it in the MAR
Memory Read Operation
Processor Main Memory Address
00001001
Memory Address Bus 00001000
00000111
Address 00000110
Other Register 00000101
Registers 00000100
Data Bus 00000011
Memory 00000010
Data 00000001
Register 00000000

Control
ALU Unit Control Bus

2. The control unit activates the read line on the control bus
Memory Read Operation
Processor Main Memory Address
00001001
Memory Address Bus 00001000
00000111
Address 00000110
Other Register 11110011 00000101
Registers 00000100
Data Bus 00000011
Memory 00000010
Data 00000001
Register 00000000

Control
ALU Unit Control Bus

3. The address bus opens the relevant memory location at that address
Memory Read Operation
Processor Main Memory Address
00001001
Memory Address Bus 00001000
00000111
Address 00000110
Other Register 11110011 00000101
Registers 00000100
Data Bus 00000011
Memory 00000010
Data 00000001
Register 00000000

Control
ALU Unit Control Bus

4. The contents of the memory location are released, sent along the data bus and
into the MDR
Memory Read Operation
Processor Main Memory Address
00001001
Memory Address Bus 00001000
00000111
Address 00000110
Other Register 00000101
Registers 00000100
Data Bus 00000011
Memory 00000010
Data 00000001
Register 00000000

Control
ALU Unit Control Bus

5. The data is then decoded and executed

Memory Write Operation
Processor Main Memory Address
00001001
Memory Address Bus 00001000
00000111
Address 00000110
Other Register 00000101
Registers 00000100
Data Bus 00000011
Memory 00000010
Data 00000001
Register 00000000

Control
ALU Unit Control Bus

1. The processor sets up the address bus with the required memory address by
placing it in the MAR
Memory Write Operation
Processor Main Memory Address
00001001
Memory Address Bus 00001000
00000111
Address 00000110
Other Register 00000101
Registers 00000100
Data Bus 00000011
Memory 00000010
Data 00000001
Register 00000000

Control
ALU Unit Control Bus

2. The processor sets up the data bus with the value to be stored in memory by
placing it in the MDR
Memory Write Operation
Processor Main Memory Address
00001001
Memory Address Bus 00001000
00000111
Address 00000110
Other Register 00000101
Registers 00000100
Data Bus 00000011
Memory 00000010
Data 00000001
Register 00000000

Control
ALU Unit Control Bus

3. The control unit activates the write line on the control bus
Memory Write Operation
Processor Main Memory Address
00001001
Memory Address Bus 00001000
00000111
Address 00000110
Other Register 00000101
Registers 00000100
Data Bus 00000011
Memory 00000010
Data 00000001
Register 00000000

Control
ALU Unit Control Bus

4. The address bus opens the relevant memory location at that address
Memory Write Operation
Processor Main Memory Address
00001001
Memory Address Bus 00001000
00000111
Address 00000110
Other Register 11000111 00000101
Registers 00000100
Data Bus 00000011
Memory 00000010
Data 00000001
Register 00000000

Control
ALU Unit Control Bus

5. The contents of the memory location are released, sent along the data bus and
into the memory location
Credits
Higher Computing – Computer Structure – The Processor

Produced by P. Greene for the City of Edinburgh Council 2004

Adapted by M. Cunningham 2010

All images licenced under Creative Commons 3.0

• Intel Insides by Ryan Maclean (rcmaclean on Flickr)