School of

Continuous Assessment Test – 1

Q1. A certain pattern detection based camera modules can be trained with
desired types of objects. Three such modules are taken, and the first module
is trained with various cat images, second module with various images of
dogs and the third module with human faces. After training, the first module
outputs logic HIGH if a cat is detected in its vicinity. The second camera
module outputs logic HIGH if a dog image is detected. Similarly, the third
module outputs logic HIGH if a human face is detected. All the three
outputs of these three camera modules are fed to a digital circuit block,
which outputs a digital logic HIGH when the following conditions are
satisfied,
a) If the frame contains only two objects – cat and dog, or cat and
human face, or dog and human face.
b) If the frame contains all the three objects - cat, dog and human
face.

Design a suitable PAL circuit for the digital block which satisfies the above
conditions. (15 marks)

Q2. Design a digital timer using Verilog HDL code with the following
specifications:
a) The timer has an input clock with name “clk” which is fed from
an external crystal oscillator running with frequency 50 KHz.
b) The timer has an input ports – seconds, minutes, hours where the
 user can give these inputs, when a one bit input load (‘ld’) is set
to logic HIGH.
c) The timer has three 32-bit registers, REG_SEC, REG_MIN,
REG_HOURS, which are loaded with input seconds, minutes, (15 marks)
hours respectively, when ‘ld’ is set to logic HIGH.
d) The timer starts down counting from the values of the above
three registers, and when reaches zero, triggers a one-bit output
port ‘tr’ (trigger), to logic HIGH.
e) The stop watch has an input named “pause”, when enabled make
the timer to pause.
f) The stop watch has an input reset, when enabled makes all the
register values to zero.
Q3. Design a 1-bit digital comparator using PROM for the following outputs –
a) NEQ (Not Equal to)
b) LEQ (Less than or Equal to) (5 marks)

c) GNEQ (Greater than or Not Equal to).

Q4.
Design a 3-bit binary sequence generator with the following specifications
a) Each number in the sequence is an even number or Fibonacci
number
b) Any consecutive repeated numbers are omitted in the obtained
sequence.
c) The sequence starts from highest to lowest possible 3-bit number
d) The sequence rolls back to the starting number after the last number
in the sequence is reached.
e) Use D-flip flop-flops for the design wherever flip-flops are needed.
f) Consider symbols for flip-flop inputs/outputs as DA/QA, DB/QB,
DC/QC etc.
Write the final obtained circuit equations and draw the circuit. Using FSM
state diagram obtained, write a Verilog HDL behavioral model code for the
above sequence generator. (15 marks)
***** End of Question Paper *****