A B C D E

1 1

LCFC Confidential
2
E555 2

NM-A241 Schematics
AMD Kaveri 2.0 Processor with DDR3L + Bolton FCH
GPU AMD TOPAZ XT

2013-11-20
3
REV:0.2 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 1 of 65
A B C D E
 A B C D E

Model Name : AATE1

AMD JET XT
DDR3*4
VRAM 256M*16/ PCI-E X8
1
AMD Memory Bus 1

Kaveri 2.0 Dual Channel

1.35V DDR3L 1866MHz
DDR3L-SO-DIMM X2
Page 17 ~ 25 FP3 BGA 854 Page 10 ~ 11
29.15mm * 32.15mm

HDMI Connector Page 4 ~ 9

HDMI Power/signal cable docking
Page 27 UMI x4 2Channel Speaker
100MHz
5GB/s Page 35
eDP Connector eDP
Page 26 Digital MIC
HD Audio Audio Codec
Page 34
AMD
CRT Connector USB3+DP Page 34
2

Page 28 Bolton FCH Audio combo Jack 2

PCI-E FCBGA 656 Page 34

24.5mm * 24.5mm USB 2.0
Card Reader
SPI ROM USB 3.0
Realtek RTS5227E
SPI CMOS Camera Page 26
BIOS 8M SATA
Page 13 Page 12 ~ 16

LPC BUS
LAN
Realtek RTL8111GUS
USB PORT 2.0 x 1 Page 41 Sub-Board
EC
3
ITE 8586EX 3

Page 38 USB PORT 3.0 x 2 Page 30

RJ45 CONN Track Point G-Sensor

Page 36 Page 42 Page 40

NGFF TYPEA USB 2.0

Click Pad Keyboard Thermal Sensor SATA HDD CONN Page 31
F75303M
WLAN Page 42 Page 39 Page 29
Page 33 PCI-E
Module

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 2 of 65
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 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+0.675VS
+0.95VS_VDDP S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+0.95VS_VDDR
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+1.8VS_VDDA
1
+3VALW 1

+1.1VS S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +1.5V
+VDD_CORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+5VALW +VDDNB_CORE
+VGA_CORE
State +3VS_VGA
+1.8VS_VGA
+1.5VS_VGA
+0.95VS_VGA USB Port Table BOM Structure Table
3 External BTO Item BOM Structure
USB 2.0 USB 3.0 Port Port USB Port Un-mount @
S0 O O O O 0 USB 2.0 Port Connector ME@
1 GPU DIS@
EHCI 2 UMA UMA@
S3 O O O X 3 VRAM Option X76@
4 RF Part Option RF@
5 Camera EMI Part Option EMI@
2
S5 S4/AC Only O O X X 6 WLAN/BT ESD Part Option ESD@ 2

EHCI 7 FPR JET GPU JET@

S5 S4 8 TOPAZ GPU TOPAZ@
Battery only O X X X 9 Quad Core APU QC@
0 10 USB 3.0 Port 15 MB 15@
xHCI
1 11
S5 S4 2 12 USB 3.0 Port
xHCI
AC & Battery X X X X 3 13 Docking port
don't exist

PCIE PORT LIST

Port Device
0 LAN
1 Card Reader
3
2 WLAN 3

3
4
5
6
7

EC SM Bus1 address EC SM Bus3 address FCH SM Bus address

Device Address Device Address Device Address ZZZ1

Smart Battery 0001 011X b Thermal Sensor DDR DIMM1

DDR DIMM2

DAZ0TX00100

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 3 of 65
A B C D E
 5 4 3 2 1

UC3A

D PCI EXPRESS D

PCIE_CRX_GTX_P0 Y8 P_GFX_RXP0/RSVD P_GFX_TXP0/DP6_TXP4 AB2 PCIE_CTX_GRX_P0 CC1 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_P0

17 PCIE_CRX_GTX_P0 PCIE_CTX_C_GRX_P0 17
PCIE_CRX_GTX_N0 Y9 P_GFX_RXN0/RSVD P_GFX_TXN0/DP6_TXN4 AB1 PCIE_CTX_GRX_N0 CC2 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_N0
17 PCIE_CRX_GTX_N0 PCIE_CTX_C_GRX_N0 17
PCIE_CRX_GTX_P1 Y4 P_GFX_RXP1/RSVD P_GFX_TXP1/DP6_TXP5 AB3 PCIE_CTX_GRX_P1 CC3 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_P1
17 PCIE_CRX_GTX_P1 PCIE_CTX_C_GRX_P1 17
PCIE_CRX_GTX_N1 W5 P_GFX_RXN1/RSVD P_GFX_TXN1/DP6_TXN5 AA2 PCIE_CTX_GRX_N1 CC4 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_N1
17 PCIE_CRX_GTX_N1 PCIE_CTX_C_GRX_N1 17
PCIE_CRX_GTX_P2 W7 P_GFX_RXP2/RSVD P_GFX_TXP2/DP6_TXP6 AA1 PCIE_CTX_GRX_P2 CC5 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_P2
17 PCIE_CRX_GTX_P2 PCIE_CTX_C_GRX_P2 17
PCIE_CRX_GTX_N2 W8 P_GFX_RXN2/RSVD P_GFX_TXN2/DP6_TXN6 Y1 PCIE_CTX_GRX_N2 CC6 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_N2
17 PCIE_CRX_GTX_N2 PCIE_CTX_C_GRX_N2 17
PCIE_CRX_GTX_P3 U5 P_GFX_RXP3/RSVD P_GFX_TXP3/RSVD Y2 PCIE_CTX_GRX_P3 CC7 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_P3
17 PCIE_CRX_GTX_P3 PCIE_CTX_C_GRX_P3 17
PCIE_CRX_GTX_N3 V4 P_GFX_RXN3/RSVD P_GFX_TXN3/RSVD W2 PCIE_CTX_GRX_N3 CC8 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_N3
17 PCIE_CRX_GTX_N3 PCIE_CTX_C_GRX_N3 17
PCIE_CRX_GTX_P4 U7 P_GFX_RXP4/RSVD P_GFX_TXP4/DP6_TXP0 V2 PCIE_CTX_GRX_P4 CC106 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_P4
17 PCIE_CRX_GTX_P4 PCIE_CTX_C_GRX_P4 17
PCIE_CRX_GTX_N4 U8 P_GFX_RXN4/RSVD P_GFX_TXN4/DP6_TXN0 V1 PCIE_CTX_GRX_N4 CC107 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_N4
17 PCIE_CRX_GTX_N4 PCIE_CTX_C_GRX_N4 17
PCIE_CRX_GTX_P5 T4 P_GFX_RXP5/RSVD P_GFX_TXP5/DP6_TXP1 V3 PCIE_CTX_GRX_P5 CC108 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_P5
17 PCIE_CRX_GTX_P5 PCIE_CTX_C_GRX_P5 17
PCIE_CRX_GTX_N5 R5 P_GFX_TXN5/DP6_TXN1 U2 PCIE_CTX_GRX_N5 CC109 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_N5

GRAPHICS
P_GFX_RXN5/RSVD
17 PCIE_CRX_GTX_N5 PCIE_CTX_C_GRX_N5 17
PCIE_CRX_GTX_P6 R7 P_GFX_RXP6/RSVD P_GFX_TXP6/DP6_TXP2 U1 PCIE_CTX_GRX_P6 CC110 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_P6
17 PCIE_CRX_GTX_P6 PCIE_CTX_C_GRX_P6 17
PCIE_CRX_GTX_N6 R8 P_GFX_RXN6/RSVD P_GFX_TXN6/DP6_TXN2 T1 PCIE_CTX_GRX_N6 CC111 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_N6
17 PCIE_CRX_GTX_N6 PCIE_CTX_C_GRX_N6 17
PCIE_CRX_GTX_P7 P8 P_GFX_RXP7/RSVD P_GFX_TXP7/DP6_TXP3 T2 PCIE_CTX_GRX_P7 CC112 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_P7
17 PCIE_CRX_GTX_P7 PCIE_CTX_C_GRX_P7 17
PCIE_CRX_GTX_N7 P7 P_GFX_RXN7/RSVD P_GFX_TXN7/DP6_TXN3 R2 PCIE_CTX_GRX_N7 CC113 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CTX_C_GRX_N7
17 PCIE_CRX_GTX_N7 PCIE_CTX_C_GRX_N7 17
P4 P_GFX_RXP8/RSVD P_GFX_TXP8/DP5_TXP0 P2
P5 P_GFX_RXN8/RSVD P_GFX_TXN8/DP5_TXN0 P1
M8 P_GFX_RXP9/RSVD P_GFX_TXP9/DP5_TXP1 P3
M7 P_GFX_RXN9/RSVD P_GFX_TXN9/DP5_TXN1 N2
M5 P_GFX_RXP10/RSVD P_GFX_TXP10/DP5_TXP2 N1
M4 P_GFX_RXN10/RSVD P_GFX_TXN10/DP5_TXN2 M1
L6 P_GFX_RXP11/RSVD P_GFX_TXP11/DP5_TXP3 M2
L5 P_GFX_RXN11/RSVD P_GFX_TXN11/DP5_TXN3 L2
L8 P_GFX_RXP12/RSVD P_GFX_TXP12/DP4_TXP0 K2
L9 P_GFX_RXN12/RSVD P_GFX_TXN12/DP4_TXN0 K1
J5 P_GFX_RXP13/RSVD P_GFX_TXP13/DP4_TXP1 K3
K4 P_GFX_RXN13/RSVD P_GFX_TXN13/DP4_TXN1 J2
J7 P_GFX_RXP14/RSVD P_GFX_TXP14/DP4_TXP2 J1
J8 P_GFX_RXN14/RSVD P_GFX_TXN14/DP4_TXN2 H1
H4 P_GFX_RXP15/RSVD P_GFX_TXP15/DP4_TXP3 H2
H5 P_GFX_RXN15/RSVD P_GFX_TXN15/DP4_TXN3 G2

C C
PCIE_CRX_DTX_P0 AH4 P_GPP_RXP0 P_GPP_TXP0 AM2 PCIE_CTX_DRX_P0 CC9 1 2 0.1U_0402_10V7-K PCIE_CTX_C_DRX_P0
36 PCIE_CRX_DTX_P0 PCIE_CTX_C_DRX_P0 36
LAN 36 PCIE_CRX_DTX_N0 PCIE_CRX_DTX_N0 AH3 P_GPP_RXN0 P_GPP_TXN0 AM1 PCIE_CTX_DRX_N0 CC10 1 2 0.1U_0402_10V7-K PCIE_CTX_C_DRX_N0 LAN
PCIE_CTX_C_DRX_N0 36
37 PCIE_CRX_DTX_P1 PCIE_CRX_DTX_P1 AG7 P_GPP_RXP1 P_GPP_TXP1 AL2 PCIE_CTX_DRX_P1 CC11 1 2 0.1U_0402_10V7-K PCIE_CTX_C_DRX_P1
PCIE_CTX_C_DRX_P1 37
CardReader 37 PCIE_CRX_DTX_N1 PCIE_CRX_DTX_N1 AF6 P_GPP_RXN1 P_GPP_TXN1 AL1 PCIE_CTX_DRX_N1 CC12 1 2 0.1U_0402_10V7-K PCIE_CTX_C_DRX_N1 CardReader
PCIE_CTX_C_DRX_N1 37
33 PCIE_CRX_DTX_P2 PCIE_CRX_DTX_P2 AE8 P_GPP_RXP2 P_GPP_TXP2 AK2 PCIE_CTX_DRX_P2 CC13 1 2 0.1U_0402_10V7-K PCIE_CTX_C_DRX_P2
PCIE_CTX_C_DRX_P2 33

GPP
WLAN PCIE_CRX_DTX_N2 AE7 P_GPP_RXN2 P_GPP_TXN2 AK1 PCIE_CTX_DRX_N2 CC14 1 2 0.1U_0402_10V7-K PCIE_CTX_C_DRX_N2 WLAN
33 PCIE_CRX_DTX_N2 PCIE_CTX_C_DRX_N2 33
AE5 P_GPP_RXP3 P_GPP_TXP3 AK3
AF4 P_GPP_RXN3 P_GPP_TXN3 AJ2
AC9 P_GPP_RXP4/RSVD P_GPP_TXP4/DP3_TXP0 AJ1 APU_DOCK_TX0+
APU_DOCK_TX0+ 32
AC8 P_GPP_RXN4/RSVD P_GPP_TXN4/DP3_TXN0 AH1 APU_DOCK_TX0-
APU_DOCK_TX0- 32
AC6 P_GPP_RXP5/RSVD P_GPP_TXP5/DP3_TXP1 AH2 APU_DOCK_TX1+
APU_DOCK_TX1+ 32
AC5 P_GPP_RXN5/RSVD P_GPP_TXN5/DP3_TXN1 AG2 APU_DOCK_TX1-
APU_DOCK_TX1- 32
AB9 P_GPP_RXP6/RSVD P_GPP_TXP6/DP3_TXP2 AF2
AB8 P_GPP_RXN6/RSVD P_GPP_TXN6/DP3_TXN2 AF1
AB4 P_GPP_RXP7/RSVD P_GPP_TXP7/DP3_TXP3 AF3
AB5 P_GPP_RXN7/RSVD P_GPP_TXN7/DP3_TXN3 AE2

UMI_CRX_FTX_P0 AJ7 P_UMI_RXP0 P_UMI_TXP0 AM9 UMI_CTX_FRX_P0 CC15 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_P0_C

12 UMI_CRX_FTX_P0 UMI_CTX_FRX_P0_C 12
UMI_CRX_FTX_N0 AJ8 P_UMI_RXN0 P_UMI_TXN0 AM10 UMI_CTX_FRX_N0 CC16 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_N0_C
12 UMI_CRX_FTX_N0 UMI_CTX_FRX_N0_C 12
UMI_CRX_FTX_P1 AK6 P_UMI_RXP1 P_UMI_TXP1 AN8 UMI_CTX_FRX_P1 CC17 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_P1_C
12 UMI_CRX_FTX_P1 UMI_CTX_FRX_P1_C 12
UMI_CRX_FTX_N1 AK7 P_UMI_RXN1 P_UMI_TXN1 AN9 UMI_CTX_FRX_N1 CC18 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_N1_C
12 UMI_CRX_FTX_N1 UMI_CTX_FRX_N1_C 12
UMI_CRX_FTX_P2 AK5 AM7 UMI_CTX_FRX_P2 CC19 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_P2_C

UMI
P_UMI_RXP2 P_UMI_TXP2
12 UMI_CRX_FTX_P2 UMI_CTX_FRX_P2_C 12
UMI_CRX_FTX_N2 AJ5 P_UMI_RXN2 P_UMI_TXN2 AM8 UMI_CTX_FRX_N2 CC20 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_N2_C
12 UMI_CRX_FTX_N2 UMI_CTX_FRX_N2_C 12
UMI_CRX_FTX_P3 AL4 P_UMI_RXP3 P_UMI_TXP3 AN6 UMI_CTX_FRX_P3 CC21 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_P3_C
12 UMI_CRX_FTX_P3 UMI_CTX_FRX_P3_C 12
UMI_CRX_FTX_N3 AK4 P_UMI_RXN3 P_UMI_TXN3 AM6 UMI_CTX_FRX_N3 CC22 1 2 0.1U_0402_10V7-K UMI_CTX_FRX_N3_C
12 UMI_CRX_FTX_N3 UMI_CTX_FRX_N3_C 12
AN18 P_ZVDDP P_ZVSS AM18 RC2 1 2 196_0402_0.5%
+0.95VS_VDDP FP3 REV 0.52

KAVERI ZM187194H4468 3G
A8@
RC1 1 2 196_0402_0.5%

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 APU PEG/PCIe/UMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 4 of 65
5 4 3 2 1
 1 2 3 4 5

DDRB_DQ[0..63] 11

DDRB_MA[0..15] 11

DDRA_MB_DM[0..7] 11
UC3C
A A
MB_DATA0
C18 DDRB_DQ0
DDRB_MA0 AC36 MB_ADD0
MEMORY CHANNEL B
MB_DATA1
B19 DDRB_DQ1
DDRB_MA1 U36 MB_ADD1 MB_DATA2 C22 DDRB_DQ2
DDRB_MA2 U37 MB_ADD2 MB_DATA3 A22 DDRB_DQ3
DDRB_MA3 T35 MB_ADD3 MB_DATA4 A18 DDRB_DQ4
DDRB_MA4 T37 MB_ADD4 MB_DATA5 B18 DDRB_DQ5
DDRB_MA5 T36 MB_ADD5 MB_DATA6 A21 DDRB_DQ6
DDRB_MA6 R36 MB_ADD6 MB_DATA7 B21 DDRB_DQ7
DDRB_MA7 P37 MB_ADD7
DDRB_MA8 P36 MB_ADD8 MB_DATA8 B24 DDRB_DQ8
DDRB_MA9 N36 MB_ADD9 MB_DATA9 A24 DDRB_DQ9
DDRB_MA10 AD36 MB_ADD10 MB_DATA10 B27 DDRB_DQ10
DDRB_MA11 P35 MB_ADD11 MB_DATA11 A28 DDRB_DQ11
DDRB_MA12 N37 MB_ADD12 MB_DATA12 B22 DDRB_DQ12
DDRB_MA13 AH37 MB_ADD13 MB_DATA13 B23 DDRB_DQ13
DDRB_MA14 M36 MB_ADD14 MB_DATA14
B26 DDRB_DQ14
DDRB_MA15 L36 MB_ADD15 MB_DATA15 C26 DDRB_DQ15

DDRB_BA0# AD35 MB_BANK0 MB_DATA16 A29 DDRB_DQ16

11 DDRB_BA0#
DDRB_BA1# AD37 MB_DATA17 B29 DDRB_DQ17
11 DDRB_BA1# MB_BANK1
DDRB_BA2# M37 MB_BANK2 MB_DATA18 B32 DDRB_DQ18
11 DDRB_BA2#
MB_DATA19 C32 DDRB_DQ19
DDRA_MB_DM0 A20 MB_DM0 MB_DATA20 B28 DDRB_DQ20
DDRA_MB_DM1 C24 MB_DM1 MB_DATA21 C28 DDRB_DQ21
DDRA_MB_DM2 A30 MB_DM2 MB_DATA22 B31 DDRB_DQ22
DDRA_MB_DM3 B35 MB_DM3 MB_DATA23 A32 DDRB_DQ23
DDRA_MB_DM4 AL35 MB_DM4
DDRA_MB_DM5 AN32 MB_DM5 MB_DATA24 C34 DDRB_DQ24
DDRA_MB_DM6 AN26 MB_DM6 MB_DATA25 A34 DDRB_DQ25
DDRA_MB_DM7 AN21 MB_DM7 MB_DATA26
C36 DDRB_DQ26
E37 MB_DM8 MB_DATA27 C37 DDRB_DQ27
MB_DATA28 A33 DDRB_DQ28
DDRB_DQS0 C20 MB_DQS_H0 MB_DATA29 B33 DDRB_DQ29
11 DDRB_DQS0
DDRB_DQS#0 B20 MB_DQS_L0 MB_DATA30 D35 DDRB_DQ30
B 11 DDRB_DQS#0 B
DDRB_DQS1 B25 MB_DQS_H1 MB_DATA31 B37 DDRB_DQ31
11 DDRB_DQS1
DDRB_DQS#1 A25
11 DDRB_DQS#1 MB_DQS_L1
DDRB_DQS2 C30 MB_DQS_H2 MB_DATA32 AL36 DDRB_DQ32
11 DDRB_DQS2
DDRB_DQS#2 B30 MB_DQS_L2 MB_DATA33 AM37 DDRB_DQ33
11 DDRB_DQS#2
DDRB_DQS3 B36 MB_DQS_H3 MB_DATA34 AN34 DDRB_DQ34
11 DDRB_DQS3
DDRB_DQS#3 A36 MB_DQS_L3 MB_DATA35 AM34 DDRB_DQ35
11 DDRB_DQS#3
DDRB_DQS4 AN36 MB_DQS_H4 MB_DATA36
AK37 DDRB_DQ36
11 DDRB_DQS4
DDRB_DQS#4 AM36 MB_DQS_L4 MB_DATA37 AK36 DDRB_DQ37
11 DDRB_DQS#4
DDRB_DQS5 AN31 MB_DQS_H5 MB_DATA38 AN35 DDRB_DQ38
11 DDRB_DQS5
DDRB_DQS#5 AM31 MB_DATA39 AL34 DDRB_DQ39
11 DDRB_DQS#5 MB_DQS_L5
DDRB_DQS6 AM25
11 DDRB_DQS6 MB_DQS_H6
DDRB_DQS#6 AL26 MB_DATA40 AL32 DDRB_DQ40
11 DDRB_DQS#6 MB_DQS_L6
DDRB_DQS7 AM20 MB_DQS_H7 MB_DATA41 AM32 DDRB_DQ41
11 DDRB_DQS7
DDRB_DQS#7 AL20 MB_DQS_L7 MB_DATA42 AN29 DDRB_DQ42
11 DDRB_DQS#7
F37 MB_DQS_H8
MB_DATA43 AL28 DDRB_DQ43
F36 MB_DQS_L8 MB_DATA44 AM33 DDRB_DQ44
MB_DATA45 AN33 DDRB_DQ45
AA37 MB_CLK_H0 MB_DATA46 AM30 DDRB_DQ46
AA36 MB_CLK_L0 MB_DATA47 AM29 DDRB_DQ47
DDRB_CLK0 Y37 MB_CLK_H1
11 DDRB_CLK0
DDRB_CLK0# Y36 MB_CLK_L1 MB_DATA48 AM27 DDRB_DQ48
11 DDRB_CLK0#
DDRB_CLK1 Y34 MB_CLK_H2 MB_DATA49 AM26 DDRB_DQ49
11 DDRB_CLK1
DDRB_CLK1# Y35 MB_CLK_L2 MB_DATA50 AN24 DDRB_DQ50
11 DDRB_CLK1#
V35 MB_CLK_H3 MB_DATA51 AM24 DDRB_DQ51
W36 MB_CLK_L3 MB_DATA52 AN28 DDRB_DQ52
MB_DATA53 AM28 DDRB_DQ53
DDRB_CKE0 K36 MB_CKE0 MB_DATA54 AN25 DDRB_DQ54
11 DDRB_CKE0
DDRB_CKE1 K37 MB_CKE1 MB_DATA55 AL24 DDRB_DQ55
11 DDRB_CKE1
K35 MB_CKE2
J37 MB_CKE3 MB_DATA56 AN22 DDRB_DQ56
MB_DATA57 AL22 DDRB_DQ57
DDRB_ODT0 AH36 MB0_ODT0 MB_DATA58 AK18 DDRB_DQ58
11 DDRB_ODT0
DDRB_ODT1 AJ37 MB0_ODT1 MB_DATA59 AL18 DDRB_DQ59
11 DDRB_ODT1
AF35 MB1_ODT0 MB_DATA60 AM23 DDRB_DQ60
C AK35 MB1_ODT1 MB_DATA61 AM22 DDRB_DQ61 C
MB_DATA62 AN20 DDRB_DQ62
DDRB_CS0# AF36 MB0_CS_L0 MB_DATA63 AM19 DDRB_DQ63
11 DDRB_CS0#
DDRB_CS1# AJ36 MB0_CS_L1
11 DDRB_CS1#
AE36 MB1_CS_L0 MB_CHECK0 E36
AH35 MB1_CS_L1 MB_CHECK1 F35
MB_CHECK2 H36
DDRB_RAS# AE37 MB_RAS_L MB_CHECK3 H37
11 DDRB_RAS#
DDRB_CAS# AG36 MB_CAS_L MB_CHECK4 D36
11 DDRB_CAS#
DDRB_WE# AF37 MB_WE_L MB_CHECK5 D37
11 DDRB_WE#
MB_CHECK6 G36
DDRB_RESET# J36 MB_RESET_L MB_CHECK7 H35
11 DDRB_RESET#
DDRB_EVENT# AB36 MB_EVENT_L
11 DDRB_EVENT# RSVD_11 A26
+VREF_DQB B17 MB_VREFDQ RSVD_12 B34
V37 MB_ZVDDIO RSVD_13 AL30
+1.35V_APU_VDDIO RSVD_14 AM21
M35 RSVD_9
RC3 1 2 MB_ZVDDIO AB35 RSVD_10

39.2_0402_1% FP3 REV 0.52

KAVERI ZM187194H4468 3G
A8@

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 APU DDRB/2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 5 of 65
1 2 3 4 5
 1 2 3 4 5

DDRA_DQ[0..63] 10

DDRA_MA[0..15] 10

DDRA_MA_DM[0..7] 10

UC3B

MEMORY CHANNEL A
DDRA_MA0 AB31 MA_ADD0 MA_DATA0 H13 DDRA_DQ0
DDRA_MA1 U33 MA_ADD1 MA_DATA1 F13 DDRA_DQ1
DDRA_MA2 U32 MA_ADD2 MA_DATA2 H16 DDRA_DQ2
A DDRA_MA3 R30 MA_ADD3 MA_DATA3 F16 DDRA_DQ3 A
DDRA_MA4 T34 MA_ADD4 MA_DATA4 G11 DDRA_DQ4
DDRA_MA5 R31 MA_ADD5 MA_DATA5 E11 DDRA_DQ5
DDRA_MA6 R33 MA_ADD6 MA_DATA6 E14 DDRA_DQ6
DDRA_MA7 P33 MA_ADD7 MA_DATA7 J14 DDRA_DQ7
DDRA_MA8 P32 MA_ADD8
DDRA_MA9 P30 MA_ADD9 MA_DATA8 J17 DDRA_DQ8
DDRA_MA10 AD34 MA_ADD10 MA_DATA9 F17 DDRA_DQ9
DDRA_MA11 P34 MA_ADD11 MA_DATA10 H21 DDRA_DQ10
DDRA_MA12 M30 MA_ADD12 MA_DATA11 E21 DDRA_DQ11
DDRA_MA13 AF33 MA_ADD13 MA_DATA12 E16 DDRA_DQ12
DDRA_MA14 M31 MA_ADD14 MA_DATA13 G17 DDRA_DQ13
DDRA_MA15 L32 MA_ADD15 MA_DATA14 F19 DDRA_DQ14
MA_DATA15 D20 DDRA_DQ15
DDRA_BA0# AC33 MA_BANK0
10 DDRA_BA0#
DDRA_BA1# AB30 MA_BANK1 MA_DATA16 D22 DDRA_DQ16
10 DDRA_BA1#
DDRA_BA2# M34 MA_BANK2 MA_DATA17 E22 DDRA_DQ17
10 DDRA_BA2#
MA_DATA18 D26 DDRA_DQ18
DDRA_MA_DM0 E13 MA_DM0 MA_DATA19 E25 DDRA_DQ19
DDRA_MA_DM1 D18 MA_DM1 MA_DATA20 G21 DDRA_DQ20
DDRA_MA_DM2 H22 MA_DM2 MA_DATA21 F22 DDRA_DQ21
DDRA_MA_DM3 H27 MA_DM3 MA_DATA22 G24 DDRA_DQ22
DDRA_MA_DM4 AG30 MA_DM4 MA_DATA23 H24 DDRA_DQ23
DDRA_MA_DM5 AK26 MA_DM5
DDRA_MA_DM6 AK20 MA_DM6 MA_DATA24 E27 DDRA_DQ24
DDRA_MA_DM7 AF14 MA_DM7 MA_DATA25 G27 DDRA_DQ25
F34 MA_DM8 MA_DATA26 E30 DDRA_DQ26
MA_DATA27 G30 DDRA_DQ27
DDRA_DQS0 F14 MA_DQS_H0 MA_DATA28 F25 DDRA_DQ28
10 DDRA_DQS0
DDRA_DQS#0 G14 MA_DQS_L0 MA_DATA29 H25 DDRA_DQ29
10 DDRA_DQS#0
DDRA_DQS1 H19 MA_DQS_H1 MA_DATA30 D30 DDRA_DQ30
10 DDRA_DQS1
DDRA_DQS#1 J19 MA_DQS_L1 MA_DATA31 H28 DDRA_DQ31
10 DDRA_DQS#1
DDRA_DQS2 D24 MA_DQS_H2
10 DDRA_DQS2
DDRA_DQS#2 E24 MA_DQS_L2 MA_DATA32 AJ31 DDRA_DQ32
10 DDRA_DQS#2
DDRA_DQS3 F28 MA_DQS_H3 MA_DATA33 AK32 DDRA_DQ33
B 10 DDRA_DQS3 B
DDRA_DQS#3 E28 MA_DQS_L3 MA_DATA34 AK28 DDRA_DQ34
10 DDRA_DQS#3
DDRA_DQS4 AJ30 MA_DQS_H4 MA_DATA35 AF27 DDRA_DQ35
10 DDRA_DQS4
DDRA_DQS#4 AK30 MA_DQS_L4 MA_DATA36 AJ33 DDRA_DQ36
10 DDRA_DQS#4
DDRA_DQS5 AH24 MA_DQS_H5 MA_DATA37 AK33 DDRA_DQ37
10 DDRA_DQS5
DDRA_DQS#5 AG24 MA_DQS_L5 MA_DATA38 AH28 DDRA_DQ38
10 DDRA_DQS#5
DDRA_DQS6 AG19 MA_DQS_H6 MA_DATA39 AJ28 DDRA_DQ39
10 DDRA_DQS6
DDRA_DQS#6 AF19 MA_DQS_L6
10 DDRA_DQS#6
DDRA_DQS7 AH14 MA_DQS_H7 MA_DATA40 AF25 DDRA_DQ40
10 DDRA_DQS7
DDRA_DQS#7 AJ14 MA_DQS_L7 MA_DATA41 AH25 DDRA_DQ41
10 DDRA_DQS#7
G31 MA_DQS_H8 MA_DATA42 AG22 DDRA_DQ42
F31 MA_DQS_L8 MA_DATA43 AJ22 DDRA_DQ43
MA_DATA44 AH27 DDRA_DQ44
Y30 MA_CLK_H0 MA_DATA45 AJ27 DDRA_DQ45
Y29 MA_CLK_L0 MA_DATA46 AE24 DDRA_DQ46
DDRA_CLK0 Y32 MA_CLK_H1 MA_DATA47 AF22 DDRA_DQ47
10 DDRA_CLK0
DDRA_CLK0# Y33 MA_CLK_L1
10 DDRA_CLK0#
DDRA_CLK1 W33 MA_CLK_H2 MA_DATA48 AH21 DDRA_DQ48
10 DDRA_CLK1
DDRA_CLK1# W34 MA_CLK_L2 MA_DATA49 AJ21 DDRA_DQ49
10 DDRA_CLK1#
W30 MA_CLK_H3 MA_DATA50 AF17 DDRA_DQ50
W31 MA_CLK_L3 MA_DATA51 AJ17 DDRA_DQ51
MA_DATA52 AK22 DDRA_DQ52
DDRA_CKE0 L33 MA_CKE0 MA_DATA53 AF21 DDRA_DQ53
10 DDRA_CKE0
DDRA_CKE1 L30 MA_CKE1 MA_DATA54 AJ19 DDRA_DQ54
10 DDRA_CKE1
K34 MA_CKE2 MA_DATA55 AE17 DDRA_DQ55
J30 MA_CKE3
MA_DATA56 AF16 DDRA_DQ56
DDRA_ODT0 AH34 MA0_ODT0 MA_DATA57 AJ16 DDRA_DQ57
10 DDRA_ODT0
DDRA_ODT1 AH33 MA0_ODT1 MA_DATA58 AF13 DDRA_DQ58
10 DDRA_ODT1
AE30 MA1_ODT0 MA_DATA59 AE13 DDRA_DQ59
AJ34 MA1_ODT1 MA_DATA60 AH17 DDRA_DQ60
MA_DATA61 AE16 DDRA_DQ61
DDRA_CS0# AE31 MA0_CS_L0 MA_DATA62 AJ13 DDRA_DQ62
10 DDRA_CS0#
DDRA_CS1# AG31 MA0_CS_L1 MA_DATA63 AG13 DDRA_DQ63
10 DDRA_CS1#
AC30 MA1_CS_L0
C +1.35V_APU_VDDIO AF32 MA1_CS_L1 MA_CHECK0 E33 C
MA_CHECK1 F33
DDRA_RAS# AC32 MA_RAS_L MA_CHECK2 H31
10 DDRA_RAS#
1

DDRA_CAS# AF34 MA_CAS_L MA_CHECK3 J31

10 DDRA_CAS#
RC5 DDRA_WE# AE33 MA_WE_L MA_CHECK4 D32
10 DDRA_WE#
1K_0402_1% MA_CHECK5 D34
DDRA_RESET# J33 MA_RESET_L MA_CHECK6 H33
10 DDRA_RESET#
DDRA_EVENT# AB33 MA_EVENT_L MA_CHECK7 H34
10 DDRA_EVENT#
2

CC29 CC30 M_VREF V36 M_VREF

+VREF_DQA H11 MA_VREFDQ RSVD_5 E19

0.1U_0402_10V7-K

1000P_0402_50V7-K

U30 MA_ZVDDIO RSVD_6 D28

1

1 1 RSVD_7 AK24
RC6 RC4 1 2 MA_ZVDDIO M33 RSVD_3 RSVD_8 AG16
1K_0402_1% AB34 RSVD_4
39.2_0402_1%
2 2 +1.35V_APU_VDDIO FP3 REV 0.52
2

KAVERI ZM187194H4468 3G
A8@

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 APU DDRA/1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 6 of 65
1 2 3 4 5
 1 2 3 4 5

+1.35V_APU_VDDIO_RUN
H_PROCHOT# : DOCK_HPD
DOCK_HPD 32
RC14 1 2 300_0402_5% APU_RESET#
Normal high
Active low

1
UC3D
1 2 300_0402_5%
RC15 APU_PWROK
Keep low after susp# low RC69
100K_0402_5%
ANALOG/DISPLAY/MISC
RC16 1 @ 2 1K_0402_1% APU_SVT

2
+1.35V_APU_VDDIO
APU_EDP_TX0+ AL6 DP0_TXP0 DP0_AUXP AG8 APU_EDP_AUX
26 APU_EDP_TX0+ APU_EDP_AUX 26
APU_EDP_TX0- AM5 DP0_TXN0 DP0_AUXN AG10 APU_EDP_AUX#
26 APU_EDP_TX0- APU_EDP_AUX# 26

1
APU_EDP_TX1+ AN5 DP0_TXP1 DP1_AUXP B2 APU_VGA_AUX
26 APU_EDP_TX1+ APU_VGA_AUX 13
APU_EDP_TX1- AM4 DP0_TXN1 DP1_AUXN B1 APU_VGA_AUX# RC23
26 APU_EDP_TX1- APU_VGA_AUX# 13

DISPLAY PORT 0
A 1K_0402_1% A
AN4 DP0_TXP2 DP2_AUXP B6 APU_HDMI_CLK
APU_HDMI_CLK 27

2
B
AN3 DP0_TXN2 DP2_AUXN B7 APU_HDMI_DATA
APU_HDMI_DATA 27

2
E
AM3 H7 APU_DOCK_AUX 3 1 APU_PROCHOT#

DISPLAY PORT
DP0_TXP3 DP3_AUXP
APU_DOCK_AUX 32 38 H_PROCHOT#

C
AN2 DP0_TXN3 DP3_AUXN G7 APU_DOCK_AUX#
APU_DOCK_AUX# 32 QC1
APU_PROCHOT# 12

MISC.
APU_VGA_TX0+_C CC31 1 2 0.1U_0402_10V7-K APU_VGA_TX0+ F2 DP1_TXP0 DP4_AUXP Y6 MLMBT3904WT1G NPN SOT323-3
13 APU_VGA_TX0+_C APU_VGA_TX0-_C CC32 1 2 0.1U_0402_10V7-K APU_VGA_TX0- F1 Y5 +1.35V_APU_VDDIO_RUN
DP1_TXN0 DP4_AUXN
13 APU_VGA_TX0-_C
APU_VGA_TX1+_C CC33 1 2 0.1U_0402_10V7-K APU_VGA_TX1+ F3 DP1_TXP1 DP5_AUXP AD2 +3VS RPC1
13 APU_VGA_TX1+_C APU_VGA_TX1-_C CC34 1 2 0.1U_0402_10V7-K APU_VGA_TX1- E2 AC2 +1.35V_APU_VDDIO
DP1_TXN1 DP5_AUXN
13 APU_VGA_TX1-_C

DISPLAY PORT 1
1 8
APU_VGA_TX2+_C CC35 1 2 0.1U_0402_10V7-K APU_VGA_TX2+ E1 DP1_TXP2 DP0_HPD AH7 EDP_HPD 2 7 +1.35V_APU_VDDIO
13 APU_VGA_TX2+_C EDP_HPD 26
APU_VGA_TX2-_C CC36 1 2 0.1U_0402_10V7-K APU_VGA_TX2- D1 DP1_TXN2 DP1_HPD B3 VGA_HPD_R 3 6
13 APU_VGA_TX2-_C VGA_HPD_R 13
DP2_HPD D7 HDMI_HPD 4 5
HDMI_HPD 27 +3VALW
APU_VGA_TX3+_C CC37 1 2 0.1U_0402_10V7-K APU_VGA_TX3+ D2 DP1_TXP3 DP3_HPD F8 DOCK_HPD
13 APU_VGA_TX3+_C APU_VGA_TX3-_C CC38 1 2 0.1U_0402_10V7-K APU_VGA_TX3- C1 AB6 10K_0804_8P4R_5%
DP1_TXN3 DP4_HPD
13 APU_VGA_TX3-_C AD1
DP5_HPD

1
+1.35V_APU_VDDIO APU_HDMI_TX2+ A2 DP2_TXP0
RP4 27 APU_HDMI_TX2+ APU_HDMI_TX2- A3 D12 APU_ENBKL_R RC26
DP2_TXN0 DP_BLON
27 APU_HDMI_TX2- B11 APU_ENVDD 1K_0402_1%
DP_DIGON
APU_ENVDD 26
1 8 ALLOW_STOP APU_HDMI_TX1+ B4 DP2_TXP1 DP_VARY_BL C12 APU_EDP_PWM_R
27 APU_HDMI_TX1+

2
2 7 SIC APU_HDMI_TX1- A4

B
DP2_TXN1

2
27 APU_HDMI_TX1-

DISPLAY PORT 2
3 6 SID DP_AUX_ZVSS D3 RC12 1 2 150_0402_1%
4 5 ALERT# APU_HDMI_TX0+ C4 1 3 THERMTRIP#

E
DP2_TXP2
27 APU_HDMI_TX0+ 14,18 H_THERMTRIP#
APU_HDMI_TX0- B5 L27 APU_TEST6 TPC4 1 Test_Point_20MIL

C
DP2_TXN2 TEST6
1K_0804_8P4R_5% 27 APU_HDMI_TX0- P27 APU_TEST9 RC59 1 @ 2 1K_0402_1% QC2
TEST9
APU_HDMI_CLK+ A5 DP2_TXP3 TEST10 P28 APU_TEST10 TPC5 1 Test_Point_20MIL MLMBT3904WT1G NPN SOT323-3
27 APU_HDMI_CLK+ APU_HDMI_CLK- A6 C10 APU_TEST14 RC60 1 @ 2 1K_0402_1%
DP2_TXN3 TEST14
27 APU_HDMI_CLK- B9 APU_TEST15 TPC6 1 Test_Point_20MIL
TEST15
APU_CLKP AM13 CLKIN_H TEST16 A10 APU_TEST16 RC61 1 @ 2 1K_0402_1% +3VS
12 APU_CLKP

CLK
APU_CLKN AN13 B10 APU_TEST17 RC62 1 @ 2 1K_0402_1%

TEST
CLKIN_L TEST17
12 APU_CLKN
TEST18 A12 APU_TEST18 RC63 1 2 1K_0402_1%
DISP_CLKP AM11 DISP_CLKIN_H TEST19 B12 APU_TEST19 RC64 1 2 1K_0402_1%
12 DISP_CLKP

2
B +0.95VS_VDDP B
DISP_CLKN AN11 DISP_CLKIN_L TEST20 C8 APU_TEST20 RC65 1 2 1K_0402_1%
12 DISP_CLKN
AJ10 RSVD_16 TEST24 D8 APU_TEST24 RC66 1 2 1K_0402_1% RC31
TEST25_H AM12 RC35 1 2 510_0402_1% 2.2K_0402_5%

2
APU_SVC B16 SVC TEST25_L AN12 RC36 1 2 510_0402_1%
57 APU_SVC
APU_SVD C16 SVD TEST28_H A8 APU_TEST28_H TPC7 1 Test_Point_20MIL RC30 RC43 1 2 0_0402_5% @
57 APU_SVD APU_ENBKL 38

1
APU_SVT A16 B8 APU_TEST28_L TPC8 1 Test_Point_20MIL 100K_0402_5%

SER.
SVT TEST28_L
57 APU_SVT
AA27 APU_TEST30_H TPC9 1 Test_Point_20MIL
Check connect to FCH or EC FCH_SCL3_LV RC10 1 @ 2 0_0402_5% SIC AL14 SIC
TEST30_H
TEST30_L AA28 APU_TEST30_L TPC10 1 Test_Point_20MIL
APU_BKOFF# 26
14 FCH_SCL3_LV

1
FCH_SDA3_LV RC11 1 @ 2 0_0402_5% SID AK14 SID TEST31 V28 APU_TEST31
14 FCH_SDA3_LV

1
Y27 APU_TEST32_H TPC12 1 Test_Point_20MIL D
TEST32_H
APU_RESET# AM14 RESET_L TEST32_L Y28 APU_TEST32_L TPC11 1 Test_Point_20MIL 2 QC8
12 APU_RESET#
1 APU_PWROK AL12 PWROK G 2N7002KW_SOT323-3
12,57 APU_PWROK

CTRL
S SB00000YY00

3
1
CC169 APU_PROCHOT# AL10 PROCHOT_L RSVD_15 AK10 RC29 C
0.1U_0402_10V7-K THERMTRIP# AK11 AM15 ALLOW_STOP APU_ENBKL_R 1 2 2 MLMBT3904WT1G NPN SOT323-3
THERMTRIP_L DMAACTIVE_L
2 ALLOW_STOP 12 QC4
ALERT# AN15 ALERT_L B
T27 APU_TEST4 TPC16 1 Test_Point_20MIL 2.2K_0402_5% E

MISC
TEST4

3
2
APU_TDI A14 TDI TEST5 T28 APU_TEST5 TPC17 1 Test_Point_20MIL
APU_TDO C14 TDO RC73
APU_TCK B15 TCK DP_STEREOSYNC A9 RC42 2 1 +1.35V_APU_VDDIO 100K_0402_5%
APU_TMS B14 TMS @

JTAG
APU_TRST# D14 TRST_L CORETYPE D16 300_0402_5% +3VS

1
2
APU_DBRDY A13 DBRDY

RSVD
Test_Point_20MIL 1 TPC1 APU_DBREQ# B13 DBREQ_L RC20
RSVD_1 A17 300_0402_5%

2
VSS_SENSE E10 VSS_SENSE_A RSVD_2 K28 @
57 VSS_SENSE
VDD_SENSE D9 VDD_SENSE RC34
57 VDD_SENSE

1
VDDNB_SENSE D10 VDDNB_SENSE 4.7K_0402_5%
57 VDDNB_SENSE

2
SENSE

Test_Point_20MIL 1 TPC13 F10 VDDIO_SENSE RSVD_17 F7

Test_Point_20MIL 1 TPC2 Test_Point_20MIL 1 TPC14 AE10 VDDP_SENSE RSVD_18 E4 RC33

1
AUDIO
Test_Point_20MIL 1 TPC3 Test_Point_20MIL 1 TPC15 AF11 VDDR_SENSE RSVD_19 E5 47K_0402_5%
AF10 VSS_SENSE_B RSVD_20 E7 +1.35V_APU_VDDIO APU_EDP_PWM
APU_EDP_PWM 26
RSVD_21 D5

1
FP3 REV 0.52

1
D
C C

2
2 QC9
KAVERI ZM187194H4468 3G RC67 G 2N7002KW_SOT323-3
A8@ 39.2_0402_1% S SB00000YY00

3
1
@ RC32 C
+VDDNB_CORE +VDD_CORE APU_EDP_PWM_R 1 2 2 MLMBT3904WT1G NPN SOT323-3

1
B QC5
RP5 APU_TEST31 2.2K_0402_5% E

3
2
2
1 8 RC74
2 7 VDD_SENSE RC68 4.7K_0402_5%
3 6 VDDNB_SENSE 39.2_0402_1% @
4 5 VSS_SENSE @ +3VS

1
1
100_1206_8P4R_5%

1
+1.35V_APU_VDDIO RC71
@ 3.3K_0402_1%
R137
APU_RESET# 1 2 APU_RESET#_R JDB ME@

2
1
1 RC72
2
0_0402_5% APU_TDI 3 2 1 2
APU_TDO 4 3
+1.35V_APU_VDDIO APU_TCK 5 4
APU_TMS 6 5 3K_0402_5%
RP6 APU_TRST# 7 6
7

2
APU_DBRDY 8
1 8 APU_TRST# APU_DBREQ# 9 8

G
2 7 APU_TMS APU_TEST19 10 9
3 6 APU_TCK APU_TEST18 11 10 EC_SMB_CK3 1 3 SIC
11 18,29,38 EC_SMB_CK3
4 5 APU_TDI APU_PWROK 12
12

2
APU_RESET#_R 13 QC6

S
D
1K_0804_8P4R_5% 14 13 BSH111_SOT23-3 D

G
15 14
16 15 EC_SMB_DA3 1 3 SID
+1.35V_APU_VDDIO +1.35V_APU_VDDIO_RUN 16 18,29,38 EC_SMB_DA3
17
18 17 QC7

S
19 18 BSH111_SOT23-3
20 19
21 20
22 GND1
GND2 Security Classification LC Future Center Secret Data Title
RC41 1 2 1K_0402_1% APU_DBREQ# ACES_88194-2041
Issued Date 2012/07/01 Deciphered Date 2014/07/01 APU Misc
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 7 of 65
1 2 3 4 5
 1 2 3 4 5

+VDD_CORE +VDDNB_CORE +1.35V_APU_VDDIO VDD_CORE

UC3E UC3F 22u 6.3V *11 @*2 Design Guide
POWER POWER
0.22u 10V *2
T11 E8 L29
0.01u 10V *3
VDD_1 VDDNB_1 VDDIO_1
T14 VDD_2 VDDNB_2 F4 L31 VDDIO_2
180p *3
T17 VDD_3 VDDNB_3 F5 L34 VDDIO_3
T21 VDD_4 VDDNB_4 G4 L37 VDDIO_4
T24 VDD_5 VDDNB_5 G8 M29 VDDIO_5
+VDD_CORE +VDD_CORE
V10 VDD_6 VDDNB_6 G10 M32 VDDIO_6
V13 VDD_7 VDDNB_7 H3 N27 VDDIO_7
A V16 VDD_8 VDDNB_8 H6 N34 VDDIO_8 2 2 1 1 1 A
V19 VDD_9 VDDNB_9 H10 P29 VDDIO_9
V22 VDD_10 VDDNB_10 J10 P31 VDDIO_10 CC42 CC43 CC44 CC45 CC46
V24 VDD_11 VDDNB_11 J13 R29 VDDIO_11 0.22U_0402_10V6-K 0.22U_0402_10V6-K .01U_0402_16V7-K .01U_0402_16V7-K .01U_0402_16V7-K
Y7 J22 R32 1 1 2@ 2 2
VDD_12 VDDNB_12 VDDIO_12
Y10 VDD_13 VDDNB_13 J25 R34 VDDIO_13
Y13 VDD_14 VDDNB_14 K11 R37 VDDIO_14
Y16 VDD_15 VDDNB_15 K14 U29 VDDIO_15
Y19 VDD_16 VDDNB_16 K17 U31 VDDIO_16
Y22 VDD_17 VDDNB_17 K21 U34 VDDIO_17
+VDD_CORE
Y25 VDD_18 VDDNB_18 K24 V27 VDDIO_18
AA4 VDD_19 VDDNB_19 L4 V34 VDDIO_19
AA11 VDD_20 VDDNB_20 L7 W29 VDDIO_20 1 1 1
AA14 VDD_21 VDDNB_21 L10 W32 VDDIO_21
AA17 VDD_22 VDDNB_22 L13 W37 VDDIO_22 CC47 CC48 CC49
AA21 VDD_23 VDDNB_23 L16 Y31 VDDIO_23 180P_0402_50V8-J 180P_0402_50V8-J 180P_0402_50V8-J
AA24 VDD_24 VDDNB_24 L19 AA34 VDDIO_24
2@ 2 2
AB7 VDD_25 VDDNB_25 L22 AB29 VDDIO_25
AC4 VDD_26 VDDNB_26 L25 AB32 VDDIO_26
AC10 M3 AB37
AC13
VDD_27
VDD_28
VDDNB_27
VDDNB_28 N11 AC29
VDDIO_27
VDDIO_28
VDDNB_CORE
AC16 VDD_29 VDDNB_29 N14 AC31 VDDIO_29 22u 6.3V *10 @*2 Design Guide
AC19 N17 AC34
AC22
VDD_30
VDD_31
VDDNB_30
VDDNB_31 N21 AC37
VDDIO_30
VDDIO_31
0.22u 10V *3
AC25
AD4
VDD_32 VDDNB_32 N24
P10
AE32
AE34
VDDIO_32 180p 10V *4
VDD_33 VDDNB_33 VDDIO_33
AD11 VDD_34 VDDNB_34 P13 AF30 VDDIO_34
AD14 VDD_35 VDDNB_35 P16 AF31 VDDIO_35
+VDDNB_CORE
AD17 VDD_36 VDDNB_36 P19 AG34 VDDIO_36
AD21 VDD_37 VDDNB_37 P22 AG37 VDDIO_37
AD24 VDD_38 VDDNB_38 P25 1 1 1 1
AE6 VDD_39 VDDNB_39 R4
AE22 VDD_40 VDDNB_40 R6 CC65 CC66 CC67 CC68
AE25 VDD_41 VDDNB_41 R9 180P_0402_50V8-J 180P_0402_50V8-J 180P_0402_50V8-J 180P_0402_50V8-J
AF5 T3 2@ 2 2 2
VDD_42 VDDNB_42
B B
AF8 VDD_43
AG11 VDD_44
+0.95VS_VDDP +0.95VS_VDDR
AH5 VDD_45
AH8 VDD_46
AH10 VDD_47 AK16 VDDP_1 VDDR_1 AK17 +VDDR_CAP +VDDNB_CORE
AK8 VDD_48 AL16 VDDP_2 VDDR_2 AM17
AM16 VDDP_3 VDDR_3 AN17
AN16 VDDP_4 CC27 CC28 2 2 2
+VDDR_CAP CC62 CC63 CC64

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1 1 0.22U_0402_10V6-K 0.22U_0402_10V6-K 0.22U_0402_10V6-K
+1.8VS_VDDA 1@ 1 1
FP3 REV 0.52 VDDR_CAP AC27

AH11 2 @ 2
KAVERI ZM187194H4468 3G
VDDA_1
VDDA_2 AJ11
VDDP
A8@ CC79 CC80 AC11 VDDP_CAP 22u 6.3V *3
D6
RSVD_22
0.22u 10V *2
FP3 REV 0.52
180p 10V *2
22U_0603_6.3V6-M

22U_0603_6.3V6-M

1 1
KAVERI ZM187194H4468 3G
A8@
2 @ 2 +0.95VS_VDDP +0.95VS_VDDP

CC69 CC70 CC71

1 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1 1 1 CC74 CC75
+1.35V_APU_VDDIO @ 180P_0402_50V8-J 180P_0402_50V8-J
@ 2 2
CC104 CC105
2 2 2
180P_0402_50V8-J

180P_0402_50V8-J

C 1 1 C

+0.95VS_VDDP
VDDR
2 2 22u 6.3V *4
0.22u 10V *2 2 2
180p 10V *2 CC72 CC73
0.22U_0402_10V6-K 0.22U_0402_10V6-K
1 1@
+1.35V_APU_VDDIO +0.95VS_VDDR +0.95VS_VDDR

CC85 CC86 CC87 CC88 CC89 CC90 CC91 CC92 CC93 CC81 CC82 CC83 CC84
VDDA
4.7u 6.3V *1
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1 1 1 1 2 2
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

1 1 1 1 1 1 1 1 1
CC23 CC24 0.22u 10V *1
@ 2 2 @ 2 2 1
0.22U_0402_10V6-K 0.22U_0402_10V6-K
1@
3.3n 10V *1
@ 2 2 2 @ 2 2 2 2 2 2

+1.8VS_VDDA

+0.95VS_VDDR
1 2 1
+1.35V_APU_VDDIO
1 1 CC76 CC77 CC78
CC94 CC95 CC96 CC97 CC98 CC99 CC100 CC101 CC102 CC103 4.7U_0603_6.3V6-K 0.22U_0402_10V6-K 3300P_0402_50V7-K
CC25 CC26 2 1 2
180P_0402_50V8-J 180P_0402_50V8-J
2 2@
0.22U_0402_10V6-K

0.22U_0402_10V6-K

0.22U_0402_10V6-K

0.22U_0402_10V6-K

0.22U_0402_10V6-K

0.22U_0402_10V6-K

0.22U_0402_10V6-K

0.22U_0402_10V6-K

0.22U_0402_10V6-K

0.22U_0402_10V6-K

2 2 2 2 2 2 2 2 2 2

D
@ 1 @ 1 1 1 1 1 1 1 1 1 D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 APU Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 8 of 65
1 2 3 4 5
 1 2 3 4 5

UC3G UC3H
A A
VSS
VSS
A1 VSS_1 VSS_61 K13 AC1 VSS_121 VSS_181 AN10
A7 VSS_2 VSS_62 K16 AC7 VSS_122 VSS_182 AN14
A11 VSS_3 VSS_63 K19 AC14 VSS_123 VSS_183 AN19
A15 VSS_4 VSS_64 K22 AC17 VSS_124 VSS_184 AN23
A19 VSS_5 VSS_65 K25 AC21 VSS_125 VSS_185 AN27
A23 VSS_6 VSS_66 L1 AC24 VSS_126 VSS_186 AN30
A27 VSS_7 VSS_67 L11 AC28 VSS_127 VSS_187 AN37
A31 VSS_8 VSS_68 L14 AD3 VSS_128 VSS_188 AD27
A35 VSS_9 VSS_69 L17 AD10 VSS_129 VSS_189 K27
A37 VSS_10 VSS_70 L21 AD13 VSS_130 VSS_190 AE11
C2 VSS_11 VSS_71 L24 AD16 VSS_131
C3 VSS_12 VSS_72 L28 AD19 VSS_132
C6 VSS_13 VSS_73 M6 AD22 VSS_133
C35 VSS_14 VSS_74 M9 AD25 VSS_134
D4 VSS_15 VSS_75 N4 AD28 VSS_135
D11 VSS_16 VSS_76 N10 AE1 VSS_136
D13 VSS_17 VSS_77 N13 AE4 VSS_137
D15 VSS_18 VSS_78 N16 AE14 VSS_138
D17 VSS_19 VSS_79 N19 AE19 VSS_139
D19 VSS_20 VSS_80 N22 AE21 VSS_140
D21 VSS_21 VSS_81 N25 AE27 VSS_141
D23 VSS_22 VSS_82 N28 AE28 VSS_142
D25 VSS_23 VSS_83 P6 AF7 VSS_143
D27 VSS_24 VSS_84 P9 AF24 VSS_144
D29 VSS_25 VSS_85 P11 AF28 VSS_145
D31 VSS_26 VSS_86 P14 AG1 VSS_146
D33 VSS_27 VSS_87 P17 AG4 VSS_147
E17 VSS_28 VSS_88 P21 AG14 VSS_148
E31 VSS_29 VSS_89 P24 AG17 VSS_149
E34 VSS_30 VSS_90 R1 AG21 VSS_150
F11 VSS_31 VSS_91 T10 AG25 VSS_151
F21 VSS_32 VSS_92 T13 AG27 VSS_152
F24 VSS_33 VSS_93 T16 AG28 VSS_153
B B
F27 VSS_34 VSS_94 T19 AH13 VSS_154
F30 VSS_35 VSS_95 T22 AH16 VSS_155
G1 VSS_36 VSS_96 T25 AH19 VSS_156
G13 VSS_37 VSS_97 U4 AH22 VSS_157
G16 VSS_38 VSS_98 U6 AH30 VSS_158
G19 VSS_39 VSS_99 U9 AH31 VSS_159
G22 VSS_40 VSS_100 V11 AJ4 VSS_160
G25 VSS_41 VSS_101 V14 AJ24 VSS_161
G28 VSS_42 VSS_102 V17 AJ25 VSS_162
G34 VSS_43 VSS_103 V21 AK9 VSS_163
G37 VSS_44 VSS_104 V25 AK12 VSS_164
H8 VSS_45 VSS_105 W1 AK13 VSS_165
H14 VSS_46 VSS_106 W4 AK15 VSS_166
H17 VSS_47 VSS_107 W6 AK19 VSS_167
H30 VSS_48 VSS_108 W9 AK21 VSS_168
H32 VSS_49 VSS_109 Y3 AK23 VSS_169
J4 VSS_50 VSS_110 Y11 AK25 VSS_170
J6 VSS_51 VSS_111 Y14 AK27 VSS_171
J11 VSS_52 VSS_112 Y17 AK29 VSS_172
J16 VSS_53 VSS_113 Y21 AK31 VSS_173
J21 VSS_54 VSS_114 Y24 AK34 VSS_174
J24 VSS_55 VSS_115 AA10 AL3 VSS_175
J27 VSS_56 VSS_116 AA13 AL8 VSS_176
J28 VSS_57 VSS_117 AA16 AL37 VSS_177
J32 VSS_58 VSS_118 AA19 AM35 VSS_178
J34 VSS_59 VSS_119 AA22 AN1 VSS_179
K10 VSS_60 VSS_120 AA25 AN7 VSS_180

FP3 REV 0.52 FP3 REV 0.52

KAVERI ZM187194H4468 3G KAVERI ZM187194H4468 3G

A8@ A8@

C C

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 APU GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 9 of 65
1 2 3 4 5
 5 4 3 2 1

DDR3L SO-DIMM A
+1.35V_DDR_VDDIOSUS +1.35V_DDR_VDDIOSUS
[email protected]

JDIMM1
+VREF_DQA 1 2
3 VREF_DQ VSS1 4 DDRA_DQ4
VSS2 DQ4 DDRA_DQ[0..63] 6
DDRA_DQ0 5 6 DDRA_DQ5
DDRA_DQ1 7 DQ0 DQ5 8
D D
DQ1 VSS3 DDRA_DQS[0..7] 6
9 10 DDRA_DQS#0
DDRA_MA_DM0 11 VSS4 DQS#0 12 DDRA_DQS0
6 DDRA_MA_DM0 DM0 DQS0 DDRA_DQS#[0..7] 6
13 14
DDRA_DQ2 15 VSS5 VSS6 16 DDRA_DQ6
1 1 DQ2 DQ6 DDRA_MA[0..15] 6
CD1 CD2 DDRA_DQ3 17 18 DDRA_DQ7

1000P_0402_50V7-K
0.1U_0402_10V7-K

19 DQ3 DQ7 20
DDRA_DQ8 21 VSS7 VSS8 22 DDRA_DQ12
2 2 DDRA_DQ9 23 DQ8 DQ12 24 DDRA_DQ13
25 DQ9 DQ13 26
DDRA_DQS#1 27 VSS9 VSS10 28 DDRA_MA_DM1
DDRA_DQS1 29
31
DQS#1
DQS1
DM1
RESET#
30
32
DDRA_RESET#
DDRA_MA_DM1
DDRA_RESET#
6
6 DDR Decoupling
DDRA_DQ10 33 VSS11 VSS12 34 DDRA_DQ14
DDRA_DQ11 35 DQ10 DQ14 36 DDRA_DQ15 +1.35V_DDR_VDDIOSUS
Close to JDIMM1.1 DDRA_DQ16
37
39
DQ11
VSS13
DQ15
VSS14
38
40 DDRA_DQ20
0.1uF *6, 330uF *1
DDRA_DQ17 41 DQ16 DQ20 42 DDRA_DQ21 CD7 CD8 CD9 CD10
43 DQ17 DQ21 44
+1.35V_DDR_VDDIOSUS +VREF_DQA DDRA_DQS#2 45 VSS15
DQS#2
VSS16
DM2
46 DDRA_MA_DM2 DDRA_MA_DM2 6 Layout Note :

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
DDRA_DQS2 47 48 1 1 1 1
49 DQS2
VSS18
VSS17
DQ22
50 DDRA_DQ22 1. Placed near JDIMM1
1

DDRA_DQ18 51 52 DDRA_DQ23
RD11
1K_0402_1%
DDRA_DQ19 53
55
DQ18
DQ19
DQ23
VSS19
54
56 DDRA_DQ28 @ 2 2 2 2 2. Place these 4 Caps near Command
VSS20 DQ28
DDRA_DQ24
DDRA_DQ25
57
59 DQ24 DQ29
58
60
DDRA_DQ29
and Control signals of DIMMA
2

61 DQ25 VSS21 62 DDRA_DQS#3

DDRA_MA_DM3 63 VSS22 DQS#3 64 DDRA_DQS3
6 DDRA_MA_DM3 DM3 DQS3
65 66
DDRA_DQ26 67 VSS23 VSS24 68 DDRA_DQ30
DQ26 DQ30
1

DDRA_DQ27 69 70 DDRA_DQ31
RD12 71 DQ27 DQ31 72
1K_0402_1% VSS25 VSS26
CD11 CD12 CD13 CD14 CD15 CD19
C C
2

6 DDRA_CKE0 DDRA_CKE0 73 74 DDRA_CKE1 1

CKE0 CKE1 DDRA_CKE1 6

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

330U_D2_2VM_R9M
75 76 1 1 1 1 1
77 VDD1 VDD2 78 DDRA_MA15 @ +
DDRA_BA2# 79 NC1 A15 80 DDRA_MA14
6 DDRA_BA2# BA2 A14
81 82
DDRA_MA12 83 VDD3 VDD4 84 DDRA_MA11 @ 2 2 @2 @ 2 @ 2 2
DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
87 A9 A7 88
DDRA_MA8 89 VDD5 VDD6 90 DDRA_MA6
DDRA_MA5 91 A8 A6 92 DDRA_MA4
93 A5 A4 94
DDRA_MA3 95 VDD7 VDD8 96 DDRA_MA2
DDRA_MA1 97 A3 A2 98 DDRA_MA0
99 A1 A0 100
DDRA_CLK0 101 VDD9 VDD10 102 DDRA_CLK1
6 DDRA_CLK0 CK0 CK1 DDRA_CLK1 6
6 DDRA_CLK0# DDRA_CLK0# 103 104 DDRA_CLK1#
CK0# CK1# DDRA_CLK1# 6
105 106
DDRA_MA10 107 VDD11 VDD12 108 DDRA_BA1#
A10/AP BA1 DDRA_BA1# 6
6 DDRA_BA0# DDRA_BA0# 109 110 DDRA_RAS#
BA0 RAS# DDRA_RAS# 6
111 112
DDRA_WE# 113 VDD13 VDD14 114 DDRA_CS0#
6 DDRA_WE# WE# S0# DDRA_CS0# 6
6 DDRA_CAS# DDRA_CAS# 115 116 DDRA_ODT0
CAS# ODT0 DDRA_ODT0 6
117 118
DDRA_MA13 119 VDD15 VDD16 120 DDRA_ODT1 +0.675VS
A13 ODT1 DDRA_ODT1 6
DDRA_CS1# 121 122
6 DDRA_CS1# S1# NC2
123 124
125 VDD17 VDD18 126 CD21 CD22 CD23
NCTEST VREF_CA +V_SM_VREF_CNTA
127 128
DDRA_DQ32 129 VSS27
DQ32
VSS28
DQ36
130 DDRA_DQ36 Layout Note : Placed near

4.7U_0603_6.3V6-K

1U_0402_6.3V6-K

0.1U_0402_10V7-K
DDRA_DQ33 131 132 DDRA_DQ37 1 1 1
DDRA_DQS#4
133
135
DQ33
VSS29
DQ37
VSS30
134
136 DDRA_MA_DM4
JDIMM1.Pin203, 204
DQS#4 DM4 DDRA_MA_DM4 6
DDRA_DQS4 137 138
139 DQS4 VSS31 140 DDRA_DQ38 2 @ 2 2
B B
DDRA_DQ34 141 VSS32 DQ38 142 DDRA_DQ39
DQ34 DQ39 1 1
DDRA_DQ35 143 144 CD5 CD6

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M
145 DQ35 VSS33 146 DDRA_DQ44
DDRA_DQ40 147 VSS34 DQ44 148 DDRA_DQ45
DDRA_DQ41 149 DQ40 DQ45 150 2 2
151 DQ41 VSS35 152 DDRA_DQS#5
DDRA_MA_DM5 153 VSS36 DQS#5 154 DDRA_DQS5
6 DDRA_MA_DM5 DM5 DQS5
155 156
DDRA_DQ42 157 VSS37 VSS38 158 DDRA_DQ46
DDRA_DQ43 159 DQ42 DQ46 160 DDRA_DQ47
161 DQ43 DQ47 162
DDRA_DQ48 163 VSS39 VSS40 164 DDRA_DQ52 close to JDIMM1.126
All VREF traces should have 20 mil trace width
DDRA_DQ49 165 DQ48 DQ52 166 DDRA_DQ53
167 DQ49 DQ53 168
DDRA_DQS#6 169 VSS41 VSS42 170 DDRA_MA_DM6 +1.35V_DDR_VDDIOSUS +1.35V_DDR_VDDIOSUS +V_SM_VREF_CNTA +1.35V_DDR_VDDIOSUS
DQS#6 DM6 DDRA_MA_DM6 6
DDRA_DQS6 171 172
173 DQS6 VSS43 174 DDRA_DQ54
VSS44 DQ54

1
DDRA_DQ50 175 176 DDRA_DQ55 RFC1 RFC2
DDRA_DQ51 177 DQ50 DQ55 178 RD6 RD9
DQ51 VSS45

2200P_0402_50V7-K
179 180 DDRA_DQ60 1K_0402_1% 1K_0402_1%
VSS46 DQ60

47P_0402_50V8-J
DDRA_DQ56 181 182 DDRA_DQ61 2 1
DDRA_DQ57 183 DQ56 DQ61 184

RF_NS@
2

2
185 DQ57 VSS47 186 DDRA_DQS#7
VSS48 DQS#7

RF@
SPD setting (SA0, SA1) 6 DDRA_MA_DM7 DDRA_MA_DM7 187 188 DDRA_DQS7 DDRA_EVENT#
189 DM7 DQS7 190 1 2
PU/PD by Channel A/B VSS49 VSS50
DDRA_DQ58 191 192 DDRA_DQ62
->Channel A 00 DQ58 DQ62

1
DDRA_DQ59 193 194 DDRA_DQ63
->Channel B 01 195 DQ59 DQ63 196 RD10
197 VSS51 VSS52 198 DDRA_EVENT# 1K_0402_1%
SA0 EVENT# DDRA_EVENT# 6
199 200 FCH_SMB_DA0 For RF
+3VS VDDSPD SDA FCH_SMB_DA0 11,14
201 202 FCH_SMB_CK0
FCH_SMB_CK0 11,14

2
203 SA1 SCL 204
1 2 VTT1 VTT2 +0.675VS

A
CD3 CD4 205
G1 G2
206 [email protected] A
2.2U_0402_6.3V6-M 0.1U_0402_10V7-K
@ 2 1 LCN_DAN06-K4406-0102
ME@

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 DDR3L SO-DIMMA/1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 10 of 65
5 4 3 2 1
 5 4 3 2 1

DDR3L SO-DIMM B
+1.35V_DDR_VDDIOSUS +1.35V_DDR_VDDIOSUS
[email protected]

JDIMM2
+VREF_DQB 1 2
3 VREF_DQ VSS_2 4 DDRB_DQ4
VSS_1 DQ4 DDRB_DQ[0..63] 5
DDRB_DQ0 5 6 DDRB_DQ5
DDRB_DQ1 7 DQ0 DQ5 8
D D
DQ1 VSS_4 DDRB_DQS[0..7] 5
9 10 DDRB_DQS#0
DDRA_MB_DM0 11 VSS_3 DQS0# 12 DDRB_DQS0
5 DDRA_MB_DM0 DM0 DQS0 DDRB_DQS#[0..7] 5
13 14
DDRB_DQ2 15 VSS_5 VSS_6 16 DDRB_DQ6
1 1 DQ2 DQ6 DDRB_MA[0..15] 5
CD24 CD25 DDRB_DQ3 17 18 DDRB_DQ7

1000P_0402_50V7-K
0.1U_0402_10V7-K

19 DQ3 DQ7 20
DDRB_DQ8 21 VSS_7 VSS_8 22 DDRB_DQ12
2 2 DDRB_DQ9 23 DQ8 DQ12 24 DDRB_DQ13
25 DQ9 DQ13 26
DDRB_DQS#1 27 VSS_9 VSS_10 28 DDRA_MB_DM1
DDRB_DQS1 29
31
DQS1#
DQS1
DM1
RESET#
30
32
DDRB_RESET#
DDRA_MB_DM1
DDRB_RESET#
5
5 DDR Decoupling
DDRB_DQ10 33 VSS_11 VSS_12 34 DDRB_DQ14
DDRB_DQ11 35 DQ10 DQ14 36 DDRB_DQ15 +1.35V_DDR_VDDIOSUS
Close to JDIMM2.1 DDRB_DQ16
37
39
DQ11
VSS_13
DQ15
VSS_14
38
40 DDRB_DQ20
0.1uF *4
DDRB_DQ17 41 DQ16 DQ20 42 DDRB_DQ21 CD30 CD31 CD32 CD33
43 DQ17 DQ21 44
+1.35V_DDR_VDDIOSUS +VREF_DQB DDRB_DQS#2 45 VSS_15
DQS2#
VSS_16
DM2
46 DDRA_MB_DM2 DDRA_MB_DM2 5 Layout Note :

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
DDRB_DQS2 47 48 1 1 1 1
49 DQS2
VSS_17
VSS_18
DQ22
50 DDRB_DQ22 1. Placed near JDIMM2
1

DDRB_DQ18 51 52 DDRB_DQ23
RD13
1K_0402_1%
DDRB_DQ19 53
55
DQ18
DQ19
DQ23
VSS_20
54
56 DDRB_DQ28 @ 2 @ 2 2 2 2. Place these 4 Caps near Command
VSS_19 DQ28
DDRB_DQ24
DDRB_DQ25
57
59 DQ24 DQ29
58
60
DDRB_DQ29
and Control signals of DIMMB
2

61 DQ25 VSS_22 62 DDRB_DQS#3

DDRA_MB_DM3 63 VSS_21 DQS3# 64 DDRB_DQS3
5 DDRA_MB_DM3 DM3 DQS3
65 66
DDRB_DQ26 67 VSS_23 VSS_24 68 DDRB_DQ30
DQ26 DQ30
1

DDRB_DQ27 69 70 DDRB_DQ31
RD14 71 DQ27 DQ31 72
1K_0402_1% VSS_25 VSS_26
CD34 CD35 CD36 CD37 CD38
C C
DDRB_CKE0 73 74 DDRB_CKE1
5 DDRB_CKE0 DDRB_CKE1 5
2

75 CKE0 CKE1 76
VDD_1 VDD_2

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
77 78 DDRB_MA15 1 1 1 1 1
DDRB_BA2# 79 NC_1 A15 80 DDRB_MA14
5 DDRB_BA2# BA2 A14
81 82
DDRB_MA12 83 VDD_3 VDD_4 84 DDRB_MA11
DDRB_MA9 85 A12/BC# A11 86 DDRB_MA7 2 2 @2 @ 2 @ 2
87 A9 A7 88
DDRB_MA8 89 VDD_5 VDD_6 90 DDRB_MA6
DDRB_MA5 91 A8 A6 92 DDRB_MA4
93 A5 A4 94
DDRB_MA3 95 VDD_7 VDD_8 96 DDRB_MA2
DDRB_MA1 97 A3 A2 98 DDRB_MA0
99 A1 A0 100
DDRB_CLK0 101 VDD_9 VDD_10 102 DDRB_CLK1
5 DDRB_CLK0 CK0 CK1 DDRB_CLK1 5
DDRB_CLK0# 103 104 DDRB_CLK1#
5 DDRB_CLK0# CK0# CK1# DDRB_CLK1# 5
105 106
DDRB_MA10 107 VDD_11 VDD_12 108 DDRB_BA1#
A10/AP BA1 DDRB_BA1# 5
5 DDRB_BA0# DDRB_BA0# 109 110 DDRB_RAS#
BA0 RAS# DDRB_RAS# 5
111 112
DDRB_WE# 113 VDD_13 VDD_14 114 DDRB_CS0#
5 DDRB_WE# WE# S0# DDRB_CS0# 5
5 DDRB_CAS# DDRB_CAS# 115 116 DDRB_ODT0
CAS# ODT0 DDRB_ODT0 5
117 118
DDRB_MA13 119 VDD_15 VDD_16 120 DDRB_ODT1 +0.675VS
A13 ODT1 DDRB_ODT1 5
5 DDRB_CS1# DDRB_CS1# 121 122
123 S1# NC_2 124
125 VDD_17 VDD_18 126 CD45 CD46
TEST VREF_CA +V_SM_VREF_CNTB
127 128
DDRB_DQ32 129 VSS_27
DQ32
VSS_28
DQ36
130 DDRB_DQ36 Layout Note : Placed near

4.7U_0603_6.3V6-K

0.1U_0402_10V7-K
DDRB_DQ33 131 132 DDRB_DQ37 1 1
DDRB_DQS#4
133
135
DQ33
VSS_29
DQ37
VSS_30
134
136 DDRA_MB_DM4
JDIMM2.Pin203, 204
DQS4# DM4 DDRA_MB_DM4 5
DDRB_DQS4 137 138
139 DQS4 VSS_32 140 DDRB_DQ38 2 2
DDRB_DQ34 141 VSS_31 DQ38 142 DDRB_DQ39
B 1 1 B
DDRB_DQ35 143 DQ34 DQ39 144 CD28 CD29

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M
145 DQ35 VSS_34 146 DDRB_DQ44
DDRB_DQ40 147 VSS_33 DQ44 148 DDRB_DQ45
DDRB_DQ41 149 DQ40 DQ45 150 2 2
151 DQ41 VSS_35 152 DDRB_DQS#5
DDRA_MB_DM5 153 VSS_36 DQS5# 154 DDRB_DQS5
5 DDRA_MB_DM5 DM5 DQS5
155 156
DDRB_DQ42 157 VSS_37 VSS_38 158 DDRB_DQ46
DDRB_DQ43 159 DQ42 DQ46 160 DDRB_DQ47
161 DQ43 DQ47 162
DDRB_DQ48 163 VSS_39 VSS_40 164 DDRB_DQ52 close to JDIMM2.126
All VREF traces should have 20 mil trace width
DDRB_DQ49 165 DQ48 DQ52 166 DDRB_DQ53
167 DQ49 DQ53 168
DDRB_DQS#6 169 VSS_41 VSS_42 170 DDRA_MB_DM6 +1.35V_DDR_VDDIOSUS +1.35V_DDR_VDDIOSUS +V_SM_VREF_CNTB +1.35V_DDR_VDDIOSUS
DQS6# DM6 DDRA_MB_DM6 5
DDRB_DQS6 171 172
173 DQS6 VSS_44 174 DDRB_DQ54
VSS_43 DQ54

1
DDRB_DQ50 175 176 DDRB_DQ55 RFC3 RFC4
DDRB_DQ51 177 DQ50 DQ55 178 RD8 RD5
DQ51 VSS_46

2200P_0402_50V7-K
179 180 DDRB_DQ60 1K_0402_1% 1K_0402_1%
VSS_45 DQ60

47P_0402_50V8-J
DDRB_DQ56 181 182 DDRB_DQ61 2 1
DDRB_DQ57 183 DQ56 DQ61 184

RF_NS@
2

2
185 DQ57 VSS_48 186 DDRB_DQS#7
VSS_47 DQS7#

RF@
5 DDRA_MB_DM7 DDRA_MB_DM7 187 188 DDRB_DQS7 DDRB_EVENT#
189 DM7 DQS7 190 1 2
DDRB_DQ58 191 VSS_49 VSS_50 192 DDRB_DQ62
SPD setting (SA0, SA1) DQ58 DQ62

1
PU/PD by Channel A/B DDRB_DQ59 193 194 DDRB_DQ63
195 DQ59 DQ63 196 RD7
->Channel A 00 197 VSS_51 VSS_52 198 DDRB_EVENT# 1K_0402_1%
->Channel B 01 199 SA0 EVENT# 200 FCH_SMB_DA0
DDRB_EVENT# 5
For RF
VDDSPD SDA FCH_SMB_DA0 10,14
1 RD4 2 201 202 FCH_SMB_CK0
+3VS FCH_SMB_CK0 10,14

2
10K_0402_5% 203 SA1 SCL 204
VTT_1 VTT_2 +0.675VS
1 2
205
GND1 GND2
206 [email protected]
CD26 CD27 207 208
A
2.2U_0402_6.3V6-M BOSS1 BOSS2 A
0.1U_0402_10V7-K
@ 2 1
LCN_DAN06-K4406-0103
ME@

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 DDR3L SO-DIMMB/2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 11 of 65
5 4 3 2 1
 1 2 3 4 5

CH82
1 2
100P_0402_50V8-J +3VALW
RH20 @ CH15
PLT_RST# 1 2 EC_A_RST# 1 2 UH3A
100P_0402_50V8-J CLK_PCI_EC RH99 1 @ 2 10K_0402_5%
0_0402_5% BOLTON-M3 @
Part 1 of 5
PLT_RST# RH1 1 2 22_0402_5% PLT_RST_R# AE2 PCIE_RST# PCICLK0 AF3 PCICLK0_R RH19 2 1 22_0402_5%
14,17,33,36,37 PLT_RST# PCICLK0 33 +3VS
EC_A_RST# RH2 1 2 22_0402_5% A_RST# AD5 A_RST# PCICLK1/GPO36 AF1 PCICLK1
38 EC_A_RST# AF5
PCICLK2/GPO37
UMI_CRX_FTX_P0 CH1 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_P0_C AE30 UMI_TX0P PCICLK3/GPO38 AG2 PCICLK3
4 UMI_CRX_FTX_P0
UMI_CRX_FTX_N0 CH2 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_N0_C AE32 AF6 PCICLK4 PCICLK1 RH100 1 2 10K_0402_5%
Force PCIe on Gen 2

PCI CLKS
UMI_TX0N PCICLK4/14M_OSC/GPO39
4 UMI_CRX_FTX_N0
UMI_CRX_FTX_P1 CH3 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_P1_C AD33 UMI_TX1P
4 UMI_CRX_FTX_P1
UMI_CRX_FTX_N1 CH4 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_N1_C AD31 UMI_TX1N PCIRST#
AB5 PCICLK3 RH101 1 @ 2 10K_0402_5%
4 UMI_CRX_FTX_N1
UMI_CRX_FTX_P2 CH5 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_P2_C AD28 UMI_TX2P
4 UMI_CRX_FTX_P2
UMI_CRX_FTX_N2 CH6 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_N2_C AD29 UMI_TX2N AD0/GPIO0 AJ3 PCICLK4 RH102 1 @ 2 10K_0402_5%
4 UMI_CRX_FTX_N2
A UMI_CRX_FTX_P3 CH7 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_P3_C AC30 UMI_TX3P AD1/GPIO1 AL5 A
4 UMI_CRX_FTX_P3
UMI_CRX_FTX_N3 CH8 1 2 0.1U_0402_10V7-K UMI_CRX_FTX_N3_C AC32 UMI_TX3N AD2/GPIO2 AG4 LPC_CLK1 RH103 1 @ 2 10K_0402_5%
4 UMI_CRX_FTX_N3
AD3/GPIO3 AL6
UMI_CTX_FRX_P0_C AB33 UMI_RX0P AD4/GPIO4 AH3
4 UMI_CTX_FRX_P0_C
UMI_CTX_FRX_N0_C AB31 UMI_RX0N AD5/GPIO5 AJ5
4 UMI_CTX_FRX_N0_C
UMI_CTX_FRX_P1_C AB28 UMI_RX1P AD6/GPIO6
AL1
4 UMI_CTX_FRX_P1_C
UMI_CTX_FRX_N1_C AB29 UMI_RX1N AD7/GPIO7 AN5
4 UMI_CTX_FRX_N1_C
UMI_CTX_FRX_P2_C Y33 UMI_RX2P AD8/GPIO8 AN6 CLK_PCI_EC RH24 1 2 10K_0402_5%
4
4
UMI_CTX_FRX_P2_C
UMI_CTX_FRX_N2_C
UMI_CTX_FRX_N2_C Y31 UMI_RX2N AD9/GPIO9 AJ1
Disable Micro controller
UMI_CTX_FRX_P3_C Y28 UMI_RX3P AD10/GPIO10 AL8 PCICLK1 RH25 1 @ 2 10K_0402_5%
4 UMI_CTX_FRX_P3_C
UMI_CTX_FRX_N3_C Y29 UMI_RX3N AD11/GPIO11 AL3
4 UMI_CTX_FRX_N3_C
AD12/GPIO12 AM7 BTRF_OFF# PCICLK3 RH26 1 2 10K_0402_5%
BTRF_OFF# 33 Disable debug strap

PCI EXPRESS INTERFACES

RH4 1 2 590_0402_1% PCIE_CALRP AF29 PCIE_CALRP AD13/GPIO13 AJ6
BT_OFF# 33
RH3 1 2 2K_0402_1% PCIE_CALRN AF31 AD14/GPIO14 AK7 PCICLK4 RH27 1 2 10K_0402_5%
VDDAN_11_PCIE PCIE_CALRN
AD15/GPIO15 AN8
APUclock select
V33 GPP_TX0P AD16/GPIO16 AG9
V31 GPP_TX0N AD17/GPIO17 AM11
W30 GPP_TX1P AD18/GPIO18 AJ10
W32 GPP_TX1N AD19/GPIO19 AL12
AB26 GPP_TX2P AD20/GPIO20 AK11 +3VALW
AB27 GPP_TX2N AD21/GPIO21 AN12
AA24 GPP_TX3P AD22/GPIO22 AG12
AA23 AD23/GPIO23 AE12 TPH39 1 Test_Point_20MIL LPC_CLK1 RH28 1 2 10K_0402_5%
GPP_TX3N
AD24/GPIO24 AC12 TPH40 1 Test_Point_20MIL Set integrate clock mode
AA27 AD25/GPIO25 AE13 TPH42 1 Test_Point_20MIL

PCI INTERFACE
GPP_RX0P
AA26 GPP_RX0N AD26/GPIO26 AF13 +3VS
W27 GPP_RX1P AD27/GPIO27 AH13 TPH41 1 Test_Point_20MIL
V27 GPP_RX1N AD28/GPIO28 AH14 DGPU_PWROK
DGPU_PWROK 59
V26 GPP_RX2P AD29/GPIO29 AD15 FCH_BT_DISABLE# RH23 1 @ 2 10K_0402_5%
W26 GPP_RX2N AD30/GPIO30 AC15
W24 GPP_RX3P AD31/GPIO31 AE16 DGPU_HOLD_RST# RH144 1 2 10K_0402_5%
W23 GPP_RX3N CBE0# AN3
CBE1# AJ8
CBE2# AN10 +3VS
VDDAN_11_CLK RH5 1 2 2K_0402_1% F27 CLK_CALRN CBE3# AD12
B B
FRAME# AG10
DEVSEL# AK9 ODD_DA_INTH# RH29 1 2 10K_0402_5%

確確確確確確+3VS, +3VL or +3VALW

G30 PCIE_RCLKP IRDY# AL10
G28 PCIE_RCLKN TRDY# AF10
PAR AE10
DISP_CLKP RH6 1 2 0_0402_5% @ DISP_CLKP_R R26 DISP_CLKP STOP# AH1
7 DISP_CLKP +3VALW
DISP_CLKN RH7 1 2 0_0402_5% @ DISP_CLKN_R T26 DISP_CLKN PERR# AM9
7 DISP_CLKN
SERR# AH8
H33 DISP2_CLKP REQ0# AG15
H31 DISP2_CLKN REQ1#/GPIO40 AG13 RTCCLK RH104 1 2 10K_0402_5%
REQ2#/CLK_REQ8#/GPIO41 AF15
APU_CLKP RH8 1 2 0_0402_5% @ APU_CLKP_R T24 APU_CLKP REQ3#/CLK_REQ5#/GPIO42 AM17
Set S5+ mode
7 APU_CLKP
APU_CLKN RH9 1 2 0_0402_5% @ APU_CLKN_R T23 APU_CLKN GNT0# AD16 RTCCLK RH30 1 2 2.2K_0402_5%
7 APU_CLKN
GNT1#/GPO44 AD13 DGPU_HOLD_RST#
DGPU_HOLD_RST# 17
@
GFX_CLKP RH10 1 2 0_0402_5% @ GFX_CLKP_R J30 SLT_GFX_CLKP GNT2#/SD_LED/GPO45 AD21 DGPU_PWREN_R RH90 1 2 0_0402_5% @
17 GFX_CLKP DGPU_PWREN 17,24,59
GFX_CLKN RH11 1 2 0_0402_5% @ GFX_CLKN_R K29 SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46 AK17 TPH2 1 Test_Point_20MIL Select S5+
17 GFX_CLKN disable pull up
CLKRUN# AD19
PCIE_LAN_CLK_P0 RH12 1 2 0_0402_5% @ PCIE_LAN_CLK_P0_R H27 GPP_CLK0P LOCK# AH9
Enable Pull down
36 PCIE_LAN_CLK_P0 PCIE_LAN_CLK_N0 RH13 1 2 0_0402_5% @ PCIE_LAN_CLK_N0_R H28 GPP_CLK0N
36 PCIE_LAN_CLK_N0
INTE#/GPIO32 AF18
PCIE_CARDREAD_CLK_P1 RH14 1 2 0_0402_5% @ PCIE_CARDREAD_CLK_P1_R J27 GPP_CLK1P INTF#/GPIO33 AE18
37 PCIE_CARDREAD_CLK_P1
PCIE_CARDREAD_CLK_N1 RH15 1 2 0_0402_5% @ PCIE_CARDREAD_CLK_N1_R K26 AC16 +3VS
37 PCIE_CARDREAD_CLK_N1 GPP_CLK1N INTG#/GPIO34
AD18 ODD_DA_INTH#
internal PU 8.2K
INTH#/GPIO35
ODD_DA_INTH# 31
PCIE_WLAN_CLK_P2 RH16 1 2 0_0402_5% @ PCIE_WLAN_CLK_P2_R F33 GPP_CLK2P @
33 PCIE_WLAN_CLK_P2
PCIE_WLAN_CLK_N2 RH17 1 2 0_0402_5% @ PCIE_WLAN_CLK_N2_R F31 GPP_CLK2N DGPU_PWREN_R RH35 1 2 10K_0402_5%
33 PCIE_WLAN_CLK_N2
E33 GPP_CLK3P
E31 GPP_CLK3N DGPU_PWREN_R RH145 1 2 1K_0402_1%
LPCCLK0 B25 LPC_CLK0 RH86 2 1 22_0402_5%
CLK_PCI_EC 38
M23 D25 LPC_CLK1 DGPU_PWROK RH146 1 2 100K_0402_5%

CLOCK GENERATOR
GPP_CLK4P LPCCLK1
M24 GPP_CLK4N LAD0 D27 LPC_AD0
LPC_AD0 38
LAD1 C28 LPC_AD1
LPC_AD1 38
M27 LAD2 A26 LPC_AD2
PCH Crystal GPP_CLK5P

LPC
LPC_AD2 38
M26 GPP_CLK5N LAD3 A29 LPC_AD3
LPC_AD3 38
C LFRAME# A31 LPC_FRAME# C
LPC_FRAME# 38
N25 GPP_CLK6P LDRQ0# B27
FCH_XTAL25_IN N26 GPP_CLK6N LDRQ1#/CLK_REQ6#/GPIO49 AE27 FCH_BT_DISABLE# FCH_XTAL32X1
SERIRQ/GPIO48 AE19 SERIRQ RH31
SERIRQ 38
FCH_XTAL25_OUT RH18 1 2 1M_0402_5% R23 GPP_CLK7P 1 2 FCH_XTAL32X2
R24 GPP_CLK7N
20M_0402_5%
YH1 N27 GPP_CLK8P DMA_ACTIVE# G25 ALLOW_STOP
ALLOW_STOP 7
R27 GPP_CLK8N PROCHOT#
E28 APU_PROCHOT# YH2
APU_PROCHOT# 7
1 4 E26 APU_PWROK 1 2

APU
APU_PG
OSC1 GND2 APU_PWROK 7,57
LDT_STP# G26
2 3 J26 14M_25M_48M_OSC APU_RST# F26 APU_RESET# 32.768KHZ_12.5PF_9H03200019
GND1 OSC2 APU_RESET# 7
SJ10000DM0J
1 1 1 Y_9H03200019_2P 1
25MHZ_10PF_7V25000014 32K_X1 G2 FCH_XTAL32X1
CH16 CH17 FCH_XTAL25_IN C31 25M_X1 CH19 CH20
10P_0402_50V8-J 10P_0402_50V8-J 32K_X2 G4 FCH_XTAL32X2 22P_0402_50V8-J 18P_0402_50V8-J
2 2 2 2
H7 FCH_S5
S5_CORE_EN FCH_S5 38
FCH_XTAL25_OUT C33 25M_X2 RTCCLK F1 RTCCLK
S5 PLUS

INTRUDER_ALERT# F3
E6
Change to 7V25000014 (TXC),. Cap 15pF*2 VDDBT_RTC_G

RTC CONN
218084401A1BOLTONM3_FCBGA656 Internal pull up 50K +RTCVCC +RTCBATT

D21 RH34 JRTC

RH21 1 2 1 2 1 2 1
2 1
1K_0402_1% RB751V-40_SOD323-2 1K_0402_1% 2
1

2
JCLR SCS00006S00 3
CH18 4 GND1
SHORT PADS GND2
1U_0402_10V6-K @

1
2 TE_2041180-2
D D
ME@

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 FCH PCIe/PCI/LPC/APU/S5+
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 12 of 65
1 2 3 4 5
 1 2 3 4 5

Table +3VS

Function SKU_ID PANEL_ID

* UMA 0

2
DIS RH94 RH96
* 1 10K_0402_5% 10K_0402_5%
DIS@ 15@
* 14" 0

1
A UH3B A

* 15" 1 SKU ID
BOLTON-M3 Part 2 of 5
SATA_FTX_DRX_P0 AK19 SATA_TX0P SD_CLK/SCLK_0/GPIO73 AL14 PANEL ID
31 SATA_FTX_DRX_P0 SATA_FTX_DRX_N0 AM19 AN14
SATA_TX0N SD_CMD/SLOAD_0/GPIO74
31 SATA_FTX_DRX_N0 AJ12 SKU ID
SD_CD#/GPIO75

2
31 SATA_FRX_DTX_N0 SATA_FRX_DTX_N0 AL20 SATA_RX0N SD_WP/GPIO76 AH12 PANEL ID
31 SATA_FRX_DTX_P0 SATA_FRX_DTX_P0 AN20 SATA_RX0P SD_DATA0/SDATI_0/GPIO77 AK13 CMOS_ON# RH95 RH97
CMOS_ON# 26
SD_DATA1/SDATO_0/GPIO78 AM13 10K_0402_5% 10K_0402_5%
SATA_FTX_DRX_P1 AN22 SATA_TX1P SD_DATA2/GPIO79 AH15 F4_LED# UMA@ 14@

SD CARD
31 SATA_FTX_DRX_P1 F4_LED# 39
SATA_FTX_DRX_N1 AL22 SATA_TX1N SD_DATA3/GPIO80 AJ14

1
31 SATA_FTX_DRX_N1

31 SATA_FRX_DTX_N1 SATA_FRX_DTX_N1 AH20 SATA_RX1N GBE_COL AC4

31 SATA_FRX_DTX_P1 SATA_FRX_DTX_P1 AJ20 SATA_RX1P GBE_CRS AD3
GBE_MDCK AD9
AJ22 SATA_TX2P GBE_MDIO W10
AH22 SATA_TX2N GBE_RXCLK AB8
GBE_RXD3 AH7
AM23 SATA_RX2N GBE_RXD2 AF7 SPI_DI_8MB
AK23 SATA_RX2P GBE_RXD1 AE7
GBE_RXD0 AD7 SPI_DO_8MB
AH24 SATA_TX3P GBE_RXCTL/RXDV AG8
AJ24 SATA_TX3N GBE_RXERR AD1 SPI_CLK_8MB

GBE LAN
GBE_TXCLK AB7
AN24 SATA_RX3N GBE_TXD3 AF9 SPI_CS1#_8MB
AL24 SATA_RX3P GBE_TXD2 AG6
GBE_TXD1 AE8
AL26 SATA_TX4P GBE_TXD0 AD8
AN26 SATA_TX4N GBE_TXCTL/TXEN AB9 RH125 1 2 0_0402_5% @
38 EC_SPI_FMISO
GBE_PHY_PD AC2
AJ26 SATA_RX4N GBE_PHY_RST# AA7 RH126 1 2 0_0402_5% @
38 EC_SPI_FMOSI
AH26 SATA_RX4P GBE_PHY_INTR W9
RH127 1 2 0_0402_5% @
38 EC_SPI_FSCK
AN29 SATA_TX5P
B B
AL28 SATA_TX5N SPI_DI/GPIO164 V6 SPI_DI_8MB RH128 1 2 0_0402_5% @
38 EC_SPI_FSCE#
SPI_DO/GPIO163 V5 SPI_DO_8MB
AK27 SATA_RX5N SPI_CLK/GPIO162 V3 SPI_CLK_8MB
AM27 SATA_RX5P SPI_CS1#/GPIO165 T6 SPI_CS1#_8MB

SERIAL ATA
ROM_RST#/SPI_WP#/GPIO161 V1 SPI_WP#

SPI ROM
AL29 NC6
AN31 NC7
VGA_RED L30 FCH_CRT_R
FCH_CRT_R 28
AL31 NC8 RH131 1 2 150_0402_1%
AL33 NC9 VGA_GREEN L32 FCH_CRT_G
FCH_CRT_G 28
RH132 1 2 150_0402_1%
AH33 NC10 VGA_BLUE
M29 FCH_CRT_B
FCH_CRT_B 28
AH31 NC11 RH133 1 2 150_0402_1%

AJ33 NC12 VGA_HSYNC/GPO68 M28 FCH_CRT_HSYNC

VDDAN_11_SATA FCH_CRT_HSYNC 28
AJ31 NC13 VGA_VSYNC/GPO69 N30 FCH_CRT_VSYNC
FCH_CRT_VSYNC 28
VGA DAC
VGA_DDC_SDA/GPO70 M33 FCH_CRT_DDC_DAT
FCH_CRT_DDC_DAT 28
RH32 1 2 1K_0402_1% VGA_DDC_SCL/GPO71 N32 FCH_CRT_DDC_CLK
FCH_CRT_DDC_CLK 28
AF28 SATA_CALRP
RH33 1 2 931_0402_1% AF27 SATA_CALRN VGA_DAC_RSET K31 RH134 1 2 715_0402_1%
+3V_SPI
AUX_VGA_CH_P V28 CH10 1 2 0.1U_0402_10V7-K APU_VGA_AUX
APU_VGA_AUX 7 +3VALW +3V_SPI
RH108 1 2 10K_0402_5% GPIO67 AD22 SATA_ACT#/GPIO67 AUX_VGA_CH_N V29 CH11 1 2 0.1U_0402_10V7-K APU_VGA_AUX# RPH1
APU_VGA_AUX# 7
SPI_CS1#_8MB 1 8
U28 RH135 1 2 100_0402_1% SPI_WP# 2 7
AUXCAL VDDAN_11_ML
AF21 SATA_X1 3 6 RH76 1 2 0_0402_5% @
ML_VGA_L0P T31 APU_VGA_TX0+_C SPI_HOLD#_8MB 4 5
APU_VGA_TX0+_C 7
ML_VGA_L0N T33 APU_VGA_TX0-_C
APU_VGA_TX0-_C 7
ML_VGA_L1P T29 APU_VGA_TX1+_C 10K_0804_8P4R_5%
APU_VGA_TX1+_C 7
ML_VGA_L1N T28 APU_VGA_TX1-_C
APU_VGA_TX1-_C 7
ML_VGA_L2P R32 APU_VGA_TX2+_C
APU_VGA_TX2+_C 7 +3V_SPI
AG21 R30 APU_VGA_TX2-_C
VGA MAINLINK

SATA_X2 ML_VGA_L2N
APU_VGA_TX2-_C 7
ML_VGA_L3P P29 APU_VGA_TX3+_C
APU_VGA_TX3+_C 7
C ML_VGA_L3N P28 APU_VGA_TX3-_C UH1 C
APU_VGA_TX3-_C 7
SPI_CS1#_8MB 1 8
CS# VCC
ML_VGA_HPD/GPIO229 C29 ML_VGA_HPD
SPI_DI_8MB 2 7 SPI_HOLD#_8MB
LANMODE_STATUS 36 DO HOLD# SPI_HOLD#_8MB 14
AH16 FANOUT0/GPIO52 VIN0/GPIO175 N2 RH112 2 @ 1 10K_0402_5%
AM15 FANOUT1/GPIO53 VIN1/GPIO176 M3 GPIO176 RH113 2 @ 1 10K_0402_5% SPI_WP# 3 6 SPI_CLK_8MB 2
AJ16 L2 GPIO177 RH114 2 @ 1 10K_0402_5% WP# CLK
FANOUT2/GPIO54 VIN2/SDATI_1/GPIO177
HW MONITOR VIN3/SDATO_1/GPIO178 N4 GPIO178 RH115 2 @ 1 10K_0402_5% 4 5 SPI_DO_8MB CH21
AK15 P1 GPIO179 RH116 2 @ 1 10K_0402_5% GND DI 0.1U_0402_10V7-K
FANIN0/GPIO56 VIN4/SLOAD_1/GPIO179
AN16 P3 GPIO180 RH117 2 @ 1 10K_0402_5% 1
FANIN1/GPIO57 VIN5/SCLK_1/GPIO180
AL16 FANIN2/GPIO58 VIN6/GBE_STAT3/GPIO181 M1 GPIO181 RH118 2 @ 1 10K_0402_5% W25Q64FVSSIG_SO8
VIN7/GBE_LED3/GPIO182 M5 GPIO182 RH119 2 @ 1 10K_0402_5% SA000039A00

ODD_EN K6 TEMPIN0/GPIO171 NC1 AG16

31 ODD_EN RH109 2 @ 1 10K_0402_5% GPIO172 K5 AH10
TEMPIN1/GPIO172 NC2
RH110 2 @ 1 10K_0402_5% GPIO173 K3 TEMPIN2/GPIO173 NC3 A28
RH111 2 @ 1 10K_0402_5% GPIO174 M6 TEMPIN3/TALERT#/GPIO174 NC4 G27 +3VS
NC5 L4
+3VALW

218084401A1BOLTONM3_FCBGA656

1
RH138 RH140
10K_0402_5% 1K_0402_1%

2
G
2

2
ML_VGA_HPD 1 3 VGA_HPD_R
VGA_HPD_R 7

S
QH4
2N7002KW_SOT323-3
SB00000YY00
D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 FCH SATA/GBE/SPI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 13 of 65
1 2 3 4 5
 1 2 3 4 5

+3VALW
RH75 @
1 2 GPU_WAKE#_R
18 GPU_WAKE#
0_0402_5%

2
+3VS
RH87
10K_0402_5% @
RH50 1 @ 2 2.2K_0402_5% FCH_SMB0CLK
@ UH3D

1
RH51 1 @ 2 2.2K_0402_5% FCH_SMB0DATA 36,38 RH92 1 2 0_0402_5% RH52 @ +3VS
LAN_WAKE#
AB6 PCIE_RST2#/GEVENT4# USBCLK/14M_25M_48M_OSC G8 +3VS 1 2 USROM3
RH123 1 2 10K_0402_5% WD_PWRGD GPU_WAKE#_R R2 RI#/GEVENT22# 1 8

USB MISC
W7 B9 RH45 1 2 11.8K_0402_1% 10K_0402_5% 2 NC_1 VCC 7
SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
NC_2 WP 1
RH91 1 2 0_0402_5% @ PM_SLP_S3#_R T3 SLP_S3# 12,17,33,36,37 PLT_RST# PLT_RST# 3 6 FCH_SMB_CK0
38 PM_SLP_S3# RH98 1 2 0_0402_5% @ PM_SLP_S5#_R W2 H1 4 PROT# SCL 5 FCH_SMB_DA0 CH22
A SLP_S5# USB_FSD1P/GPIO186 A
38 PM_SLP_S5# PBTN_OUT# J4 H3 GND SDA 0.1U_0402_10V7-K
PWR_BTN# USB_FSD1N
38 PBTN_OUT# BOLTON-M3 2
RH22 1 2 0_0402_5% @ FCH_PWROK_R N7 PCA24S08AD_SO8

USB 1.1
PWR_GOOD
38 FCH_PWROK
USB_FSD0P/GPIO185 H6 SA00004MK00/SA00004ML00
+3VALW Test_Point_20MIL 1 TPH3 T9 TEST0
Part 4 of 5
USB_FSD0N H5
Test_Point_20MIL 1 TPH4 T10 TEST1/TMS
Test_Point_20MIL 1 TPH5 V9 H10 USB20_P13
GATEA20 AE22
TEST2
GA20IN/GEVENT0#
USB_HSD13P
USB_HSD13N G10 USB20_N13
USB20_P13 32 Docking port

ACPI / WAKE UP EVENTS

38 GATEA20 USB20_N13 32
RH37 1 @ 2 10K_0402_5% EC_WAKE# KBRST# AG19 KBRST#/GEVENT1#
38 KBRST#
EC_SCI# R9 K10 USB20_P12
RH38 1 @ 2 10K_0402_5% WD_PWRGD
38 EC_SCI#
C26
PME#/GEVENT3#
LPC_SMI#/GEVENT23#
USB_HSD12P
USB_HSD12N J12 USB20_N12
USB20_P12 30 External port
USB20_N12 30
DOCK_DETECT# T5 LPC_PD#/GEVENT5#
32 DOCK_DETECT#
RH39 1 @ 2 2.2K_0402_5% FCH_SMB1CLK U4 SYS_RESET#/GEVENT19# USB_HSD11P G12 TPH43 1 Test_Point_20MIL
EC_WAKE# K1 WAKE#/GEVENT8# USB_HSD11N F12
18,38 EC_WAKE#
RH40 1 @ 2 2.2K_0402_5% FCH_SMB1DATA V7 IR_RX1/GEVENT20# FCH_SMB0CLK RH129 1 2 0_0402_5% @ FCH_SMB_CK0
H_THERMTRIP# R10 K12 USB20_P10
RH41 1 @ 2 10K_0402_5% FCH_SMB2CLK
7,18 H_THERMTRIP#
WD_PWRGD AF19
THRMTRIP#/SMBALERT#/GEVENT2#
WD_PWRGD
USB_HSD10P
USB_HSD10N K13 USB20_N10
USB20_P10 30 USB charger port (15) FCH_SMB0DATA RH130 1 2 0_0402_5% @ FCH_SMB_DA0
USB20_N10 30
RH42 1 @ 2 10K_0402_5% FCH_SMB2DATA RH122 1 @ 2 RSMRST# U2 RSMRST# USB_HSD9P B11 TPH28 1 Test_Point_20MIL
38 EC_RSMRST#
0_0402_5% USB_HSD9N D11
RH124 1 2 10K_0402_5% AC_PRESENT @ AG24
CH9 1 2 0.1U_0402_10V7-K AE24
CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD8P E10 TPH29 1 Test_Point_20MIL DIMM1, DIMM2, Security EEPROM
AE26 SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD8N F10
LAN_CLKREQ# AF22 CLK_REQ0#/SATA_IS3#/GPIO60
+3VS +3VS
36 LAN_CLKREQ#
AH17 SATA_IS4#/FANOUT3/GPIO55 USB_HSD7P C10
AG18 SATA_IS5#/FANIN3/GPIO59 USB_HSD7N A10 RH55 1 @ 2 2.2K_0402_5%
+3VALW FCH_SPKR AF24 SPKR/GPIO66
35 FCH_SPKR

2
USB 2.0
FCH_SMB0CLK AD26 H9 USB20_P6
WLAN

G
SCL0/GPIO43 USB_HSD6P
USB20_P6 33
RPH2 FCH_SMB0DATA AD25 SDA0/GPIO47 USB_HSD6N G9 USB20_N6 RH56 1 @ 2 2.2K_0402_5%
USB20_N6 33
1 8 FCH_SMB1CLK T7 SCL1/GPIO227
2 7 USB_OC2# FCH_SMB1DATA R7 A8 USB20_P5
3 6 USB_OC1# CLKREQ_WLAN# AG25
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
USB_HSD5P
USB_HSD5N C8 USB20_N5
USB20_P5 26 CMOS FCH_SMB0CLK 6 1 FCH_SMB_CK0

S
33 CLKREQ_WLAN# USB20_N5 26 FCH_SMB_CK0 10,11
4 5 USB_OC0# CARD_CLKREQ# AG22

D
CLK_REQ1#/FANOUT4/GPIO61

GPIO
37 CARD_CLKREQ#

5
J2 F8 TPH30 1 Test_Point_20MIL QH3A

G
IR_LED#/LLB#/GPIO184 USB_HSD4P
10K_0804_8P4R_5% AG26 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD4N E8 2N7002KDWH_SOT363-6
B B
Test_Point_20MIL 1 TPH34 V8 DDR3_RST#/GEVENT7#/VGA_PD sb00000YR00
W8 GBE_LED0/GPIO183 USB_HSD3P C6 TPH31 1 Test_Point_20MIL @
SPI_HOLD#_8MB Y6 SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD3N A6 FCH_SMB0DATA 3 4 FCH_SMB_DA0

S
13 SPI_HOLD#_8MB FCH_SMB_DA0 10,11
V10

D
GBE_LED2/GEVENT10#
AA8 GBE_STAT0/GEVENT11# USB_HSD2P C5 TPH32 1 Test_Point_20MIL QH3B
GPU_CLKREQ AF25 CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD2N A5 2N7002KDWH_SOT363-6
17 GPU_CLKREQ
sb00000YR00
USB_HSD1P C1 TPH33 1 Test_Point_20MIL @
RH44 1 2 0_0402_5% @ FN_LED#_R M7 BLINK/USB_OC7#/GEVENT18# USB_HSD1N C3
39 FN_LED#
FCH_ODD_DA R8 USB_OC6#/IR_TX1/GEVENT6#
31 FCH_ODD_DA
Test_Point_20MIL 1 TPH46 T1 E1 USB20_P0
ZERO_ODD_DP# P6
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_HSD0P
USB_HSD0N E3 USB20_N0
USB20_P0 32 USB charger port (14)
31 ZERO_ODD_DP# USB20_N0 32 VDDAN_11_SSUSB_S
AC_PRESENT F5 USB_OC3#/AC_PRES/TDO/GEVENT15#
38 AC_PRESENT

USB OC
USB_OC2# P5 USB_OC2#/TCK/GEVENT14# USBSS_CALRP C16 USBSS_CALRP RH46 1 2 1K_0402_1%
32 USB_OC2#
USB_OC1# J7 USB_OC1#/TDI/GEVENT13# USBSS_CALRN A16 USBSS_CALRN RH47 1 2 1K_0402_1%
30 USB_OC1#
USB_OC0# T8 USB_OC0#/GEVENT12#/TRST
30 USB_OC0#
A14 USB30_TX_P3
RH67 1 @ 2
USB_SS_TX3P
USB_SS_TX3N C14 USB30_TX_N3
USB30_TX_P3 32 Docking port Click Pad
USB30_TX_N3 32 +3VS
10K_0402_5%
RH63 1 2 33_0402_5% AZ_BITCLK AB3 C12 USB30_RX_P3
34
34
FCH_AZ_BITCLK
FCH_AZ_SDOUT RH64 1 2 33_0402_5% AZ_SDOUT AB1
AZ_BITCLK
AZ_SDOUT
USB_SS_RX3P
USB_SS_RX3N A12 USB30_RX_N3
USB30_RX_P3 32 Docking port
USB30_RX_N3 32
FCH_AZ_SDIN0 AA2
34 FCH_AZ_SDIN0 AZ_SDIN0/GPIO167
2N7002KDWH

2
RH68 1 @ 2 AZ_SDIN1 Y5 D15 USB30_TX_P2
External port

G
AZ_SDIN1/GPIO168 USB_SS_TX2P
10K_0402_5% AZ_SDIN2 Y3 AZ_SDIN2/GPIO169 USB_SS_TX2N B15 USB30_TX_N2
USB30_TX_P2 30 Vth= min 1V, max 2.5V
USB30_TX_N2 30
AZ_SDIN3 Y1 AZ_SDIN3/GPIO170 ESD 2KV
RH65 1 2 33_0402_5% AZ_SYNC AD6 E14 USB30_RX_P2
HD AUDIO
34
34
FCH_AZ_SYNC
FCH_AZ_RST# RH66 1 2 33_0402_5% AZ_RST# AE4
AZ_SYNC
AZ_RST#
USB_SS_RX2P
USB_SS_RX2N F14 USB30_RX_N2
USB30_RX_P2 30 External port FCH_SMB1CLK 6 1 FCH_SMB1CLK_R

USB 3.0

S
USB30_RX_N2 30 FCH_SMB1CLK_R 42
@

D
5
F15 TPH44 1 Test_Point_20MIL QH1A

G
USB_SS_TX1P
Test_Point_20MIL 1 TPH6 K19 PS2_DAT/SDA4/GPIO187 USB_SS_TX1N G15 TPH45 1 Test_Point_20MIL 2N7002KDWH_SOT363-6
Test_Point_20MIL 1 TPH7 J19 PS2_CLK/CEC/SCL4/GPIO188 sb00000YR00
J21 SPI_CS2#/GBE_STAT2/GPIO166 USB_SS_RX1P H13
USB_SS_RX1N G13 FCH_SMB1DATA 3 4 FCH_SMB1DATA_R

S
FCH_SMB1DATA_R 42
@

D
Test_Point_20MIL 1 TPH35 D21 J16 USB30_TX_P0 QH1B
C
Test_Point_20MIL 1 TPH36 C20
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
USB_SS_TX0P
USB_SS_TX0N H16 USB30_TX_N0
USB30_TX_P0 30 USB charger port (15) 2N7002KDWH_SOT363-6
C
USB30_TX_N0 30
Test_Point_20MIL 1 TPH37 D23 PS2M_DAT/GPIO191 sb00000YR00
Test_Point_20MIL 1 TPH38 C22 J15 USB30_RX_P0
PS2M_CLK/GPIO192 USB_SS_RX0P
USB_SS_RX0N K15 USB30_RX_N0
USB30_RX_P0 30 USB charger port (15)
USB30_RX_N0 30
Test_Point_20MIL 1 TPH8 F21 KSO_0/GPIO209
Test_Point_20MIL 1 TPH9 E20 KSO_1/GPIO210 SCL2/GPIO193 H19 FCH_SMB2CLK
Test_Point_20MIL 1 TPH10 F20 KSO_2/GPIO211 SDA2/GPIO194 G19 FCH_SMB2DATA FCH_SMB1CLK @ RH136 2 1 0_0402_5% FCH_SMB1CLK_R
Test_Point_20MIL 1 TPH11 A22 SCL3_LV/GPIO195 G22 FCH_SCL3_LV
RH105 1 @ 2 10K_0402_5% AZ_SDIN1 Test_Point_20MIL 1 TPH12 E18
KSO_3/GPIO212
KSO_4/GPIO213 SDA3_LV/GPIO196 G21 FCH_SDA3_LV
FCH_SCL3_LV 7 APU SIC/SIV FCH_SMB1DATA @ RH139 2 1 0_0402_5% FCH_SMB1DATA_R
FCH_SDA3_LV 7
RH106 1 @ 2 10K_0402_5% AZ_SDIN2 Test_Point_20MIL 1 TPH13 A20 KSO_5/GPIO214 EC_PWM0/EC_TIMER0/GPIO197 E22
RH107 1 @ 2 10K_0402_5% AZ_SDIN3 Test_Point_20MIL 1 TPH14 J18 KSO_6/GPIO215 EMBEDDED CTRL EC_PWM1/EC_TIMER1/GPIO198 H22
Test_Point_20MIL 1 TPH15 H18 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199J22 ROM Strap RH48 1 2 2.2K_0402_5%
Test_Point_20MIL 1 TPH16 G18
KSO_7/GPIO216
KSO_8/GPIO217 EC_PWM3/EC_TIMER3/GPIO200 H21
Set on SPI ROM
Test_Point_20MIL 1 TPH17 B21 KSO_9/GPIO218
Test_Point_20MIL 1 TPH18 K18 KSO_10/GPIO219 KSI_0/GPIO201 K21 F1_LED#
F1_LED# 39
Test_Point_20MIL 1 TPH19 D19 KSO_11/GPIO220 KSI_1/GPIO202 K22
Test_Point_20MIL 1 TPH20 A18 KSO_12/GPIO221 KSI_2/GPIO203 F22
Test_Point_20MIL 1 TPH21 C18 F24
Test_Point_20MIL 1 TPH22 B19
KSO_13/GPIO222
KSO_14/XDB0/GPIO223
KSI_3/GPIO204
KSI_4/GPIO205 E24 No Device
+3VS RPH3 Test_Point_20MIL 1 TPH23 B17 KSO_15/XDB1/GPIO224 KSI_5/GPIO206 B23
1 8 FCH_SMB2CLK Test_Point_20MIL 1 TPH24 A24 KSO_16/XDB2/GPIO225 KSI_6/GPIO207 C24 +3VS +3VS
2 7 FCH_SMB2DATA Test_Point_20MIL 1 TPH25 D17 KSO_17/XDB3/GPIO226 KSI_7/GPIO208 F18
3 6 FCH_SMB0CLK RH53 1 @ 2 2.2K_0402_5%
4 5 FCH_SMB0DATA

2
G
2.2K_0804_8P4R_5% RH54 1 @ 2 2.2K_0402_5%
218084401A1BOLTONM3_FCBGA656

FCH_SMB2CLK 6 1 FCH_SMB_CK2

S
D
5
QH2A

G
2N7002KDWH_SOT363-6
sb00000YR00
D D
@
FCH_SMB2DATA 3 4 FCH_SMB_DA2

S
D
QH2B
2N7002KDWH_SOT363-6
sb00000YR00
@

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 FCH ACPI/USB/GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 14 of 65
1 2 3 4 5
 1 2 3 4 5

VDDCR_11 +1.1VS
22u *1, 1u*1 for circuit check list
1007mA RH61 1 2
+3VS UH3C

1U_0402_10V6-K

1U_0402_10V6-K
10U_0603_6.3V6-M

0.1U_0402_10V7-K

0.1U_0402_10V7-K
1 1 1 1 1 @ 0_0805_5%
BOLTON-M3 Part 3 of 5

RH78 1 2 VDDIO_33_PCIGP
102mA AB17 T14

CH40

CH41

CH42

CH43

CH44
VDDIO_33_PCIGP_1 VDDCR_11_1
AB18 VDDIO_33_PCIGP_2 VDDCR_11_2 T17

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
2 2 2 2 2
22U_0603_6.3V6-M
1 1 1 1 @ 0_0603_5% AE9 VDDIO_33_PCIGP_3 VDDCR_11_3 T20
AD10 U16
CH23

VDDIO_33_PCIGP_4 VDDCR_11_4

PCI/GPIO I/O
AG7 U18

CH24

CH25

CH26
VDDIO_33_PCIGP_5 VDDCR_11_5
AC13 V14

CORE S0
VDDIO_33_PCIGP_6 VDDCR_11_6
A
2 2 2 @2 AB12 V17 VDDAN_11_CLK +1.1VS A
VDDIO_33_PCIGP_7 VDDCR_11_7
AB13 VDDIO_33_PCIGP_8 VDDCR_11_8 V20
VDDPL_33_SYS AB14 VDDIO_33_PCIGP_9 VDDCR_11_9 Y17 +3VS VDDPL_33_SATA
AB16 VDDIO_33_PCIGP_10 RH141 1 2
340mA LH12

1U_0402_10V6-K

1U_0402_10V6-K

22U_0603_6.3V6-M
0.1U_0402_10V7-K

0.1U_0402_10V7-K
H24 VDDAN_11_CLK_1 H26 0_0603_5% 1 2
1 2 0_0402_5% @ V22
VDDPL_33_SYS 47mA 1 1 1 1 1 @
VDDPL_33_DACML RH57 VDDPL_33_DAC VDDPL_33_DAC 20mA VDDAN_11_CLK_2 J25

2.2U_0402_6.3V6-M
RH58 1 2 0_0402_5% @ VDDPL_33_ML U22 VDDAN_11_CLK_3 K24 BLM18PG221SN1D_2P

CH45

CH46

CH47

CH48

CH49
T22
VDDPL_33_ML 12mA 1
VDDAN_11_CLK_4 L22

CH72
30mA

CLKGEN I/O
VDDAN_33_DAC_R VDDAN_33_DAC
L18 2 2 2 2 2
VDDPL_33_SSUSB_S VDDPL_33_SSUSB_S 11mA VDDAN_11_CLK_5 M22
D7 VDDAN_11_CLK_6 N21
VDDPL_33_USB_S
AH29
VDDPL_33_USB_S 14mA 2
VDDPL_33_PCIE VDDPL_33_PCIE 11mA VDDAN_11_CLK_7 N22
AG28 VDDAN_11_CLK_8 P22
VDDAN_11_PCIE +1.1VS
VDDPL_33_SATA VDDPL_33_SATA 12mA
VDDPL_33_PCIE
RH60 1 2 0_0402_5% M31
1088mA
@ LDO_CAP VDDAN_11_PCIE_1 AB24 RH142 1 2 0_0805_5%
+1.1VS CH27 1 2 2.2U_0402_6.3V6-M VDDAN_11_PCIE_2 Y21 LH13

1U_0402_10V6-K

22U_0603_6.3V6-M
0.1U_0402_10V7-K
@ V21 VDDAN_11_PCIE_3 AE25 1 2
LH17 7mA VDDPL_11_DAC 1 1 1 @
VDDPL_11_DAC 226mA VDDAN_11_PCIE_4 AD24

2.2U_0402_6.3V6-M
1 2 RH137 1 2 Y22 VDDAN_11_PCIE_5 AB23 BLM18PG221SN1D_2P

CH50

CH51

CH52
VDDAN_11_ML_1 1
BLM18BB470SN1D_2P~D V23 VDDAN_11_PCIE_6 AA22

CH73
VDDAN_11_ML_2
2 2 2

MAIN LINK
CH14

0.1U_0402_10V7-K

CH13

4.7U_0603_6.3V6-K

CH12

0.1U_0402_10V7-K
@ 0_0603_5% 2 1 2 V24 VDDAN_11_ML_3 VDDAN_11_PCIE_7 AF26
V25 VDDAN_11_PCIE_8 AG27

PCI EXPRESS
VDDAN_11_ML_4
2
VDDAN_11_SATA +1.1VS
VDDAN_11_ML @ 1 2 1 AB10 VDDIO_33_GBE_S VDDAN_11_SATA_1 AA21
VDDAN_11_SATA_4 Y20
VDDPL_33_SYS
1337mA
VDDAN_11_SATA_2 AB21 RH143 1 2 0_0805_5%
VDDAN_11_SATA_3 AB22 LH14

1U_0402_10V6-K

1U_0402_10V6-K

0.1U_0402_10V7-K

22U_0603_6.3V6-M
SERIAL ATA
AB11 VDDCR_11_GBE_S_1 VDDAN_11_SATA_5 AC22 1 1 1 1 @ 1 2
AA11 VDDAN_11_SATA_6 AC21

CH56
VDDCR_11_GBE_S_2

0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
GBE LAN
VDDAN_11_SATA_7 AA20 BLM18PG221SN1D_2P

CH53

CH54

CH55
1 1
VDDAN_11_SATA_8 AA18

CH74
AA9 2 2 2 2
VDDAN_11_SATA_9 AB20

CH75
VDDIO_GBE_S_1
AA10 VDDIO_GBE_S_2 VDDAN_11_SATA_10 AC19
B 2 2 B
+3VALW

+3VALW VDDAN_33_USB_S
59mA VDDIO_33_S RH79 1 2 +3VALW
LH1 470mA

1U_0402_10V6-K

1U_0402_10V6-K
2.2U_0402_6.3V6-M
1 2 G7 VDDAN_33_USB_S_1 VDDIO_33_S_1 N18 1 1 1 @ 0_0603_5% LH7
H8 L19 1 2

CH57
VDDAN_33_USB_S_2 VDDIO_33_S_2
1U_0402_10V6-K

1U_0402_10V6-K
10U_0603_6.3V6-M

10U_0603_6.3V6-M

0.1U_0402_10V7-K

BLM18PG221SN1D_2P J8 M18

CH58

CH59
1 1 1 1 1 VDDAN_33_USB_S_3 VDDIO_33_S_3

2.2U_0402_6.3V6-M
K8 V12 @ BLM18PG221SN1D_2P
CH28

CH29

VDDAN_33_USB_S_4 VDDIO_33_S_4
2 2 2 1
K9 V13
CH30

CH31

CH32

CH67
VDDAN_33_USB_S_5 VDDIO_33_S_5

3.3V_S5 I/O
M9 VDDAN_33_USB_S_6 VDDIO_33_S_6 Y12
2 2 2 2 2 M10 Y13
VDDAN_33_USB_S_7 VDDIO_33_S_7
N9 W11 2
VDDAN_33_USB_S_8 VDDIO_33_S_8
N10 VDDAN_33_USB_S_9
+1.1VALW VDDCR_1.1V_USB

USB
M12
N12
VDDAN_33_USB_S_10
G24
5mA VDDXL_33_S +1.1VALW LH15
VDDAN_33_USB_S_11 VDDXL_33_S
M11 VDDAN_33_USB_S_12 1 2
140mA 272mA

10U_0603_6.3V6-M

0.1U_0402_10V7-K

0.1U_0402_10V7-K
VDDAN_11_USB_S U12 VDDAN_11_USB_S_1 VDDCR_11_S_1 N20 VDDCR_11_S RH80 1 2 BLM18PG221SN1D_2P 1 1 1
U13 VDDAN_11_USB_S_2 VDDCR_11_S_2 M20

1U_0402_10V6-K

1U_0402_10V6-K
0_0603_5%1

CH76

CH77

CH78
42mA T12
70mA @ 1
VDDCR_1.1V_USB VDDCR_11_USB_S_1 VDDPL_11_SYS_S J24 VDDPL_11_SYS_S
+1.1VALW VDDAN_11_SSUSB_S T13 2 2 2

CH65

CH66
VDDCR_11_USB_S_2
+1.1VALW
12mA 2 2
LH2 @ 282mA VDDAN_33_HWM_S M8
1 2 P16 VDDAN_11_SSUSB_S_1 LH8
M14 VDDAN_11_SSUSB_S_2 1 2
1U_0402_10V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

BLM18BB470SN1D_2P~D N14 AA4 VDDAN_33_HWM +3VALW

1 1 1 VDDAN_11_SSUSB_S_3 VDDIO_AZ_S
P13 VDDAN_11_SSUSB_S_4 BLM18PG221SN1D_2P
P14 LH9
CH33

CH34

CH35

VDDAN_11_SSUSB_S_5
2

1 2 VDDAN_11_USB_S
USB SS

1 1

0.1U_0402_10V7-K
2.2U_0402_6.3V6-M

2.2U_0402_6.3V6-M
RH62 2 2 2 N16

CH64
VDDCR_11_SSUSB_S_1 1

0.1U_0402_10V7-K
N17 BLM18PG221SN1D_2P LH16

CH60

CH63
0_0805_5% VDDCR_11_SSUSB_S_2 1
P17 1 2

CH61
C @ VDDCR_11_SSUSB_S_3 C
M17 2 2
VDDCR_11_SSUSB_S_4

0.1U_0402_10V7-K

0.1U_0402_10V7-K
1

2.2U_0402_6.3V6-M
2 BLM18PG221SN1D_2P
2 1 1 1
+1.1VALW VDDCR_11_SSUSB_S

CH79

CH80

CH81
LH3 424mA
1 2 2 2 @ 2
POWER
1U_0402_10V6-K
10U_0603_6.3V6-M

0.1U_0402_10V7-K

0.1U_0402_10V7-K

BLM18BB470SN1D_2P~D +3VALW
1 1 1 1
CH36

CH37

CH38

CH39

218084401A1BOLTONM3_FCBGA656
26mA VDDIO_AZ_S
RH81 1 2
2 2 2 2

2.2U_0402_6.3V6-M
@ 0_0603_5%1

CH62
2

+3VS VDDAN_33_DAC_R VDDPL_33_DACML VDDAN_33_USB_S VDDPL_33_USB_S +3VALW VDDPL_33_SSUSB_S

LH18 RH147 LH10 LH11

1 2 1 2 1 2 1 2
1U_0402_10V6-K
0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
2.2U_0402_6.3V6-M

2.2U_0402_6.3V6-M

2.2U_0402_6.3V6-M

2.2U_0402_6.3V6-M

BLM18PG221SN1D_2P 1 1 @ 0_0603_5% 1 1 BLM18PG221SN1D_2P 1 1 BLM18PG221SN1D_2P 1 1

CH86

CH84

CH68

CH70
CH85

CH83

CH69

CH71

D 2 2 2 @ 2 2 2 2 2 D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 FCH POWER/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 15 of 65
1 2 3 4 5
 1 2 3 4 5

UH3E
A A

BOLTON-M3
A3 VSS_1
Part 5 of 5
VSS_66 T25
A33 VSS_2 VSS_67 T27
B7 VSS_3 VSS_68 U6
B13 VSS_4 VSS_69 U14
D9 VSS_5 VSS_70 U17
D13 VSS_6 VSS_71 U20
E5 VSS_7 VSS_72 U21
E12 VSS_8 VSS_73 U30
E16 VSS_9 VSS_74 U32
E29 VSS_10 VSS_75 V11
F7 VSS_11 VSS_76 V16
F9 VSS_12 VSS_77 V18
F11 VSS_13 VSS_78 W4
F13 VSS_14 VSS_79 W6
F16 VSS_15 VSS_80 W25
F17 VSS_16 VSS_81 W28
F19 VSS_17 VSS_82 Y14
F23 VSS_18 VSS_83 Y16
F25 VSS_19 VSS_84 Y18
F29 VSS_20 VSS_85 AA6
G6 VSS_21 VSS_86 AA12
G16 VSS_22 VSS_87 AA13
G32 VSS_23 VSS_88 AA14
H12 VSS_24 VSS_89 AA16
H15 VSS_25 VSS_90 AA17
H29 VSS_26 VSS_91 AA25
J6 VSS_27 VSS_92 AA28
J9 VSS_28 VSS_93 AA30
J10 AA32

GROUND
VSS_29 VSS_94
J13 VSS_30 VSS_95 AB25
J28 VSS_31 VSS_96 AC6
J32 VSS_32 VSS_97 AC18
B B
K7 VSS_33 VSS_98 AC28
K16 VSS_34 VSS_99 AD27
K27 VSS_35 VSS_100 AE6
K28 VSS_36 VSS_101 AE15
L6 VSS_37 VSS_102 AE21
L12 VSS_38 VSS_103 AE28
L13 VSS_39 VSS_104 AF8
L15 VSS_40 VSS_105 AF12
L16 VSS_41 VSS_106 AF16
L21 VSS_42 VSS_107 AF33
M13 VSS_43 VSS_108 AG30
M16 VSS_44 VSS_109 AG32
M21 VSS_45 VSS_110 AH5
M25 VSS_46 VSS_111 AH11
N6 VSS_47 VSS_112 AH18
N11 VSS_48 VSS_113 AH19
N13 VSS_49 VSS_114 AH21
N23 VSS_50 VSS_115 AH23
N24 VSS_51 VSS_116 AH25
P12 VSS_52 VSS_117 AH27
P18 VSS_53 VSS_118 AJ18
P20 VSS_54 VSS_119 AJ28
P21 VSS_55 VSS_120 AJ29
P31 VSS_56 VSS_121 AK21
P33 VSS_57 VSS_122 AK25
R4 VSS_58 VSS_123 AL18
R6 VSS_59 VSS_124 AM21
R11 VSS_60 VSS_125 AM25
R25 VSS_61 VSS_126 AN1
R28 VSS_62 VSS_127 AN18
T11 VSS_63 VSS_128 AN28
T16 VSS_64 VSS_129 AN33
T18 VSS_65
VSSPL_DAC T21
C N8 VSSAN_HWM VSSAN_DAC L28 C
VSSANQ_DAC K33
K25 VSSXL VSSIO_DAC N28

H25 VSSPL_SYS

218084401A1BOLTONM3_FCBGA656

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 FCH GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 16 of 65
1 2 3 4 5
 1 2 3 4 5

UV3G

PCIE_CTX_C_GRX_N[0..7]
4 PCIE_CTX_C_GRX_N[0..7]
PCIE_CTX_C_GRX_P[0..7]
4 PCIE_CTX_C_GRX_P[0..7]
PCIE_CRX_GTX_N[0..7]
4 PCIE_CRX_GTX_N[0..7]
PCIE_CRX_GTX_P[0..7] PCIE_CTX_C_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0
4 PCIE_CRX_GTX_P[0..7] PCIE_RX0P PCIE_TX0P
PCIE_CTX_C_GRX_N0 AE31 AG31 PCIE_CRX_C_GTX_N0
PCIE_RX0N PCIE_TX0N
A A

PCIE_CTX_C_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1

PCIE_CTX_C_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PCIE_CRX_C_GTX_N1
PCIE_RX1N PCIE_TX1N

PCIE_CTX_C_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2

PCIE_CTX_C_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_CRX_C_GTX_N2
PCIE_RX2N PCIE_TX2N
DIS@
PCIE_CRX_GTX_P0 CV132 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_P0 PCIE_CTX_C_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3
PCIE_CRX_GTX_N0 CV133 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_N0 PCIE_CTX_C_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_CRX_C_GTX_N3
PCIE_CRX_GTX_P1 CV134 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_P1 PCIE_RX3N PCIE_TX3N
PCIE_CRX_GTX_N1 CV135 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_N1
PCIE_CRX_GTX_P2 CV136 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_P2 PCIE_CTX_C_GRX_P4 AB30 AC25 PCIE_CRX_C_GTX_P4
PCIE_CRX_GTX_N2 CV137 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_N2 PCIE_CTX_C_GRX_N4 AA31 PCIE_RX4P PCIE_TX4P AB25 PCIE_CRX_C_GTX_N4
PCIE_CRX_GTX_P3 CV138 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_P3 PCIE_RX4N PCIE_TX4N
PCIE_CRX_GTX_N3 CV139 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_N3
PCIE_CTX_C_GRX_P5 AA29 Y23 PCIE_CRX_C_GTX_P5
PCIE_CTX_C_GRX_N5 Y28 PCIE_RX5P PCIE_TX5P Y24 PCIE_CRX_C_GTX_N5
PCIE_CRX_GTX_P4 CV157 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_P4 PCIE_RX5N PCIE_TX5N
PCIE_CRX_GTX_N4 CV158 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_N4
PCIE_CRX_GTX_P5 CV159 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_P5 PCIE_CTX_C_GRX_P6 Y30 AB27 PCIE_CRX_C_GTX_P6
PCIE_CRX_GTX_N5 CV168 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_N5 PCIE_CTX_C_GRX_N6 W31 PCIE_RX6P PCIE_TX6P AB26 PCIE_CRX_C_GTX_N6
PCIE_CRX_GTX_P6 CV170 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_P6 PCIE_RX6N PCIE_TX6N
PCIE_CRX_GTX_N6 CV171 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_N6
PCIE_CRX_GTX_P7 CV173 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_P7 PCIE_CTX_C_GRX_P7 W29 Y27 PCIE_CRX_C_GTX_P7
PCIE_CRX_GTX_N7 CV174 1DIS@ 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_N7 PCIE_CTX_C_GRX_N7 V28 PCIE_RX7P PCIE_TX7P Y26 PCIE_CRX_C_GTX_N7
PCIE_RX7N PCIE_TX7N
+3VS_VGA
V30 W24
U31 NC_121 NC_137 W23
NC_122 NC_138

1
U29 V27 RV50
B +3VS +3VS_VGA T28 NC_123 NC_139 U26 10K_0402_5% B
NC_124 NC_140 @

2
PCI EXPRESS INTERFACE
T30 U24 RV49 @
R31 NC_125 NC_141 U23 2 1
NC_126 NC_142 12,24,59 DGPU_PWREN
1

CV140

0.1U_0402_10V7-K
RV43 10K_0402_5%
10K_0402_5% R29 T26 +3VS_VGA
NC_127 NC_143 1
5

UV4 @ P28 T27

NC_128 NC_144
VCC

1
@
PLT_RST# 1
12,14,33,36,37 PLT_RST# IN1 2
4 PLT_RST_VGA# P30 T24 RV52
OUT PLT_RST_VGA# 18,59 NC_129 NC_145
DGPU_HOLD_RST# 2 N31 T23 10K_0402_5%
GND

12 DGPU_HOLD_RST# IN2 NC_130 NC_146 QV7 @

2

2
@

2
MC74VHC1G08DFT2G_SC70-5 RV44 N29 P27
3

DIS@ M28 NC_131 NC_147 P26 1 3 CLK_REQ_GPU#

100K_0402_5% NC_132 NC_148 14 GPU_CLKREQ CLK_REQ_GPU# 18

CV141

0.1U_0402_10V7-K

S
DIS@
1
1

2
M30 P24 2N7002KW_SOT323-3
L31 NC_133 NC_149 P23 SB00000YY00 RV53
NC_134 NC_150

@
10K_0402_5%
2 1 @ 2 @
L29 M27

1
K30 NC_135 NC_151 N26 RV51 0_0402_5%
NC_136 NC_152

CLOCK
GFX_CLKP AK30
12 GFX_CLKP PCIE_REFCLKP
GFX_CLKN AK32 +0.95VS_VGA
12 GFX_CLKN PCIE_REFCLKN

CALIBRATION

C Y22 RV47 1 DIS@ 2 1.69K_0402_1% C

PCIE_CALR_TX
RV40 1 DIS@ 2 1K_0402_1% N10 AA22 RV48 1 DIS@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX

PLT_RST_VGA# AL27
PERSTB

2160856030-A0_FCBGA631
JET@

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet PCIE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 17 of 65
1 2 3 4 5
 5 4 3 2 1

UV3A
+3VS_VGA

Test_Point_20MIL 1 TPV17 N9 AF2

Test_Point_20MIL 1 TPV18 L9 DBG_DATA16 NC_13 AF4
Test_Point_20MIL 1 TPV19 AE9 DBG_DATA15 NC_14
1 Y11 DBG_DATA14 AG3 H_THERMTRIP# 7,14
Test_Point_20MIL TPV20
Test_Point_20MIL 1 TPV21 AE8 DBG_DATA13 NC_15 AG5
Test_Point_20MIL 1 TPV22 AD9 DBG_DATA12 NC_16 RV87 @
DBG_DATA11 NC_DPA

1
Test_Point_20MIL 1 TPV23 AC10 AH3 C
Test_Point_20MIL 1 TPV24 AD7 DBG_DATA10 NC_17 AH1 GPIO19_CTF RV86 1 @ 2 47K_0402_5% 1 2 2 MLMBT3904WT1G NPN SOT323-3
Test_Point_20MIL 1 TPV25 AC8 DBG_DATA9 NC_18 B QV3 @
D +1.8VS_VGA +1.8VS_VGA Test_Point_20MIL 1 TPV26 AC7 DBG_DATA8 AK3 2.2K_0402_5% E D

3
DBG_DATA7 NC_19

CV148

0.1U_0402_10V7-K
Test_Point_20MIL 1 TPV27 AB9 AK1 DV1 1
DBG_DATA6 NC_20

2
Test_Point_20MIL 1 TPV28 AB8 PLT_RST_VGA# 1 2 RV88

G
DBG_DATA5 DBG 17,59 PLT_RST_VGA#
QV2A Test_Point_20MIL 1 TPV29 AB7 AK5 100K_0402_5%
DBG_DATA4 NC_21

1
sb00000YR00 Test_Point_20MIL 1 TPV30 AB4 AM3 RB751V-40_SOD323-2
DBG_DATA3 NC_22 @ 2

@
RV54 RV55 Test_Point_20MIL 1 TPV31 AB2 SCS00006S00

1
SMBCLK 1 6 4.7K_0402_5% 4.7K_0402_5% Test_Point_20MIL 1 TPV32 Y8 DBG_DATA2 AK6 @
S

EC_SMB_CK3 7,29,38 DBG_DATA1 NC_23

D TOPAZ@ TOPAZ@ Test_Point_20MIL 1 TPV33 Y7
DBG_DATA0 NC_24
AM5
2N7002KDWH_SOT363-6 Test_Point_20MIL 1 TPV34 AL9 NC_DPB

2
DIS@ DBG_CNTL0 AJ7
Test_Point_20MIL 1 TPV1 U1 NC_25 AH6
NC_1 NC_26
5

Test_Point_20MIL 1 TPV2 U3
G

QV2B NC_153 AK8

sb00000YR00 AM26 NC_27 AL7
NC_R NC_28
SMBDAT 4 3
S

EC_SMB_DA3 7,29,38
D

W6
2N7002KDWH_SOT363-6 V6 NC_2 +1.8VS_VGA
DIS@ NC_3 V4
Pull high 2.2K to +3VS at EC SIDE AC6 NC_29 U5 +3VS_VGA
AC5 NC_4 NC_30
NC_5 +3VS_VGA

CV150

0.1U_0402_10V7-K
AA5 V2
AA6 NC_6 NC_31
NC_7 NC_DPC 1
Y4
NC_32

CV149

0.1U_0402_10V7-K
W5
NC_33

@
1 2
+3VS_VGA +3VS_VGA +3VS_VGA

1
Y2
NC_34

@
RV91 RV92
2

@
RV111 1 DIS@ 2 10K_0402_5% Y6 J8 10K_0402_5% 10K_0402_5% UV9
NC_8 NC_35 @ JET@

1
DV2

2
VGA_AC_BATT 1 2 GPIO5_AC_BATT RV70 RV71 1 8
38 VGA_AC_BATT VCC(A) VCC(B)
4.7K_0402_5% 4.7K_0402_5% @

@
RB751V-40_SOD323-2 DIS@ DIS@ GPIO15 RV89 1 2 0_0402_5% 2 7 RV96 1 2 33_0402_5% SVI2_SVD
1A 1B SVI2_SVD 18,59
SCS00006S00 I2C

@
DIS@ GPIO20 RV90 1 2 0_0402_5% 3 6 RV97 1 2 33_0402_5% SVI2_SVC
2A 2B SVI2_SVC 18,59
R1 @
R3 SCL AL25 5 4
SDA NC_G DIR GND

1
RV113 1 @ 2 GPIO5_AC_BATT
+3VS_VGA RV72 1 DIS@ 2 4.7K_0402_5% RV93 RV94
C 0_0402_5% AK26 10K_0402_5% 10K_0402_5% 74AVCH2T45GD_XSON8_3X2 C
+3VS_VGA RV73 1 DIS@ 2 4.7K_0402_5% U6
GENERAL PURPOSE I/O NC_AVSSN_1 JET@ @
GPIO_0 AJ25 +3VS_VGA
RV95

2
NC_AVSSN_2 AH24
SMBDAT U8 NC_B 1 2
SMBDATA
1

SMBCLK U7
SMBCLK

CV151

0.1U_0402_10V7-K

10U_0603_6.3V6-M
RV61 GPIO5_AC_BATT T9 AG25 10K_0402_5%
GPIO_5_AC_BATT NC_AVSSN_3

CV152

@
10K_0402_5% GPIO6 T8 1 1
TOPAZ@ T7 GPIO_6 NC_DAC1 AH26
Test_Point_20MIL 1 TPV3 GPIO8_ROMSO P10 NC_GPIO_7 NC_HSYNC
2

GPIO_8_ROMSO

@
RV62 TOPAZ@ Test_Point_20MIL 1 TPV4 GPIO9_ROMSI P4
GPIO_9_ROMSI 2 2 +1.8VS_VGA

@
RV114 1 @ 2 OCP_L 1 2 GPIO6 Test_Point_20MIL 1 TPV5 GPIO10_ROMSCK P2
38,59 GPU_VR_HOT# N6 GPIO_10_ROMSCK AD22
0_0402_5% 1K_0402_1% N5 NC_GPIO_11 NC_RSET
1 NC_GPIO_12
CV142 N3 AG24
0.1U_0402_10V7-K NC_GPIO_13 NC_AVDD AE22
TOPAZ@ SVI2_SVD RV150 1 2 0_0402_5% @ GPIO15 N1 NC_AVSSQ
2 M4 GPIO_15_PWRCNTL_0 AE23
GPIO_16 NC_VDD1DI

2
R6 AD23
RV74 1 @ 2 10K_0402_5% GPIO_17_THERMAL_INT NC_VSS1DI RV121 RV123 RV125
GPIO19_CTF M2 10K_0402_5% 10K_0402_5% 10K_0402_5%
SVI2_SVC RV151 1 2 0_0402_5% @ GPIO20 P8 GPIO_19_CTF AM12 +3VS_VGA @ @ @
P7 GPIO_20_PWRCNTL_1 CEC_1

1
Test_Point_20MIL 1 TPV6 GPIO22_ROMCSB N8 GPIO_21
AK10 GPIO_22_ROMCSB AK12 RV107 1 TOPAZ@ 2 0_0402_5% SVI2_SVD SVI2_SVD
AM10 GPIO_29 NC_SVI2_1 AL11 1 TOPAZ@ 2 SVI2_SVT SVI2_SVD 18,59
RV108 0_0402_5%
+3VS_VGA 1 2 N7 GPIO_30 NC_SVI2_2 AJ11 1 TOPAZ@ 2 SVI2_SVT 59
RV112 @ 0_0402_5% RV109 0_0402_5% SVI2_SVC SVI2_SVT
17 CLK_REQ_GPU# 1 2 10K_0402_5% CLKREQB NC_SVI2_3 SVI2_SVC 18,59
RV75 @

2
Test_Point_20MIL 1 TPV7 JTAG_TRSTB L6 SVI2_SVC
JTAG_TRSTB
1

Test_Point_20MIL 1 TPV8 JTAG_TDI L5 RV118 RV119 RV120

RV67 Test_Point_20MIL 1 TPV9 JTAG_TCK L3 JTAG_TDI 10K_0402_5% 10K_0402_5% 10K_0402_5%
JTAG_TCK

2
10K_0402_5% Test_Point_20MIL 1 TPV10 JTAG_TMS L1 AL13 @ @ @

MLPS&SVI2
JTAG_TMS NC_GENLK_CLK
1

@ Test_Point_20MIL 1 TPV11 JTAG_TDO K4 AJ13 RV122 RV124 RV126

1
RV63 RV64 RV65 RV66 K7 JTAG_TDO NC_GENLK_VSYNC 10K_0402_5% 10K_0402_5% 10K_0402_5%
2

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% +3VS_VGA AF24 TESTEN SVI2_SVD @ @ @

@ @ @ @ NC_9 AG13

1
RV76 1 @ 2 5.11K_0402_1% NC_SWAPLOCKA SVI2_SVT
2

AC19 PS_0
1 DIS@ 2 W8 PS_0 PS_0
JTAG_TRSTB RV77 1K_0402_1% SVI2_SVC
JTAG_TDI NC_GENERICB
JTAG_TCK W7 AH12
JTAG_TMS AD10 NC_GENERICD NC_SWAPLOCKB
B JTAG_TDO AJ9 NC_GENERICE_HPD4 AD19 PS_1 B
NC_10 PS_1 PS_1
AE17 PS_2 VID CODES
1 TPV12 1 2 0_0402_5% AB16 PS_2 PS_2
Test_Point_20MIL RV78 @
+3VS_VGA PX_EN AE20 PS_3
1 2 0_0402_5% AJ27 PS_3 PS_3 +1.8VS_VGA +1.8VS_VGA
RV79 @ SVC SVD Boot Voltage
@ NC_VSYNC
RV115 1 2 +3VS_VGA
0 0 1.1V

2
@ AC16
NC_DBG_VREFG
2

4.7K_0402_5% QV4 RV80 1 2 4.7K_0402_5% RV98 RV100

G

RV140 8.45K_0402_1% 10K_0402_5% 0 1 1.0V

1 2 1 3 DIS@ @
14,38 EC_WAKE#
TOPAZ@ 1 0 0.9V(Default)
D

NC_DDC/AUX

1
0_0402_5% RV106 1 2 4.7K_0402_5% PLL/CLOCK AE6 CV153 PS_0 CV154 PS_2
@ 2N7002KW_SOT323-3 NC_DDC1CLK AE5 1 1 0.8V
NC_DDC1DATA

0.1U_0402_10V7-K

0.1U_0402_10V7-K
SB00000YY00 Test_Point_20MIL 1 TPV13 AA1
14 GPU_WAKE# NC_11

1
@ AD2 1 1
TOPAZ@ NC_AUX1P AD4 RV99 RV101
RV68 DIS@ RV81 1 2 16.2K_0402_1% AA3 NC_AUX1N 2K_0402_1% 4.75K_0402_1%
NC_12

@
DIS@ DIS@
1 2 2 2

2
1M_0402_5% XTALIN AM28 AD13
XTALOUT AK28 XTALIN NC_AUX2P AD11
YV1 DIS@ XTALOUT NC_AUX2N
4 3 XTALIN RV82 1 @ 2 10K_0402_5% AC22
NC2 OSC2 RV83 1 @ 2 10K_0402_5% AB22 XO_IN
XTALOUT 1 2 XO_IN2
OSC1 NC1 AE16 +1.8VS_VGA +1.8VS_VGA
27MHZ_16PF_+-30PPM 7V27000011 NC_36 AD16
1 1 NC_37

1
CV143 CV144 THERMAL AC1
DIS@ 22P_0402_50V8-J 22P_0402_50V8-J T4 NC_DDCVGACLK AC3 RV102 RV104
2 2 T2 DPLUS NC_DDCVGADATA 10K_0402_5% 3.24K_0402_1%
+1.8VS_VGA DMINUS @ X76@
DIS@

2
FDO R5 CV155 PS_1 CV156 PS_3
CV145 AD17 GPIO28_FDO
TSVDD PS_3[3..1]

0.1U_0402_10V7-K

0.1U_0402_10V7-K
AC17
TSVSS 101 = Micron 2G

1
1 1
110 = Samsung 2G
1U_0402_10V6-K

1 AE19 RV103 RV105

TS_A 4.75K_0402_1% 5.62K_0402_1% 111 = Hynix 2G

@
A DIS@ X76@ A
2 2
DIS@

2160856030-A0_FCBGA631

2
2 JET@

JET@
RV84 1 2 FDO

10K_0402_5%

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 18 of 65
5 4 3 2 1
 1 2 3 4 5

+1.8VS_VGA
TPV14
Test_Point_32MIL CV26 CV27 CV28
UV3B

10U_0603_6.3V6-M

1U_0402_10V6-K

1U_0402_10V6-K
+1.5VS_VGA 1 1 1

1
AM30
MEM I/O PCIE_PVDD

PCIE

DIS@

DIS@

DIS@
A CV1 CV2 CV8 CV3 CV4 CV5 CV6 CV7 H13 AB23 A
H16 VDDR1_1 NC_38 AC23 2 2 2
VDDR1_2 NC_39
.01U_0402_16V7-K

0.1U_0402_10V7-K

10U_0603_6.3V6-M

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K
H19 AD24
J10 VDDR1_3 NC_40 AE24
1 1 1 1 1 1 1 1 VDDR1_4 NC_41
J23 AE25
J24 VDDR1_5 NC_42 AE26
VDDR1_6 NC_43
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
J9 AF25 +0.95VS_VGA
2 2 2 2 2 2 2 2 VDDR1_7 NC_44

@
K10 AG26
K23 VDDR1_8 NC_45
K24 VDDR1_9
K9 VDDR1_10 L23 CV29 CV30 CV31 CV32 CV33 CV34 CV35 CV36
L11 VDDR1_11 PCIE_VDDC_1 L24
VDDR1_12 PCIE_VDDC_2

10U_0603_6.3V6-M

10U_0603_6.3V6-M
L12 L25
VDDR1_13 PCIE_VDDC_3

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
L13 L26 1 1 1 1 1 1 1 1
L20 VDDR1_14 PCIE_VDDC_4 M22
L21 VDDR1_15 PCIE_VDDC_5 N22
VDDR1_16 PCIE_VDDC_6

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

@
L22 N23
VDDR1_17 PCIE_VDDC_7 N24 2 2 2 2 2 2 2 2
PCIE_VDDC_8 R22
+1.8VS_VGA PCIE_VDDC_9 T22
LEVEL PCIE_VDDC_10 U22
TRANSLATION PCIE_VDDC_11 V22 +VGA_CORE
CV9 AA20 PCIE_VDDC_12
AA21 VDD_CT_1
AB20 VDD_CT_2 AA15 CV37 CV38 CV39 CV40 CV41 CV42 CV43 CV44 CV45 CV46 CV47 CV48 CV49 CV50
VDD_CT_3 CORE VDDC_1
1U_0402_10V6-K

1 AB21 N15
VDD_CT_4 VDDC_2

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
N17
VDDC_3 R13
I/O VDDC_4 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DIS@

R16
2 AA17 VDDC_5 R18
VDDR3_1 VDDC_6

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

@
AA18 Y21
AB17 VDDR3_2 VDDC_7 T12 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AB18 VDDR3_3 VDDC_8 T15
VDDR3_4 VDDC_9 T17
V12 VDDC_10 T20
B
Y12 NC_VDDR4_1 VDDC_11 U13 B
+3VS_VGA U12 NC_VDDR4_2 VDDC_12 U16
NC_VDDR4_3 VDDC_13 U18 CV51 CV52 CV53 CV54 CV55 CV56 CV57 CV58
VDDC_14 V21
VDDC_15

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K
CV10 V15
VDDC_16 V17
VDDC_17 1 1 1 1 1 1 1 1
V20
VDDC_18
1U_0402_10V6-K

Y13

POWER
1 VDDC_19

DIS@

DIS@

DIS@

DIS@

@
Y16
VDDC_20 Y18 2 2 2 2 2 2 2 2
VDDC_21
DIS@

AA12
2 VDDC_22 M11
VDDC_23 N12
VDDC_24 U11
VDDC_25 AB13
NC_GENERICA U10
NC_GPIO_1 W9
PLL
NC_GENERICC Y9
NC_GPIO_14 W10
NC_GPIO_18 T10 +0.95VS_VGA
+1.8VS_VGA MPLL_PVDD NC_GPIO_2 AC14
NC_HPD1 AB12
LV3 NC_DIGON AB11 CV22
1 2 CV17 CV18 CV19
90mA L8 NC_VARY_BL AC11
MPLL_PVDD NC_DDC2CLK

1U_0402_10V6-K
AC13
NC_DDC2DATA Only available on TOPAZ, NC balls on JET
10U_0603_6.3V6-M

10U_0603_6.3V6-M

1U_0402_10V6-K

BLM18PG221SN1D_2P SPLL_PVDD 1
DIS@ 1 1 1
AC20 TOPAZ_VDDC_SEN
75mA NC_46

DIS@
H7 AD20 TOPAZ_VDDC_RTN
SPLL_PVDD NC_47 2
DIS@

DIS@

DIS@

2 2 2 SPLL_VDDC
R21
BIF_VDDC_1 U21
100mA H8 BIF_VDDC_2
SPLL_VDDC +VGA_CORE
C C
J7 ISOLATED
+1.8VS_VGA SPLL_PVSS
CORE I/O
M13 CV59 CV60 CV61 CV62 CV63 CV64 CV65
LV4 VDDCI_1 M15
VDDCI_2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

0.1U_0402_10V7-K

0.1U_0402_10V7-K
1 2 CV20 CV21 M16
VDDCI_3

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
M17 1 1 1 1 1 1 1
VDDCI_4
10U_0603_6.3V6-M

BLM18PG121SN1D_2P M18
VDDCI_5
1U_0402_10V6-K

DIS@ 1 1 M20
VDDCI_6
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
M21
VDDCI_7 N20 2 2 2 2 2 2 2
VDDCI_8
DIS@

DIS@

2 2 W1
NC_48 W3
NC_49

2160856030-A0_FCBGA631
+0.95VS_VGA JET@

LV5
1 2 CV24 CV25
FOR JET,PUT VIAS UNDER ASIC +VGA_CORE
0.1U_0402_10V7-K

BLM18PG121SN1D_2P
1U_0402_10V6-K

DIS@ 1 1
VDDC_SEN RV1 1 2 0_0402_5% @
59 VDDC_SEN
DIS@

DIS@

2 2 VDDC_RTN RV2 1 2 0_0402_5% @

59 VDDC_RTN

TOPAZ@
VDDC_SEN RV3 1 2 0_0402_5% TOPAZ_VDDC_SEN
D D
TOPAZ@
VDDC_RTN RV4 1 2 0_0402_5% TOPAZ_VDDC_RTN

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet Core Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 19 of 65
1 2 3 4 5
 5 4 3 2 1

UV3C UV3D UV3E

DP POWER NC/DP POWER

AG15 AE11 AL15 AA27 A3

AG16 NC_DP_VDDR_1 NC_50 AF11 NC_UPHYAB_TMDPA_TX0N AB24 GND_1 GND_65 A30
AK14
AF16 NC_DP_VDDR_2 NC_51 AE13 NC_UPHYAB_TMDPA_TX0P AB32 GND_2 GND_66 AA13
AG17 NC_DP_VDDR_3 NC_52 AF13 AC24 GND_3 GND_67 AA16
D AH16 D
+1.8VS_VGA AG18 NC_DP_VDDR_4 NC_53 AG8 NC_UPHYAB_TMDPA_TX1N AC26 GND_4 GND_68 AB10
AJ15
AG19 NC_DP_VDDR_5 NC_54 AG10 NC_UPHYAB_TMDPA_TX1P AC27 GND_5 GND_69 AB15
CV66 CV67 AF14 NC_DP_VDDR_6 NC_55 AD25 GND_6 GND_70 AB6
AL17
DP_VDDR NC_UPHYAB_TMDPA_TX2N AD32 GND_7 GND_71 AC9
AK16
NC_UPHYAB_TMDPA_TX2P GND_8 GND_72
10U_0603_6.3V6-M
AE27 AD6
GND_9 GND_73

1U_0402_10V6-K
1 1 AH18 AF32 AD8
NC_UPHYAB_TMDPA_TX3N AG27 GND_10 GND_74 AE7
AJ17
AG20 AF6 NC_UPHYAB_TMDPA_TX3P AH32 GND_11 GND_75 AG12
NC_DP_VDDC_1 NC_56 GND_12 GND_76
DIS@

DIS@

AG21 AF7 AL19 K28 AH10

2 2 AF22 NC_DP_VDDC_2 NC_57 AF8 NC_TXOUT_L3P K32 GND_13 GND_77 AH28
AK18
AG22 NC_DP_VDDC_3 NC_58 AF9 NC_TXOUT_L3N L27 GND_14 GND_78 B10
AD14 NC_DP_VDDC_4 NC_59 M32 GND_15 GND_79 B12
DP_VDDC NC_TMDP N25 GND_16 GND_80 B14
N27 GND_17 GND_81 B16
P25 GND_18 GND_82 B18
AH20
AG14 AE1 NC_UPHYAB_TMDPB_TX0N P32 GND_19 GND_83 B20
AJ19
+0.95VS_VGA AH14 NC_DP_VSSR_1 NC_60 AE3 NC_UPHYAB_TMDPB_TX0P R27 GND_20 GND_84 B22
AM14 NC_DP_VSSR_2 NC_61 AG1 T25 GND_21 GND_85 B24
AL21
CV70 CV71 AM16 NC_DP_VSSR_3 NC_62 AG6 NC_UPHYAB_TMDPB_TX1N T32 GND_22 GND_86 B26
AK20
AM18 NC_DP_VSSR_4 NC_63 AH5 NC_UPHYAB_TMDPB_TX1P U25 GND_23 GND_87 B6
NC_DP_VSSR_5 NC_64 GND_24 GND_88
0.1U_0402_10V7-K

AF23 AF10 AH22 U27 B8

NC_DP_VSSR_6 NC_65 NC_UPHYAB_TMDPB_TX2N GND_25 GND_89
1U_0402_10V6-K

1 1 AG23 AG9 AJ21 V32 C1

AM20 NC_DP_VSSR_7 NC_66 AH8 NC_UPHYAB_TMDPB_TX2P W25 GND_26 GND_90 C32
AM22 NC_DP_VSSR_8 NC_67 AM6 W26 GND_27 GND_91 E28
AL23
NC_DP_VSSR_9 NC_68 NC_UPHYAB_TMDPB_TX3N GND_28 GND_92
DIS@

DIS@

AM24 AM8 AK22 W27 F10

2 2 AF19 NC_DP_VSSR_10 NC_69 AG7 NC_UPHYAB_TMDPB_TX3P Y25 GND_29 GND_93 F12
AF20 NC_DP_VSSR_11 NC_70 AG11 Y32 GND_30 GND_94 F14
AK24
AE14 NC_DP_VSSR_12 NC_71 NC_TXOUT_U3P GND_31 GND_95 F16
AJ23
DP_VSSR NC_TXOUT_U3N GND_96 F18
GND_97 F2
GND_98 F20
AF17 AE10 M6 GND_99 F22
NC_UPHYAB_DP_CALR NC_72 N13 GND_32 GND_100 F24
2160856030-A0_FCBGA631 N16 GND_33 GND_101 F26
C
JET@ N18 GND_34 GND_102 F6 C
N21 GND_35 GND_103 F8
GND_36 GND GND_104
2160856030-A0_FCBGA631 P6 G10
JET@ P9 GND_37 GND_105 G27
R12 GND_38 GND_106 G31
R15 GND_39 GND_107 G8
R17 GND_40 GND_108 H14
R20 GND_41 GND_109 H17
T13 GND_42 GND_110 H2
T16 GND_43 GND_111 H20
T18 GND_44 GND_112 H6
T21 GND_45 GND_113 J27
T6 GND_46 GND_114 J31
ASIC Ball Topaz Jet ASIC Ball Topaz Jet U15 GND_47 GND_115 K11
U17 GND_48 GND_116 K2
U20 GND_49 GND_117 K22
U10,T10 VDDC NC U1 BP_0 NC GND_50 GND_118
U9 K6
AB13,W9 V13 GND_51 GND_119
AB11,AB12 U3 BP_1 NC V16 GND_52
GND_53
AC11,AC13 V18
GND_54
AC14,Y9,W10 Y10
Y15 GND_55
AM26 DIECRACKMON NC GND_56
Y17
Y20 GND_57
R11 GND_58 A32
Y11 NC DBG_DATA13 GND_59 VSS_MECH_1
AC20 FB_VDDC NC T11 AM1
AA11 GND_60 VSS_MECH_2 AM32
M12 GND_61 VSS_MECH_3
AE9 NC DBG_DATA14 GND_62
AD20 FB_VSS NC N11
V11 GND_63
GND_64
L9 NC DBG_DATA15
W1 FB_VDDCI NC
N9 NC DBG_DATA16 2160856030-A0_FCBGA631
B W3 FB_VSS NC JET@ B

AE8 NC DBG_DATA12
AJ11 GPIO_SVC NC_SVI2
AL9 NC DBG_CNTL0
AK12 GPIO_SVD NC_SVI2
H13,H16,H19,J10 VMEMIO VDDR1
AL11 GPIO_SVT NC_SVI2 J23,J24,J9,K10
K23,K24,K9,L11
N6 GPIO_11 NC_GPIO11 L12,L13,L20,L21
L22
N5 GPIO_12 NC_GPIO12
AA17,AA18 VDD_GPIO33 VDDR3
N3 GPIO_13 NC_GPIO13 AB17,AB18

AJ27 WAKEB NC_VSYNC

AA20,AA21 VDD_GPIO18 VDD_CT
AB20,AB21
T8 PCC/GPIO_6 GPIO_6

AA3 PLL_ANALOG_OUT NC

AA1 PLL_ANALOG_IN NC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet DP Power/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 20 of 65
5 4 3 2 1
 1 2 3 4 5

UV3F
FBA_MA[15..0] 22,23
A A
FBA_BA[2..0] 22,23 GDDR5/DDR3 GDDR5/DDR3
FBA_D0 K27 K17 FBA_MA0
22,23 FBA_DQS[7..0] DQA0_0 MAA0_0
FBA_D1 J29 J20 FBA_MA1
FBA_D2 H30 DQA0_1 MAA0_1 H23 FBA_MA2
22,23 FBA_DQM[7..0] DQA0_2 MAA0_2
FBA_D3 H32 G23 FBA_MA3
FBA_D4 G29 DQA0_3 MAA0_3 G24 FBA_MA4
22,23 FBA_DQS#[7..0] DQA0_4 MAA0_4
FBA_D5 F28 H24 FBA_MA5
FBA_D[0..63] FBA_D6 F32 DQA0_5 MAA0_5 J19 FBA_MA6
22,23 FBA_D[0..63] DQA0_6 MAA0_6
FBA_D7 F30 K19 FBA_MA7
FBA_D8 C30 DQA0_7 MAA0_7 G20 FBA_MA13
FBA_D9 F27 DQA0_8 MAA0_8 L17 FBA_MA15
FBA_D10 A28 DQA0_9 MAA0_9
FBA_D11 C28 DQA0_10 J14 FBA_MA8
FBA_D12 E27 DQA0_11 MAA1_0 K14 FBA_MA9
FBA_D13 G26 DQA0_12 MAA1_1 J11 FBA_MA10
FBA_D14 D26 DQA0_13 MAA1_2 J13 FBA_MA11
FBA_D15 F25 DQA0_14 MAA1_3 H11 FBA_MA12
FBA_D16 A25 DQA0_15 MAA1_4 G11 FBA_BA2
FBA_D17 C25 DQA0_16 MAA1_5 J16 FBA_BA0
DQA0_17 MAA1_6

MEMORY INTERFACE
FBA_D18 E25 L15 FBA_BA1
FBA_D19 D24 DQA0_18 MAA1_7 G14 FBA_MA14
FBA_D20 E23 DQA0_19 MAA1_8 L16
FBA_D21 F23 DQA0_20 MAA1_9
FBA_D22 D22 DQA0_21 E32 FBA_DQM0
FBA_D23 F21 DQA0_22 WCKA0_0 E30 FBA_DQM1
FBA_D24 E21 DQA0_23 WCKA0B_0 A21 FBA_DQM2
FBA_D25 D20 DQA0_24 WCKA0_1 C21 FBA_DQM3
FBA_D26 F19 DQA0_25 WCKA0B_1 E13 FBA_DQM4
FBA_D27 A19 DQA0_26 WCKA1_0 D12 FBA_DQM5
FBA_D28 D18 DQA0_27 WCKA1B_0 E3 FBA_DQM6
FBA_D29 F17 DQA0_28 WCKA1_1 F4 FBA_DQM7
+1.5VS_VGA FBA_D30 A17 DQA0_29 WCKA1B_1
FBA_D31 C17 DQA0_30 H28 FBA_DQS0
FBA_D32 E17 DQA0_31 EDCA0_0 C27 FBA_DQS1
B
FBA_D33 D16 DQA1_0 EDCA0_1 A23 FBA_DQS2 B
FBA_D34 F15 DQA1_1 EDCA0_2 E19 FBA_DQS3
DQA1_2 EDCA0_3
1
FBA_D35 A15 E15 FBA_DQS4
RV5 FBA_D36 D14 DQA1_3 EDCA1_0 D10 FBA_DQS5
40.2_0402_1% FBA_D37 F13 DQA1_4 EDCA1_1 D6 FBA_DQS6
DIS@ FBA_D38 A13 DQA1_5 EDCA1_2 G5 FBA_DQS7
FBA_D39 C13 DQA1_6 EDCA1_3
2

FBA_D40 E11 DQA1_7 H27 FBA_DQS#0

CV72 FBA_D41 A11 DQA1_8 DDBIA0_0 A27 FBA_DQS#1
FBA_D42 C11 DQA1_9 DDBIA0_1 C23 FBA_DQS#2
FBA_D43 F11 DQA1_10 DDBIA0_2 C19 FBA_DQS#3
DQA1_11 DDBIA0_3
1

1U_0402_10V6-K
1 FBA_D44 A9 C15 FBA_DQS#4
RV6 FBA_D45 C9 DQA1_12 DDBIA1_0 E9 FBA_DQS#5
100_0402_5% FBA_D46 F9 DQA1_13 DDBIA1_1 C5 FBA_DQS#6
+1.5VS_VGA DQA1_14 DDBIA1_2
DIS@
DIS@ FBA_D47 D8 H4 FBA_DQS#7
2 FBA_D48 E7 DQA1_15 DDBIA1_3
2

FBA_D49 A7 DQA1_16 L18 FBA_ODTA0

DQA1_17 ADBIA0 FBA_ODTA0 22
FBA_D50 C7 K16 FBA_ODTA1
DQA1_18 ADBIA1 FBA_ODTA1 23
FBA_D51 F7
DQA1_19
1

FBA_D52 A5 H26 FBA_CLKA0

DQA1_20 CLKA0 FBA_CLKA0 22
RV7 FBA_D53 E5 H25 FBA_CLKA0#
DQA1_21 CLKA0B FBA_CLKA0# 22
40.2_0402_1% FBA_D54 C3
DIS@ FBA_D55 E1 DQA1_22 G9 FBA_CLKA1
DQA1_23 CLKA1 FBA_CLKA1 23
FBA_D56 G7 H9 FBA_CLKA1#
FBA_CLKA1# 23
2

FBA_D57 G6 DQA1_24 CLKA1B

CV73 FBA_D58 G1 DQA1_25 G22 FBA_RASA0#
DQA1_26 RASA0B FBA_RASA0# 22
FBA_D59 G3 G17 FBA_RASA1#
DQA1_27 RASA1B FBA_RASA1# 23
FBA_D60 J6
DQA1_28
1

1U_0402_10V6-K

1 FBA_D61 J1 G19 FBA_CASA0#

DQA1_29 CASA0B FBA_CASA0# 22
RV8 FBA_D62 J3 G16 FBA_CASA1#
DQA1_30 CASA1B FBA_CASA1# 23
100_0402_5% FBA_D63 J5
DQA1_31
DIS@

DIS@ H22 FBA_CSA0#

2 CSA0B_0 FBA_CSA0# 22
K26 J22
2

J26 MVREFDA_1 CSA0B_1

MVREFSA_2 G13 FBA_CSA1#
C C
CSA1B_0 FBA_CSA1# 23
J25 K13
RV14 1 DIS@ 2 120_0402_1% K25 NC_120 CSA1B_1
MEM_CALRP0 K20 FBA_CKEA0
CKEA0 FBA_CKEA0 22
J17 FBA_CKEA1
CKEA1 FBA_CKEA1 23
RV9 DIS@ RV10 DIS@ G25 FBA_WEA0#
WEA0B FBA_WEA0# 22
FBA_RST# 1 2 1 2 L10 H10 FBA_WEA1#
22,23 FBA_RST# DRAM_RST WEA1B FBA_WEA1# 23
49.9_0402_1% 10_0402_5% K8
L7 CLKTESTA
CLKTESTB
1

1 1
CV74 RV11 CV75 TPV15 1 Test_Point_32MIL
120P_0402_50V8-J 5.1K_0402_5% 68P_0402_50V8-J
DIS@ DIS@ @ 2160856030-A0_FCBGA631
2 2 TPV16 1 Test_Point_32MIL JET@
2

CV76

0.1U_0402_10V7-K

CV77

0.1U_0402_10V7-K

1 1
@

2 2
1

RV12 RV13
51.1_0402_1% 51.1_0402_1%
@ @
2

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet MEM Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 21 of 65
1 2 3 4 5
 1 2 3 4 5

Memory Partition A - Lower 32 bits

FBA_MA[15..0] 21,23
UV6
UV5
FBA_BA[2..0] 21,23
M8 E3 FBA_D17
+FBA_VREFC0_U M8 E3 FBA_D2 +FBA_VREFD0_L H1 VREFCA DQL0 F7 FBA_D20
VREFCA DQL0 VREFDQ DQL1 FBA_DQS[7..0] 21,23
H1 F7 FBA_D5 F2 FBA_D23
VREFDQ DQL1 F2 FBA_D0 FBA_MA0 N3 DQL2 F8 FBA_D21
A
DQL2 A0 DQL3 Group2 (IN1) FBA_DQM[7..0] 21,23 A
FBA_MA0 N3 F8 FBA_D4 FBA_MA1 P7 H3 FBA_D16
FBA_MA1 P7 A0 DQL3 H3 FBA_D1 FBA_MA2 P3 A1 DQL4 H8 FBA_D18
A1 DQL4 Group0 (IN3) A2 DQL5 FBA_DQS#[7..0] 21,23
FBA_MA2 P3 H8 FBA_D6 FBA_MA3 N2 G2 FBA_D19
FBA_MA3 N2 A2 DQL5 G2 FBA_D3 FBA_MA4 P8 A3 DQL6 H7 FBA_D22
A3 DQL6 A4 DQL7 FBA_D[0..63] 21,23
FBA_MA4 P8 H7 FBA_D7 FBA_MA5 P2
FBA_MA5 P2 A4 DQL7 FBA_MA6 R8 A5
FBA_MA6 R8 A5 FBA_MA7 R2 A6 D7 FBA_D9
FBA_MA7 R2 A6 D7 FBA_D31 FBA_MA8 T8 A7 DQU0 C3 FBA_D10
FBA_MA8 T8 A7 DQU0 C3 FBA_D27 FBA_MA9 R3 A8 DQU1 C8 FBA_D13
FBA_MA9 R3 A8 DQU1 C8 FBA_D30 FBA_MA10 L7 A9 DQU2 C2 FBA_D12
A9 DQU2 A10/AP DQU3 Group1 (TOP)
FBA_MA10 L7 C2 FBA_D25 FBA_MA11 R7 A7 FBA_D8
FBA_MA11 R7 A10/AP DQU3 A7 FBA_D28 FBA_MA12 N7 A11 DQU4 A2 FBA_D14
A11 DQU4 Group3 (BOT) A12/BC DQU5
FBA_MA12 N7 A2 FBA_D24 FBA_MA13 T3 B8 FBA_D15
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D29 FBA_MA14 T7 A13 DQU6 A3 FBA_D11
FBA_MA14 T7 A13 DQU6 A3 FBA_D26 A14 DQU7
A14 DQU7 +1.5VS_VGA
+1.5VS_VGA
FBA_BA0 M2 B2
FBA_BA0 M2 B2 FBA_BA1 N8 BA0 VDD_1 D9
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA2 M3 BA1 VDD_2 G7
FBA_BA2 M3 BA1 VDD_2 G7 BA2 VDD_3 K2 +1.5VS_VGA
BA2 VDD_3 K2 VDD_4 K8
VDD_4 K8 VDD_5 N1
VDD_5 VDD_6

1
N1 FBA_CLKA0 J7 N9
FBA_CLKA0 J7 VDD_6 N9 FBA_CLKA0# K7 CK VDD_7 R1 RV18
21 FBA_CLKA0 CK VDD_7 CK VDD_8
FBA_CLKA0# K7 R1 FBA_CKEA0 K9 R9 4.99K_0402_1%
21 FBA_CLKA0# CK VDD_8 CKE VDD_9
FBA_CKEA0 K9 R9 DIS@
21 FBA_CKEA0 CKE VDD_9

2
FBA_ODTA0 K1 A1 CV100 +FBA_VREFC0_U
FBA_ODTA0 K1 A1 FBA_CSA0# L2 ODT VDDQ_1 A8
21 FBA_ODTA0 ODT VDDQ_1 CS VDDQ_2

0.1U_0402_10V7-K
FBA_CSA0# L2 A8 FBA_RASA0# J3 C1
21 FBA_CSA0# CS VDDQ_2 RAS VDDQ_3

1
FBA_RASA0# J3 C1 FBA_CASA0# K3 C9 1
21 FBA_RASA0# RAS VDDQ_3 CAS VDDQ_4
FBA_CASA0# K3 C9 FBA_WEA0# L3 D2 RV19
21 FBA_CASA0# CAS VDDQ_4 WE VDDQ_5
FBA_WEA0# L3 D2 E9 4.99K_0402_1%
B 21 FBA_WEA0# WE VDDQ_5 VDDQ_6 B

DIS@
E9 F1 DIS@
VDDQ_6 F1 FBA_DQS2 F3 VDDQ_7 H2 2

2
FBA_DQS0 F3 VDDQ_7 H2 FBA_DQS1 C7 DQSL VDDQ_8 H9
FBA_DQS3 C7 DQSL VDDQ_8 H9 DQSU VDDQ_9
DQSU VDDQ_9
FBA_DQM2 E7 A9
FBA_DQM0 E7 A9 FBA_DQM1 D3 DML VSS_1 B3
FBA_DQM3 D3 DML VSS_1 B3 DMU VSS_2 E1
DMU VSS_2 E1 VSS_3 G8
VSS_3 G8 FBA_DQS#2 G3 VSS_4 J2
FBA_DQS#0 G3 VSS_4 J2 FBA_DQS#1 B7 DQSL VSS_5 J8
FBA_DQS#3 B7 DQSL VSS_5 J8 DQSU VSS_6 M1 +1.5VS_VGA
DQSU VSS_6 M1 VSS_7 M9
VSS_7 M9 VSS_8 P1
VSS_8 VSS_9

1
P1 FBA_RST# T2 P9
FBA_RST# T2 VSS_9 P9 RESET VSS_10 T1 RV24
21,23 FBA_RST# RESET VSS_10 VSS_11
T1 L8 T9 4.99K_0402_1%
L8 VSS_11 T9 ZQ VSS_12 DIS@
ZQ VSS_12

2
J1 B1 CV103 +FBA_VREFD0_L
NC1 VSSQ_1
1

1
J1 B1 L1 B9
NC1 VSSQ_1 NC2 VSSQ_2

0.1U_0402_10V7-K
RV15 RV16 L1 B9 RV17 J9 D1
NC2 VSSQ_2 NC3 VSSQ_3

1
10K_0402_5% 243_0402_1% J9 D1 243_0402_1% L9 D8 1
@ DIS@ L9 NC3 VSSQ_3 D8 DIS@ FBA_MA15 M7 NC4 VSSQ_4 E2 RV25
FBA_MA15 M7 NC4 VSSQ_4 E2 NC5 VSSQ_5 E8 4.99K_0402_1%
2

2
NC5 VSSQ_5 VSSQ_6

DIS@
E8 F9 DIS@
VSSQ_6 F9 VSSQ_7 G1 2

2
VSSQ_7 G1 VSSQ_8 G9
VSSQ_8 G9 VSSQ_9
VSSQ_9 96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3 MT41J256M16HA-093G
MT41J256M16HA-093G X76@
X76@
C C

FBA_CLKA0

+1.5VS_VGA UV6 SIDE +1.5VS_VGA UV7 SIDE

1
CV78 CV79 CV80 CV81 CV82 CV83 CV89 CV90 CV91 CV92 CV93 CV94 RV26
40.2_0402_1%
10U_0603_6.3V6-M

10U_0603_6.3V6-M

DIS@
1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1 1 1 1 1 1 1 1 1 1 1 1

2
CV104 DIS@
1 2
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

2 2 2 2 2 2 2 2 2 2 2 2 .01U_0402_16V7-K

1
RV27
40.2_0402_1%
DIS@

2
+1.5VS_VGA UV6 SIDE +1.5VS_VGA UV7 SIDE
FBA_CLKA0#
CV84 CV85 CV86 CV87 CV88 CV95 CV96 CV97 CV98 CV99
0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1 1 1 1 1 1 1 1 1 1
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

2 2 2 2 2 2 2 2 2 2

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet DDR3 VRAM 0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 22 of 65
1 2 3 4 5
 1 2 3 4 5

Memory Partition A - Upper 32 bits

UV7
FBA_MA[15..0] 21,22
UV8
+FBA_VREFC1_U M8 E3 FBA_D36
VREFCA DQL0 FBA_BA[2..0] 21,22
H1 F7 FBA_D34 M8 E3 FBA_D60
VREFDQ DQL1 F2 FBA_D37 +FBA_VREFD1_L H1 VREFCA DQL0 F7 FBA_D58
A A
DQL2 VREFDQ DQL1 FBA_DQS[7..0] 21,22
FBA_MA0 N3 F8 FBA_D35 F2 FBA_D63
FBA_MA1 P7 A0 DQL3 H3 FBA_D39 FBA_MA0 N3 DQL2 F8 FBA_D59
A1 DQL4 Group4 (IN1) A0 DQL3 FBA_DQM[7..0] 21,22
FBA_MA2 P3 H8 FBA_D32 FBA_MA1 P7 H3 FBA_D56 Group7 (IN3)
FBA_MA3 N2 A2 DQL5 G2 FBA_D38 FBA_MA2 P3 A1 DQL4 H8 FBA_D62
A3 DQL6 A2 DQL5 FBA_DQS#[7..0] 21,22
FBA_MA4 P8 H7 FBA_D33 FBA_MA3 N2 G2 FBA_D57
FBA_MA5 P2 A4 DQL7 FBA_MA4 P8 A3 DQL6 H7 FBA_D61
A5 A4 DQL7 FBA_D[0..63] 21,22
FBA_MA6 R8 FBA_MA5 P2
FBA_MA7 R2 A6 D7 FBA_D41 FBA_MA6 R8 A5
FBA_MA8 T8 A7 DQU0 C3 FBA_D47 FBA_MA7 R2 A6 D7 FBA_D55
FBA_MA9 R3 A8 DQU1 C8 FBA_D42 FBA_MA8 T8 A7 DQU0 C3 FBA_D51
FBA_MA10 L7 A9 DQU2 C2 FBA_D43 FBA_MA9 R3 A8 DQU1 C8 FBA_D54
FBA_MA11 R7 A10/AP DQU3 A7 FBA_D44 FBA_MA10 L7 A9 DQU2 C2 FBA_D48
A11 DQU4 Group5 (TOP) A10/AP DQU3
FBA_MA12 N7 A2 FBA_D46 FBA_MA11 R7 A7 FBA_D52 Group6 (BOT)
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D45 FBA_MA12 N7 A11 DQU4 A2 FBA_D50 +1.5VS_VGA
FBA_MA14 T7 A13 DQU6 A3 FBA_D40 FBA_MA13 T3 A12/BC DQU5 B8 FBA_D53
A14 DQU7 FBA_MA14 T7 A13 DQU6 A3 FBA_D49
A14 DQU7

1
+1.5VS_VGA RV30
+1.5VS_VGA
FBA_BA0 M2 B2 4.99K_0402_1%
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA0 M2 B2 DIS@
FBA_BA2 M3 BA1 VDD_2 G7 FBA_BA1 N8 BA0 VDD_1 D9

2
BA2 VDD_3 K2 FBA_BA2 M3 BA1 VDD_2 G7 CV127 +FBA_VREFC1_U
VDD_4 K8 BA2 VDD_3 K2
VDD_5 VDD_4

0.1U_0402_10V7-K
N1 K8
VDD_6 VDD_5

1
FBA_CLKA1 J7 N9 N1 1
21 FBA_CLKA1 CK VDD_7 VDD_6
FBA_CLKA1# K7 R1 FBA_CLKA1 J7 N9 RV31
21 FBA_CLKA1# CK VDD_8 CK VDD_7
FBA_CKEA1 K9 R9 FBA_CLKA1# K7 R1 4.99K_0402_1%
21 FBA_CKEA1 CKE VDD_9 CK VDD_8

DIS@
FBA_CKEA1 K9 R9 DIS@
CKE VDD_9 2

2
FBA_ODTA1 K1 A1
21 FBA_ODTA1 ODT VDDQ_1
FBA_CSA1# L2 A8 FBA_ODTA1 K1 A1
21 FBA_CSA1# CS VDDQ_2 ODT VDDQ_1
FBA_RASA1# J3 C1 FBA_CSA1# L2 A8
21 FBA_RASA1# RAS VDDQ_3 CS VDDQ_2
FBA_CASA1# K3 C9 FBA_RASA1# J3 C1
21 FBA_CASA1# CAS VDDQ_4 RAS VDDQ_3
FBA_WEA1# L3 D2 FBA_CASA1# K3 C9
B 21 FBA_WEA1# WE VDDQ_5 CAS VDDQ_4 B
E9 FBA_WEA1# L3 D2
VDDQ_6 F1 WE VDDQ_5 E9
FBA_DQS4 F3 VDDQ_7 H2 VDDQ_6 F1
FBA_DQS5 C7 DQSL VDDQ_8 H9 FBA_DQS7 F3 VDDQ_7 H2 +1.5VS_VGA
DQSU VDDQ_9 FBA_DQS6 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9

1
FBA_DQM4 E7 A9
FBA_DQM5 D3 DML VSS_1 B3 FBA_DQM7 E7 A9 RV36
DMU VSS_2 E1 FBA_DQM6 D3 DML VSS_1 B3 4.99K_0402_1%
VSS_3 G8 DMU VSS_2 E1 DIS@
FBA_DQS#4 G3 VSS_4 J2 VSS_3 G8

2
FBA_DQS#5 B7 DQSL VSS_5 J8 FBA_DQS#7 G3 VSS_4 J2 CV130 +FBA_VREFD1_L
DQSU VSS_6 M1 FBA_DQS#6 B7 DQSL VSS_5 J8
VSS_7 DQSU VSS_6

0.1U_0402_10V7-K
M9 M1
VSS_8 VSS_7

1
P1 M9 1
FBA_RST# T2 VSS_9 P9 VSS_8 P1 RV37
21,22 FBA_RST# RESET VSS_10 VSS_9
T1 FBA_RST# T2 P9 4.99K_0402_1%
VSS_11 RESET VSS_10

DIS@
L8 T9 T1 DIS@
ZQ VSS_12 L8 VSS_11 T9 2

2
ZQ VSS_12
1

J1 B1
NC1 VSSQ_1

1
RV28 L1 B9 J1 B1
243_0402_1% J9 NC2 VSSQ_2 D1 RV29 L1 NC1 VSSQ_1 B9
DIS@ L9 NC3 VSSQ_3 D8 243_0402_1% J9 NC2 VSSQ_2 D1
FBA_MA15 M7 NC4 VSSQ_4 E2 DIS@ L9 NC3 VSSQ_3 D8
2

NC5 VSSQ_5 E8 FBA_MA15 M7 NC4 VSSQ_4 E2

2
VSSQ_6 F9 NC5 VSSQ_5 E8
VSSQ_7 G1 VSSQ_6 F9
VSSQ_8 G9 VSSQ_7 G1
VSSQ_9 VSSQ_8 G9 FBA_CLKA1
96-BALL VSSQ_9
SDRAM DDR3 96-BALL

1
MT41J256M16HA-093G SDRAM DDR3
X76@ MT41J256M16HA-093G RV38
C X76@ 40.2_0402_1% C
DIS@

2
CV131 DIS@
1 2
+1.5VS_VGA UV8 SIDE +1.5VS_VGA UV9 SIDE
.01U_0402_16V7-K

1
CV105 CV106 CV107 CV108 CV109 CV110 CV116 CV117 CV118 CV119 CV120 CV121
RV39
10U_0603_6.3V6-M

10U_0603_6.3V6-M

40.2_0402_1%
1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1 1 1 1 1 1 1 1 1 1 1 1 DIS@

2
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

FBA_CLKA1#
2 2 2 2 2 2 2 2 2 2 2 2

+1.5VS_VGA UV8 SIDE +1.5VS_VGA UV9 SIDE

CV111 CV112 CV113 CV114 CV115 CV122 CV123 CV124 CV125 CV126
0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1 1 1 1 1 1 1 1 1 1
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

2 2 2 2 2 2 2 2 2 2

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet DDR3 VRAM 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 23 of 65
1 2 3 4 5
 1 2 3 4 5

+0.95VS to +0.95VS_VGA +1.5VS to +1.5VS_VGA

+5VS +0.95VS +0.95VS_VGA SCS00006S00 DIS@

RB751V-40_SOD323-2
QV9 DIS@ DV5 1 2
A AO4354 1N A
8 1
RV133

1
7 2 JV1 @
+5VALW RV129 6 3 1 2 DGPU_PWREN 1 2 1.5VS_VGA_EN
1 2 1.5VS_VGA_EN 55
180K_0402_1% 5 240K_0402_5%
DIS@ JUMP_43X79 1 1 1
CV161 CV162 CV172

2
4.7U_0603_6.3V6-K 0.1U_0402_10V7-K DIS@ 0.1U_0402_10V7-K
RV137 DIS@ @ @
1

300_0402_5% 2 2 2

2
RV142 DIS@
100K_0402_5% RV130

1
DIS@ 0_0402_5%
DIS@
2

1
+0.95VS_VGA_GATE D RV141
QV11 2 2 1 DGPU_PWREN#
2N7002KW_SOT323-3 G

1
D SB00000YY00 10K_0402_5%
1 S

3
2 QV10 CV160 DIS@ DIS@
G 2N7002KW_SOT323-3 .01U_0402_16V7-K
3 S SB00000YY00 DIS@
DIS@ 2
1

D
DGPU_PWREN 2 QV12
G 2N7002KW_SOT323-3
S SB00000YY00
3

DIS@

B B

+1.8VS to +1.8VS_VGA
+1.8VS
VIN 1.8V (VBIAS=5V), IMAX=6A, Rds=15mohm
UV11 DIS@
1 5
VIN1 GND +1.8VS_VGA
1 2 6 CV165 1DIS@ 2820P_0402_50V7-K
+5VALW VIN2 CT JV2 @
CV163 18PWRON_R 3 7 +18VS_LS 1 2
1U_0402_6.3V6-K ON VOUT1 1 2
2@ 4 8 JUMP_43X79
VBIAS VOUT2 1

1 9 CV166
THERMALPAD 0.1U_0402_10V7-K
CV164 2@
0.1U_0402_10V7-K
2 DIS@
TPS22965DSGR_WSON8_2X2

SCS00006S00
RB751V-40_SOD323-2
DV4 1 2 DIS@

From FCH RV132

DGPU_PWREN 1 2 18PWRON_R
12,17,59 DGPU_PWREN
3.3K_0402_5%
C 1 C
1

DIS@
RV131 CV167
100K_0402_5% 0.1U_0402_10V7-K
@ 2 DIS@
2

+3VS to +3VS_VGA
+VGA_CORE

+5VALW +3VS +3VS_VGA

2
JV3 @ RV144
1

3 1 1 2 100_0402_1%
RV134 1 2 @
47K_0402_5% QV5 JUMP_43X39

1
DIS@ AO3413_SOT23-3
G
2

DIS@
2

RV138

1
300_0402_5% D RV143
2

@ QV13 2 2 1 DGPU_PWREN#
RV135 2N7002KW_SOT323-3 G
1

10K_0402_5% SB00000YY00 S 10K_0402_5%

3

DIS@ @ @
1

DGPU_PWREN# D RV139
QV8 2 2 1 DGPU_PWREN#
2N7002KW_SOT323-3 G
1

D D SB00000YY00 10K_0402_5% D
1 S
3

DGPU_PWREN 2 QV6 CV169 @ @

G 2N7002KW_SOT323-3 .01U_0402_16V7-K
S SB00000YY00 DIS@
3

DIS@ 2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Topaz & Jet SWITCH POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 24 of 65
1 2 3 4 5
 5 4 3 2 1

PS_0[1] ROM_CONFIG[0] Bit

STRAP_BIOS_ROM_EN = 1 MLPS
PS_0[2] ROM_CONFIG[1] ROM_CONFIG[2:0] = [001] 256MB
5 4 3 2 1
PS_0[3] ROM_CONFIG[2]
PS_0[5:1] 1 1 0 0 1
D
PS_0[4] N/A 1 (Default) D
PS_1[5:1] 1 1 0 0 0
PS_0[5] N/A 1 (Default) PS_2[5:1] 1 1 0 0 0
PS_3[5:1] 1 1 X X X
PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported

PS_1[2] STRAP_BIF_CLK_PM_EN 0 = The CLKREQB power management

capability is disabled

PS_1[3] N/A 0 (Default)

PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING 1 = The transmitter full-swing

is enabled

PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled

PS_2[1] N/A 0 (Default)

C PS_2[2] N/A 0 (Default) C

PS_2[3] STRAP_BIOS_ROM_EN 0 = Disable the external BIOS ROM device

PS_0 PS_1 PS_2 PS_3

PS_2[4] N/A 1 (Default)

RV98 RV99 RV102 RV103 RV100 RV101 RV104 RV105

PS_2[5] N/A 1 (Default)

Micron PU 8.45K PD 2K NC PD 4.75K NC PD 4.75K PU 3.24K PD 5.62K

PS_3[1] BOARD_CONFIG[0] PS_3[3..1] 2G
101 = Micron 2G
PS_3[2] BOARD_CONFIG[1] 110 = Samsung 2G Samsung PU 8.45K PD 2K NC PD 4.75K NC PD 4.75K
111 = Hynix 2G
PU 3.4K PD 10K
PS_3[3] BOARD_CONFIG[2] 2G

Hynix PU 8.45K PD 2K NC PD 4.75K NC PD 4.75K PU 4.75K NC

PS_3[4] N/A 1 (Default) 2G

PS_3[5] N/A 1 (Default)

3.24K SD03432418T
5.62K SD03456210T
3.4K SD03434010T
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 Topaz & Jet BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 25 of 65
5 4 3 2 1
 5 4 3 2 1

LCDVDD Circuit CMOS Camera

+3VS +LCDVDD_CON
U1
5 1 +LCDVDD R37 1 2 0_0805_5%
IN2 OUT +3VS +3VS_CMOS
1 2 @ 1
GND
C1 4 3 LCD_ENVDD C2 R5 1 2 0_0603_5%
1U_0402_6.3V6-K IN1 EN 4.7U_0603_6.3V6-K
D D
2 G5243AT11U_SOT23-5 2
@
SA00005XJ00

+3VS +3VS_CMOS
+3VS
U3 R76 @
5 1 +3VS_CMOSP 1 2
IN2 OUT

2
1 2 0_0603_5% 1
R3 C3 GND C4
4.7K_0402_5% 1U_0402_6.3V6-K 4 3 CMOS_ON# 4.7U_0603_6.3V6-K
IN1 EN CMOS_ON# 13

2
@ @
R2 2 G5243AT11U_SOT23-5 2

1
100K_0402_5% SA00005XJ00
LCD_ENVDD @

1
D
2 Q12
From APU G 2N7002KW_SOT323-3
S SB00000YY00

3
R1 1 C
APU_ENVDD 1 2 2
7 APU_ENVDD B
2.2K_0402_5% E
3
2

Q1
R4 MLMBT3904WT1G NPN SOT323-3
100K_0402_5%
@
1

C C

CMOS USB Port5

14 USB20_N5 USB20_N5 R6 1 @ 2 0_0402_5% USB20_N5_CMOS JLCD

+LEDVDD W= 80 mil 1
1 2 2 1
3 2
L1 DLW21SN900HQ2L_4P R136 1 2 100K_0402_5% 4 3
4 3 SM070003100 EMC@ R10 1 2 0_0402_5% @ +3VDMIC 5 4
+3VS W= 20 mil 5
+3VS_CMOS W= 20 mil 6
USB20_P5 R7 1 @ 2 0_0402_5% USB20_P5_CMOS 7 6
14 USB20_P5 +LCDVDD_CON W= 60 mil 7
8
+3VALW_LOGO 9 8
LOGO_LED# 10 9
38,41 LOGO_LED# 10
7 APU_BKOFF# R135 1 @ 2 0_0402_5% EDP_BKOFF# 11
APU_EDP_PWM 12 11
7 APU_EDP_PWM 12
38 EC_BKOFF# R134 1 2 0_0402_5% @ 13
DMIC_DATA 14 13
B+ 34 DMIC_DATA 14
DMIC_CLK 15
34 DMIC_CLK 15
2A 80 mil 2A 80 mil 16
R8 1 2 0_0805_5% +LEDVDD USB20_N5_CMOS 17 16
USB20_P5_CMOS 18 17
1 18
@ 19
C8 APU_EDP_AUX# C13 1 2 0.1U_0402_10V7-K APU_EDP_AUX#_CON 20 19 31
7 APU_EDP_AUX# 20 GND1
B 4.7U_0805_25V6-K APU_EDP_AUX C14 1 2 0.1U_0402_10V7-K APU_EDP_AUX_CON 21 32 B
2 7 APU_EDP_AUX 21 GND2
EDP_HPD 22 33
+LEDVDD +3VS_CMOS 7 EDP_HPD 22 GND3
23 34
24 23 GND4 35
+3VALW APU_EDP_TX1- C9 1 2 0.1U_0402_10V7-K APU_EDP_TX1-_CON 25 24 GND5 36
R9 7 APU_EDP_TX1- 25 GND6
RFC5 RFC6 RFC7 RFC8 APU_EDP_TX1+ C10 1 2 0.1U_0402_10V7-K APU_EDP_TX1+_CON 26 37
7 APU_EDP_TX1+ 26 GND7
1 2 +3VALW_LOGO 27 38
27 GND8
2200P_0402_50V7-K

2200P_0402_50V7-K

APU_EDP_TX0- C11 1 2 0.1U_0402_10V7-K APU_EDP_TX0-_CON 28 39

7 APU_EDP_TX0- 28 GND9
47P_0402_50V8-J

47P_0402_50V8-J
2 1 2 1 APU_EDP_TX0+ C12 1 2 0.1U_0402_10V7-K APU_EDP_TX0+_CON 29 40
2.2K_0402_1% 7 APU_EDP_TX0+ 29 GND10
30 41
RF_NS@

RF_NS@
30 GND11
RF@

RF@

I-PEX_20525-030E-02
1 2 1 2 ME@

EDP_HPD

For RF For RF EDP_BKOFF#

1
R12 R13
100K_0402_5% 100K_0402_5%
ESD request +LCDVDD_CON +3VALW_LOGO

2
+3VALW_LOGO
RFC9 RFC10 RFC11 RFC12
LOGO_LED#
2200P_0402_50V7-K

2200P_0402_50V7-K
47P_0402_50V8-J

47P_0402_50V8-J

2 1 2 1
3

RF_NS@

RF_NS@

D1
RF@

RF@

PESD5V0U2BT_SOT23-3
EMC@ 1 2 1 2
A A
1

For RF For RF

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 LCD/CMOS CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 26 of 65
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS +5VS_HDMI +3VS

1
R14 R15 R16 R17

2
R18

G
2.2K_0402_5% 2.2K_0402_5% 2K_0402_1% 2K_0402_1%
1M_0402_5% Q5

2
G
2N7002KW_SOT323-3

2
D SB00000YY00 D
APU_HDMI_CLK 1 6 HDMI_CLK_CON HDMI_HPD 3 1 HDMI_DET_CON

S
7 APU_HDMI_CLK 7 HDMI_HPD

D
5

2
Q4A

G
2N7002KDWH_SOT363-6 R19
sb00000YR00 100K_0402_5%

APU_HDMI_DATA 4 3 HDMI_DAT_CON

S
7 APU_HDMI_DATA

1
D
Q4B
2N7002KDWH_SOT363-6
sb00000YR00

7 APU_HDMI_CLK+ APU_HDMI_CLK+ C15 1 2 0.1U_0402_10V7-K HDMI_CLK+_C R20 1 @ 2 0_0402_5% HDMI_CLK+_CON

1 2
+5VS U2 +5VS_HDMI
L2 DLW21SN900HQ2L_4P
4 3 SM070003100 EMC@ 3 1
VOUT

7 APU_HDMI_CLK- APU_HDMI_CLK- C16 1 2 0.1U_0402_10V7-K HDMI_CLK-_C R21 1 @ 2 0_0402_5% HDMI_CLK-_CON 1 C25

VIN 0.1U_0402_10V7-K
2 2
GND

7 APU_HDMI_TX0+ APU_HDMI_TX0+ C17 1 2 0.1U_0402_10V7-K HDMI_TX0+_C R22 1 @ 2 0_0402_5% HDMI_TX0+_CON 1 1

G5250Q1T73U SOT23 3P
1 2 C23 C24 SA00004ZB0J
2200P_0402_50V7-K 0.1U_0402_10V7-K @
L3 DLW21SN900HQ2L_4P 2@ 2@
4 3 SM070003100 EMC@

7 APU_HDMI_TX0- APU_HDMI_TX0- C18 1 2 0.1U_0402_10V7-K HDMI_TX0-_C R23 1 @ 2 0_0402_5% HDMI_TX0-_CON

C C

7 APU_HDMI_TX1+ APU_HDMI_TX1+ C19 1 2 0.1U_0402_10V7-K HDMI_TX1+_C R24 1 @ 2 0_0402_5% HDMI_TX1+_CON

1 2
JHDMI
L4 DLW21SN900HQ2L_4P HDMI_DET_CON 19
4 3 SM070003100 EMC@ 18 HP_DET
+5VS_HDMI +5V
17
APU_HDMI_TX1- C20 1 2 0.1U_0402_10V7-K HDMI_TX1-_C R25 1 @ 2 0_0402_5% HDMI_TX1-_CON HDMI_DAT_CON 16 DDC/CEC_GND
7 APU_HDMI_TX1- SDA
HDMI_CLK_CON 15
14 SCL
APU_HDMI_TX2+ C21 1 2 0.1U_0402_10V7-K HDMI_TX2+_C R26 1 @ 2 0_0402_5% HDMI_TX2+_CON 13 Reserved
7 APU_HDMI_TX2+ CEC
HDMI_CLK-_CON 12 20
1 2 11 CK- GND1 21
HDMI_CLK+_CON 10 CK_shield GND2 22
L5 DLW21SN900HQ2L_4P HDMI_TX0-_CON 9 CK+ GND3 23
4 3 SM070003100 EMC@ 8 D0- GND4
HDMI_TX0+_CON 7 D0_shield
APU_HDMI_TX2- C22 1 2 0.1U_0402_10V7-K HDMI_TX2-_C R27 1 @ 2 0_0402_5% HDMI_TX2-_CON HDMI_TX1-_CON 6 D0+
7 APU_HDMI_TX2- D1-
5
HDMI_TX1+_CON 4 D1_shield
HDMI_TX2-_CON 3 D1+
2 D2-
HDMI_TX2+_CON 1 D2_shield
D2+
CONCR_099ATAC19NBLCNF
ME@

HDMI Connector
B B

For ESD

D2 RCLAMP0524PATCT_SLP2510P8-10-9 D3 RCLAMP0524PATCT_SLP2510P8-10-9 D4 RCLAMP0524PATCT_SLP2510P8-10-9

HDMI_CLK-_CON R28 1 2 499_0402_1% HDMI_GND

HDMI_CLK+_CON R29 1 2 499_0402_1%
HDMI_TX0-_CON R30 1 2 499_0402_1% +5VS_HDMI 1 9 +5VS_HDMI HDMI_CLK-_CON 1 9 HDMI_CLK-_CON HDMI_TX1-_CON 1 9 HDMI_TX1-_CON
HDMI_TX0+_CON R31 1 2 499_0402_1% HDMI_DET_CON 2 8 HDMI_DET_CON HDMI_CLK+_CON 2 8 HDMI_CLK+_CON HDMI_TX1+_CON 2 8 HDMI_TX1+_CON
HDMI_DAT_CON 4 7 HDMI_DAT_CON HDMI_TX0-_CON 4 7 HDMI_TX0-_CON HDMI_TX2-_CON 4 7 HDMI_TX2-_CON
HDMI_CLK_CON 5 6 HDMI_CLK_CON HDMI_TX0+_CON 5 6 HDMI_TX0+_CON HDMI_TX2+_CON 5 6 HDMI_TX2+_CON

HDMI_TX1-_CON R32 1 2 499_0402_1%

HDMI_TX1+_CON R33 1 2 499_0402_1% EMC@ EMC@ EMC@
3

3
HDMI_TX2-_CON R34 1 2 499_0402_1%
HDMI_TX2+_CON R35 1 2 499_0402_1%
1

D
+3VS 2 Q6
G 2N7002KW_SOT323-3
S SB00000YY00
3

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 27 of 65
5 4 3 2 1
 1 2 3 4 5

+CRT_VCC and +5VS_HDMI trace width 100mils

+5VS +CRT_VCC +5VS_HDMI

UCR1

3 RCR9 1 2 0_0805_5%
DCR1 DCR2
40 mils VOUT
1 6 CRT_R_CON CRT_DDC_CLK_CON 1 6 HSYNC_CON 1 1 @
V_I/O1 V_I/O4 V_I/O1 V_I/O4 VIN
2 5 +CRT_VCC 2 5 +CRT_VCC 1 1 2 CCR3
Ground VBUS Ground VBUS CCR1 CCR2 GND 0.1U_0402_10V7-K
A A
CRT_B_CON 3 4 CRT_G_CON VSYNC_CON 3 4 CRT_DDC_DAT_CON 2200P_0402_50V7-K 0.1U_0402_10V7-K 2
V_I/O2 V_I/O3 V_I/O2 V_I/O3 G5250Q1T73U SOT23 3P
CM1293A_SC-74 CM1293A_SC-74 2 2 SA00004ZB0J
SC300003N00 SC300003N00
EMC@ EMC@ @

closer to JCRT

Only for Edge 15''

JCRT
6
From FCH LCR1 Test_Point_20MIL 1 TP2 11
FCH_CRT_R 1 2 CRT_R_CON 1
13 FCH_CRT_R
BLM15BB750SN1D_2P 7
LCR2 CRT_DDC_DAT_CON 12
FCH_CRT_G 1 2 CRT_G_CON 2
13 FCH_CRT_G
BLM15BB750SN1D_2P 8
LCR3 HSYNC_CON 13
FCH_CRT_B 1 2 CRT_B_CON 3
13 FCH_CRT_B
BLM15BB750SN1D_2P +CRT_VCC 9

CCR4

10P_0402_50V8-J

CCR5

10P_0402_50V8-J

CCR6

10P_0402_50V8-J

CCR7

10P_0402_50V8-J

CCR8

10P_0402_50V8-J

CCR9

10P_0402_50V8-J
1 1 1 1 1 1 VSYNC_CON 14 16

1
150_0402_1%

150_0402_1%

150_0402_1%
4 17

RCR1

RCR2

RCR3
10
CRT_DDC_CLK_CON 15
2 2 2 2 2 2 +CRT_VCC 5

2
SUYIN_070546HR015S21BZR
B B
ME@

closer to JCRT CRT Connector

+CRT_VCC

@
CCR10 1 2 0.1U_0402_10V7-K

1
From FCH LCR4

OE#
FCH_CRT_HSYNC 2 4 CRT_HSYNC_1 1 2 HSYNC_CON
13 FCH_CRT_HSYNC A Y BLM15BB750SN1D_2P

G
UCR2 1
3 74AHCT1G125GW_SOT353-5 CCR12
10P_0402_50V8-J
EMC_NS@
2
+CRT_VCC

@
CCR11 1 2 0.1U_0402_10V7-K
5

LCR5
P

OE#

FCH_CRT_VSYNC 2 4 CRT_VSYNC_1 1 2 VSYNC_CON

13 FCH_CRT_VSYNC A Y BLM15BB750SN1D_2P
G

C UCR3 1 C
74AHCT1G125GW_SOT353-5 CCR13
3

10P_0402_50V8-J
EMC_NS@
2

+3VS +CRT_VCC

2
RCR7 RCR8

2
G 2.2K_0402_5% 2.2K_0402_5%

From FCH

1
EMC_NS@
FCH_CRT_DDC_DAT 1 6 CRT_DDC_DAT_R RCR12 1 2 0_0402_5% CRT_DDC_DAT_CON
S

13 FCH_CRT_DDC_DAT
D

QCR1A
5

2N7002KDWH_SOT363-6
G

sb00000YR00
@
EMC_NS@
FCH_CRT_DDC_CLK 4 3 CRT_DDC_CLK_R RCR13 1 2 0_0402_5% CRT_DDC_CLK_CON
S

13 FCH_CRT_DDC_CLK
D

QCR1B
2N7002KDWH_SOT363-6 1 1
sb00000YR00 CCR14 CCR15
@ 100P_0402_50V8-J 100P_0402_50V8-J
EMC_NS@ EMC_NS@
RCR10 1 2 0_0402_5% @ 2 2
D D

RCR11 1 2 0_0402_5% @

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 CRT CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 28 of 65
1 2 3 4 5
 5 4 3 2 1

thermal sensor
Close U4
REMOTE1+ +3VS
placed near by VRAM REMOTE1+
Under DIMM
1 1

1
D U4 C44 C D
C41 100P_0402_50V8-J 2
2200P_0402_50V7-K @ B
2 REMOTE1- 1 10 EC_SMB_CK3 2 E
EC_SMB_CK3 7,18,38

3
VCC SCL REMOTE1- Q8
1 REMOTE1+ 2 9 EC_SMB_DA3 MLMBT3904WT1G NPN SOT323-3
DP1 SDA EC_SMB_DA3 7,18,38
C43 REMOTE1- 3 8
REMOTE2+ 0.1U_0402_10V7-K DN1 ALERT#
2 REMOTE2+ 4 7
1 DP2 THERM# Close to cpu side

1
C42 REMOTE2- 5 6 REMOTE2+
2200P_0402_50V7-K DN2 GND R42 1

1
2 REMOTE2- 10K_0402_5% C45 C
F75303M_MSOP10 @ 100P_0402_50V8-J 2
@ B

2
2 E
+3VS

3
REMOTE2- Q9
Address 1001_101xb MLMBT3904WT1G NPN SOT323-3

REMOTE2+/-:
internal pull up 1.2K to 1.5V Trace width/space:10/10 mil
R for initial thermal Trace length:<8"
shutdown temp

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/14 Deciphered Date 2012/12/21 Thermal sensor
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 29 of 65
5 4 3 2 1
 5 4 3 2 1

+5VALW +5V_CHGUSB

C46
@ U10 Only for Edge 15''
0.1U_0402_10V7-K 1 2 1 12
IN OUT 10 USB20_P10_C
USB20_P10 3 DP_IN 11 USB20_N10_C
14 USB20_P10 DP_OUT DM_IN
USB20_N10 2 14
14 USB20_N10 DM_OUT GND
+5VALW +USB_VCCA
For EMI +5VALW 9 AOU_DET#
W=80mils STATUS# AOU_DET# 38
W=80mils 4
U6 C28 EMC_NS@ USB_OC1# 13 ILIM_SEL
D D
14 USB_OC1# FAULT# +5VALW
1 8 1 2 1000P_0402_50V7-K AOU_EN 5
GND Vout1 38 AOU_EN EN
2 7 15 ILIM_LO
3 VIN1 Vout2 6 AOU_CTL1 6 ILIM_LO 16 ILIM_HI
VIN2 Vout3 38 AOU_CTL1 CLT1 ILIM_HI
USB_ON# 4 5 USB_OC0# 7
32,38 USB_ON# EN FLG USB_OC0# 14 CLT2
1 1 AOU_CTL3 8 17
38 AOU_CTL3 CLT3 GND_Pad
G547I2P81U_MSOP8
C26 C27
0.1U_0402_10V7-K Low Active 2.5A 1000P_0402_50V7-K @
2@ 2 EMC_NS@ TPS2546RTER_QFN16_4X4 ILIM_LO R52 1 2 20K_0402_1%

ILIM_HI R53 1 2 20K_0402_1%

Only for Edge 15''

L6 L7 L8 D11 D12 RCLAMP0524PATCT_SLP2510P8-10-9

USB20_P12 1 2 USB20_P12_C USB3TXDP2 1 2 USB3_TX2_C_P USB30_RX_P2 1 2 USB3_RX2_C_P USB20_P12_C 1 6 USB20_N12_C
V_I/O1 V_I/O4
2 5
USB20_N12 4 3 USB20_N12_C USB3TXDN2 4 3 USB3_TX2_C_N USB30_RX_N2 4 3 USB3_RX2_C_N Ground VBUS +USB_VCCA USB3_TX2_C_P 1 9 USB3_TX2_C_P
C C
3 4 USB3_TX2_C_N 2 8 USB3_TX2_C_N
DLW21SN900HQ2L_4P DLW21SN900HQ2L_4P DLW21SN900HQ2L_4P V_I/O2 V_I/O3 USB3_RX2_C_P 4 7 USB3_RX2_C_P
SM070003100 SM070003100 SM070003100 CM1293A_SC-74 USB3_RX2_C_N 5 6 USB3_RX2_C_N
EMC@ EMC@ EMC@ SC300003N00
EMC@

EMC@

3
+USB_VCCA +USB_VCCA

JUSB2
USB30_TX_P2 C47 1 2 0.1U_0402_10V7-K USB3TXDP2 R54 1 2 0_0402_5%
EMC_NS@ USB3_TX2_C_P 9 1
14 USB30_TX_P2 StdA_SSTX+
1 1 1
USB30_TX_N2 C48 1 2 0.1U_0402_10V7-K USB3TXDN2 R55 1 2 0_0402_5%
EMC_NS@ USB3_TX2_C_N 8 VBUS + C49
14 USB30_TX_N2 StdA_SSTX- 150U_B2_6.3VM_R35M
USB20_P12 R56 1 2 0_0402_5%
EMC_NS@ USB20_P12_C 3 C50 C51
14 USB20_P12 D+ 470P_0402_50V7-K 0.1U_0402_10V7-K
7
USB20_N12 R57 1 2 0_0402_5%
EMC_NS@ USB20_N12_C 2 GND_DRAIN 10 2 2 2 @
14 USB20_N12 D- GND_1
USB30_RX_P2 R58 1 2 0_0402_5%
EMC_NS@ USB3_RX2_C_P 6 11
14 USB30_RX_P2
4 StdA_SSRX+ GND_2 12
For ESD, Close to JUSB2
USB30_RX_N2 R59 1 2 0_0402_5%
EMC_NS@ USB3_RX2_C_N 5 GND_5 GND_3 13
14 USB30_RX_N2 StdA_SSRX- GND_4
TAITW_PUBAU1-09FNLSCNN4H0
ME@

USB3.0 Connector

B B
L9 L10 L11 D13 D14 RCLAMP0524PATCT_SLP2510P8-10-9
USB20_P10_C 1 2 USB20_P10_CON USB3TXDP0 1 2 USB3_TX0_C_P USB30_RX_P0 1 2 USB3_RX0_C_P USB20_P10_CON 1 6 USB20_N10_CON
V_I/O1 V_I/O4
2 5
USB20_N10_C 4 3 USB20_N10_CON USB3TXDN0 4 3 USB3_TX0_C_N USB30_RX_N0 4 3 USB3_RX0_C_N Ground VBUS +5V_CHGUSB USB3_TX0_C_P 1 9 USB3_TX0_C_P
3 4 USB3_TX0_C_N 2 8 USB3_TX0_C_N
DLW21SN900HQ2L_4P DLW21SN900HQ2L_4P DLW21SN900HQ2L_4P V_I/O2 V_I/O3 USB3_RX0_C_P 4 7 USB3_RX0_C_P
SM070003100 SM070003100 SM070003100 CM1293A_SC-74 USB3_RX0_C_N 5 6 USB3_RX0_C_N
EMC@ EMC@ EMC@ SC300003N00
EMC@

EMC@

3
+5V_CHGUSB +5V_CHGUSB

JUSB1
USB30_TX_P0 C52 1 2 0.1U_0402_10V7-K USB3TXDP0 R60 1 2 0_0402_5%
EMC_NS@ USB3_TX0_C_P 9 1
14 USB30_TX_P0 StdA_SSTX+
1 1 1
USB30_TX_N0 C53 1 2 0.1U_0402_10V7-K USB3TXDN0 R61 1 2 0_0402_5%
EMC_NS@ USB3_TX0_C_N 8 VBUS + C54
14 USB30_TX_N0 StdA_SSTX- 150U_B2_6.3VM_R35M
USB20_P10_C R62 1 2 0_0402_5%
EMC_NS@ USB20_P10_CON 3 C55 C56
7 D+ 470P_0402_50V7-K 0.1U_0402_10V7-K
USB20_N10_C R63 1 2 0_0402_5%
EMC_NS@ USB20_N10_CON 2 GND_DRAIN 10 2 2 2 @
USB30_RX_P0 R64 1 2 0_0402_5%
EMC_NS@ USB3_RX0_C_P 6 D- GND_1 11
14 USB30_RX_P0
4 StdA_SSRX+ GND_2 12
For ESD, Close to JUSB1
USB30_RX_N0 R65 1 2 0_0402_5%
EMC_NS@ USB3_RX0_C_N 5 GND_5 GND_3 13
14 USB30_RX_N0 StdA_SSRX- GND_4
TAITW_PUBAU1-09FNLSCNN4H0
ME@

A
USB3.0 Connector A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 USB CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 30 of 65
5 4 3 2 1
 5 4 3 2 1

SATA HDD
+5VS
J1 @
1 2
+5VS 1 2 +5VS_HDD
1 1 1 1 1
JUMP_43X79
C57 C58 C59 C60 C61
D 10U_0603_6.3V6-M 10U_0603_6.3V6-M 1U_0402_10V6-K 0.1U_0402_10V7-K 1000P_0402_50V7-K D
2 2@ 2@ 2@ 2@ J2 @
1 2
+3VS 1 2 +3VS_HDD
JUMP_43X79

Only for Edge 15''

JHDD2

1
SATA_FTX_DRX_P0 C62 1 2 .01U_0402_16V7-K SATA_FTX_C_DRX_P0 2 GND1
13 SATA_FTX_DRX_P0 A+ +3VS_HDD +5VS_HDD
SATA_FTX_DRX_N0 C63 1 2 .01U_0402_16V7-K SATA_FTX_C_DRX_N0 3
13 SATA_FTX_DRX_N0 A-
4
SATA_FRX_DTX_N0 C64 1 2 .01U_0402_16V7-K SATA_FRX_C_DTX_N0 5 GND2
13 SATA_FRX_DTX_N0 SATA_FRX_DTX_P0 C65 1 2 .01U_0402_16V7-K SATA_FRX_C_DTX_P0 6 B- RFC13 RFC14 RFC15 RFC16
13 SATA_FRX_DTX_P0 7 B+
GND3

2200P_0402_50V7-K

2200P_0402_50V7-K
47P_0402_50V8-J

47P_0402_50V8-J
2 1 2 1
8
+3VS_HDD VCC_3V3_1

RF@

RF@
9 RF_NS@ RF_NS@
10 VCC_3V3_2 1 2 1 2
11 VCC_3V3_3
HDD_DETECT# 12 GND4
38 HDD_DETECT# 13 GND5
14 GND6
+5VS_HDD VCC5_1
15 For RF For RF
16 VCC5_2
17 VCC5_3
18 GND7
Pin18 connect to GND for SATA Gen3 19 RESERVED
C
20 GND8 23 C
21 VCC12_1 GND9 24
22 VCC12_2 GND10
VCC12_3

ACES_50812-0227P-001
ME@

SATA ODD & ODD Power Control +5VS TO +5VS_ODD

Only for Edge 15''
R67 1 @ 2 0_0805_5%

JODD +5VS +5VS_ODD

1
SATA_FTX_DRX_P1 C66 1 2 .01U_0402_16V7-K SATA_FTX_C_DRX_P1 2 1 U7
80 mils J3 @
13 SATA_FTX_DRX_P1
SATA_FTX_DRX_N1 C67 1 2 .01U_0402_16V7-K SATA_FTX_C_DRX_N1 3 2 80 mils 5 1 +5VS_ODD_OUT 1 2
13 SATA_FTX_DRX_N1 3 IN2 OUT 1 2
4
SATA_FRX_DTX_N1 C68 1 2 .01U_0402_16V7-K SATA_FRX_C_DTX_N1 5 4 2 JUMP_43X79
13 SATA_FRX_DTX_N1 SATA_FRX_DTX_P1 C69 1 2 .01U_0402_16V7-K SATA_FRX_C_DTX_P1 6 5 1 GND From FCH
B B
13 SATA_FRX_DTX_P1 7 6 14 C70 4 3 ODD_EN
7 GND1 IN1 EN ODD_EN 13 1
14 ZERO_ODD_DP# ZERO_ODD_DP# 8 1U_0402_6.3V6-K
9 8 15 2 G5243AT11U_SOT23-5 C71
+5VS_ODD 9 GND2

1
10 SA00005XJ00 4.7U_0603_6.3V6-K
ZERO_ODD_DA# 11 10 2
12 11 R68
13 12 100K_0402_5%
1 13

2
C91
1U_0402_10V6-K ACES_50885-0137P-001
@ 2 ME@

+5VS

R36
1 2
+5VS_ODD
10K_0402_5%
2
G

Q7
RFC17 RFC18
3 1
FCH_ODD_DA 14

2200P_0402_50V7-K
S

47P_0402_50V8-J
2 1
2N7002KW_SOT323-3

RF_NS@
SB00000YY00

RF@
R38 1 @ 2
ODD_DA_INTH# 12 1 2
0_0402_5%

For RF
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 HDD/ODD CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 31 of 65
5 4 3 2 1
 1 2 3 4 5

A A

Only for Edge 15''

JU3LC
24
23 G4
22 G3
21 G2
USB30_RX_N3 20 G1
14 USB30_RX_N3 20
USB30_RX_P3 19
14 USB30_RX_P3 19
18
USB30_TX_N3 17 18
14 USB30_TX_N3 17
USB30_TX_P3 16
14 USB30_TX_P3 16
15
APU_DOCK_TX1- 14 15
4 APU_DOCK_TX1- 14
APU_DOCK_TX1+ 13
4 APU_DOCK_TX1+ 13
12
APU_DOCK_TX0- 11 12
4 APU_DOCK_TX0- 11
APU_DOCK_TX0+ 10
4 APU_DOCK_TX0+ 10
9
APU_DOCK_AUX# 8 9
7 APU_DOCK_AUX# 8
APU_DOCK_AUX 7
7 APU_DOCK_AUX 7
6
USB20_N13 5 6
14 USB20_N13 5
USB20_P13 4
B 14 USB20_P13 4 B
3
USB20_N0 2 3
14 USB20_N0 2
USB20_P0 1
14 USB20_P0 1
ACES_50406-02071-001
ME@

CABLE

Only for Edge 15''

JU3LF
1
USB_OC2# 2 1
14 USB_OC2# 2
USB_ON# 3
30,38 USB_ON# 3
4
5 4
6 5
7 6
DOCK_HPD 8 7
7 DOCK_HPD 8
DOCK_CONSUMP 9
50 DOCK_CONSUMP 9
DOCK_DETECT# 10
14 DOCK_DETECT# 10
LID_SW# 11
38 LID_SW# 11
ON/OFFBTN# 12
38 ON/OFFBTN# 12
13
14 13
C C
15 14
16 15
17 16
18 17
+5VALW 18
+3VS 19
20 19
+3VL 20
21
22 GND1
GND2
ACES_88194-2041
ME@

FFC

+3VL +3VALW +5VALW

2
R94 R89 R88
100K_0402_5% 100K_0402_5% 100K_0402_5%
@

1
D D
ON/OFFBTN# DOCK_DETECT#

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/7 Deciphered Date 2014/12/7 One link DP CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 32 of 65
1 2 3 4 5
 2 1

NGFF typeA Card(WLAN)

+3V_WLAN +3V_WLAN

+3VALW R90 1 @ 2 0_0805_5% +3V_WLAN RFC19 RFC20

2200P_0402_50V7-K
1

47P_0402_50V8-J
+3VS R91 1 @ 2 0_0805_5% 2 1
C92
10U_0603_6.3V6-M
2

RF@
RF_NS@
1 2

+3V_WLAN

For RF
JWLBT
1 2
USB20_P6 3 GND1 3.3VAUX1 4
14 USB20_P6 USB_D+ 3.3VAUX2
USB20_N6 5 6
14 USB20_N6 USB_D- LED#1
7
GND2 NC 8
9 NC NC 10
B 11 NC NC 12 B
13 NC NC 14
15 16
17 NC LED#2 18
19 MLDIR_SENSE GND16 20
21 DP_ML3N DP_AUXN 22
23 DP_ML3P DP_AUXP 24
25 GND3 GND13 26
27 DP_ML2N DP_ML1N 28
29 DP_ML2P DP_ML1P 30
31 GND4 GND14 32
33 DP_HPD DP_ML0N 34
35 GND5 DP_ML0P 36
4 PCIE_CTX_C_DRX_P2
37 PETP0 GND15 38 R40 1 @ 2 100_0402_5%
4 PCIE_CTX_C_DRX_N2
39 PETN0 RESERVED1 40 R41 1 @ 2 100_0402_5%
41 GND6 RESERVED2 42
4 PCIE_CRX_DTX_P2
43 PERP0 RESERVED3 44
4 PCIE_CRX_DTX_N2
45 PERN0 COEX3 46
47 GND7 COEX2 48
12 PCIE_WLAN_CLK_P2
49 REFCLKP0 COEX1 50 PCICLK0 PCICLK0 12
12 PCIE_WLAN_CLK_N2
51 REFCLKN0 SUSCLK 52 PLT_RST# PLT_RST# 12,14,17,36,37
53 GND8 PERST0# 54 R93 1 2 100_0402_5% EC_RX EC_RX 38
14 CLKREQ_WLAN#
55 CLKREQ0# RESERVED/W_DISABLE#2 56 BTRF_OFF# BTRF_OFF# 12
38 WLAN_WAKE#
57 PEWAKE0# W_DISABLE#1 58
59 GND9 I2C_DATA 60 R95 1 2 1K_0402_1% BT_OFF#
BT_OFF# 12
61 PETP1 I2C_CLK 62
63 PETN1 I2C_ALERT# 64 EC_TX_R R92 1 2 100_0402_5% EC_TX
EC_TX 38
+3VALW R125 1 2 10K_0402_5% 65 GND10 RESERVED4 66
67 PERP1 PERST1# 68
+3V_WLAN R126 1 @ 2 10K_0402_5% 69 PERN1 CLKREQ1# 70
71 GND11 PEWAKE1# 72
73 REFCLKP1 3.3VAUX4 74 EC_TX_R
75 REFCLKN1 3.3VAUX5
GND12

1
76 77
PEG1 PEG2 R96
TE_2199230-8 100K_0402_5%
ME@

2
1. softstart (RC) will check on EVT PCB
2. if AOAC enable +3V_WLAN always ON
if AOAC disable +3V_WLAN is same as +3VS

+3VALW to +3V_WLAN
+3VALW +3V_WLAN
Q10
AO3413_SOT23-3
J4 @
3
S

1 +3VWLAN 1 2
1 2
A A
JUMP_43X79
G

1 1 1
2

C93 C94 C96

0.1U_0402_10V7-K .01U_0402_16V7-K 4.7U_0603_6.3V6-K
2@ 2@ 2@

R97
AOAC_ON# 2 1
38 AOAC_ON#
47K_0402_5%
1
C95
0.1U_0402_10V7-K
2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 NGFF TYPEA WLAN CARD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 33 of 65
2 1
 5 4 3 2 1

+3VS

+5VS LDO 1V8 VREF 1V65 LDO 3V3

1
CA1
+1.8V_LDO +1.65V_LDO +3V_LDO 0.1U_0402_10V7-K
C3505 close Pin7
RA1 1 2 0_0805_5%CA2 CA3 CA4 CA5 +5VS_CLASSD
CA6 CA7 CA8 CA9 CA10 CA11 2
@

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
1 1 1 1

0.1U_0402_10V7-K

4.7U_0603_6.3V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M
D 2 1 1 1 1 1 D

1U_0402_6.3V6-K
2 2 2 2
1 2 2 2 2 2
+3VS

RA28 1 2 0_0402_5% @ +3VS_VDDO

X5R CAP X5R CAP X5R CAP
1
CA12
0.1U_0402_10V7-K +3VL
Close to Pin13,16
2 CA12 close Pin2
+3VS RA3 1 2 0_0805_5%

@ +3VALW
2

RA29 +3V_AVDD_HP @
10K_0402_5% 12/3 For PH noise RA2 1 2 0_0805_5%

1
1

EC_MUTE#_R UA1
CA13
FCH_AZ_RST# 9 3 1U_0402_6.3V6-K
14 FCH_AZ_RST# RESET# FILT_1.8V +1.8V_LDO 2
7
VDD_IO 2
+3VS_VDDIO C3537 close Pin24
VDDO_3.3 +3VS_VDDO
FCH_AZ_BITCLK 5 18 +3VS_DVDD
14 FCH_AZ_BITCLK BIT_CLK DVDD_3.3
FCH_AZ_SYNC 8 27
14 FCH_AZ_SYNC SYNC AVDD_3.3 +3V_LDO
29 +1.65V_LDO
FCH_AZ_SDIN0 RA5 1 2 33_0402_5% FCH_AZ_SDIN0_R 6 VREF_1.65V 28 +3VS_DVDD +3VS
14 FCH_AZ_SDIN0 SDATA_IN AVDD_5V +5VS_AVDD
FCH_AZ_SDOUT 4 @
14 FCH_AZ_SDOUT SDATA_OUT RA4 1 2 0_0805_5%
C
35 PC_BEEP
PC_BEEP 10
PC_BEEP
CX20751-11Z LEFT+
12 SPK_L2+
SPK_L2+ 35
C
EC_MUTE#_R 39 14 SPK_L1-
38 EC_MUTE#_R SPKR_MUTE# LEFT- SPK_L1- 35 X5R CAP, Please Close Pin18
JSENSE 38 17 SPK_R2+
35 JSENSE JSENSE RIGHT+ SPK_R2+ 35
37 15 SPK_R1- 1
GPIO1/PORTC_R_MIC RIGHT- SPK_R1- 35
36 35 CA14
DMIC_CLK RA7 1 2 33_0402_5% DMIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34 1U_0402_6.3V6-K
26 DMIC_CLK DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB +MICBIASB 2
DMIC_DATA 1
26 DMIC_DATA DMIC_DAT/GPIO1 33 PORTB_R
PORTB_R_LINE PORTB_R 35
32 PORTB_L
PORTB_L_LINE PORTB_L 35
+5VS_CLASSD CA16 1 2 0.1U_0402_10V7-K 11
CLASS-D_REF 30 EXT_MIC_A
13 PORTD_A_MIC 31 EXT_MIC_B
EXT_MIC_A 35 Apple --> EXT_MIC_A, HGNDB
LPWR_5.0 PORTD_B_MIC EXT_MIC_B 35
W= 80mils 16
RPWR_5.0 25 HGNDA
Nokia --> EXT_MIC_B, HGNDA +5VS_AVDD +5VS
HGNDA HGNDA 35,41
CA17 1 2 1U_0402_6.3V6-K 19 26 HGNDB @
FLY_P HGNDB HGNDB 35,41
20 RA6 1 2 0_0805_5%
FLY_N 24
AVDD_HP +3V_AVDD_HP
+AVEE +AVEE 21
AVEE 23 HP_OUTR
PORTA_R HP_OUTR 35 1
41 22 HP_OUTL
HP indicate 1 GND PORTA_L HP_OUTL 35
CA15
CA18 Should be 1U_0402_6.3V6-K
2.2U_0402_6.3V6-M 2
2 connect to CX20751-11Z_QFN40_5X5
GNDA CX20751-21Z
SA00005ZT0J Please Close Pin28
GND
EMC_NS@
SPK_L2+ RA35 1 2
EMC_NS@ 100_0402_5% CA50 1 2 220P_0402_50V7-K

B EMC_NS@ B
SPK_L1- RA36 1 2
EMC_NS@ 100_0402_5% CA51 1 2 220P_0402_50V7-K

EMC_NS@
SPK_R2+ RA37 1 2
EMC_NS@ 100_0402_5% CA52 1 2 220P_0402_50V7-K
+3VS_VDDIO
EMC_NS@ RA25 1 @ 2 0_0402_5%
+3VS
SPK_R1- RA38 1 2
EMC_NS@ 100_0402_5% CA53 1 2 220P_0402_50V7-K
+3VALW RA27 1 2 0_0402_5% @

2
W= 300mils CA42
EMI, close to UA1 RF, close to RA7 EMC_NS@ 4.7U_0603_6.3V6-K
CA19 1 2 0.1U_0402_10V7-K 1

RA26 EMC_NS@
FCH_AZ_BITCLK_C 1 2 FCH_AZ_BITCLK
EMC_NS@ DMIC_CLK CA20 1 2 0.1U_0402_10V7-K
CA42 close Pin7
1 1
33_0402_5% EMC_NS@
CA40 CA41 CA21 1 2 0.1U_0402_10V7-K
22P_0402_50V8-J 150P_0402_50V8-J
2 EMC_NS@ 2 EMC@

GND GNDA
FCH_AZ_RST# FCH_AZ_SYNC FCH_AZ_SDOUT DMIC_DATA
1
1 1 1
CA43
CA37 CA38 CA39 47P_0402_50V8-J
22P_0402_50V8-J 22P_0402_50V8-J 22P_0402_50V8-J 2 EMC_NS@
2 EMC_NS@ 2 EMC_NS@ 2 EMC_NS@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 HDA-CX20751
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 34 of 65
5 4 3 2 1
 5 4 3 2 1

D
Speaker D

PC Beep
ME@
SPK_L1- RA8 1 2 BLM18PG221SN1D_2P
SPK_L1-_CON TYCO_2041180-4
34 SPK_L1- 6
SPK_L2+ RA9 1 2 BLM18PG221SN1D_2P
SPK_L2+_CON 5 GND2
34 SPK_L2+ GND1
SPK_R1- RA10 1 2 BLM18PG221SN1D_2P
SPK_R1-_CON SPK_L1-_CON 4
34 SPK_R1- SPK_L2+_CON 3 4
SPK_R2+ RA11 1 2 BLM18PG221SN1D_2P
SPK_R2+_CON SPK_R1-_CON 2 3
34 SPK_R2+ SPK_R2+_CON 1 2
DA3 1
EC Beep 2 JSPK
38 BEEP#
CA24
1 1 RA12 2 1 2
PC_BEEP 34
FCH Beep CA25 1 2 470P_0402_50V8-J SPK_L1-_CON
3 33_0402_5%
0.1U_0402_10V7-K
14 FCH_SPKR
CA26 1 2 470P_0402_50V8-J SPK_L2+_CON
BAT54CW_SOT323-3

1 CA27 1 2 470P_0402_50V8-J SPK_R1-_CON

RA13
10K_0402_5%
CA28 1 2 470P_0402_50V8-J SPK_R2+_CON
2

C C

Apple --> EXT_MIC_A, HGNDB

EXT. MIC/LINE IN Nokia --> EXT_MIC_B, HGNDA
+3VS

1
EXT_MIC_A RA14 1 2 100_0402_5% CA29 1 2 2.2U_0402_6.3V6-K HGNDB RA18
34 EXT_MIC_A HGNDB 34,41
5.11K_0402_1%

2
EXT_MIC_B RA15 1 2 100_0402_5% CA30 1 2 2.2U_0402_6.3V6-K HGNDA
34 EXT_MIC_B HGNDA 34,41 JSENSE 2 1
RA20 20K_0402_1%
34 JSENSE JSENSE_CON 41
B RA21 2 1 39.2K_0402_1% B
Changed CA29 & CA30 from 1uF to 2.2uF/X5R
to meet Port-D(headset-Mic) THD+N <= -65 dB

HeadPhone/LINE OUT
RA16 1 2 2.2K_0402_5% +MICBIASB

HP_OUTL RA17 1 2 47_0402_5% HP_OUTL_CON

34 HP_OUTL HP_OUTL_CON 41
CA31
1 RA19 2 1 2
34 PORTB_L PORTB_L
100_0402_5%
10U_0603_6.3V6-M

RA22 1 @ 2 2.2K_0402_5% +MICBIASB

HP_OUTR RA23 1 2 47_0402_5% HP_OUTR_CON

34 HP_OUTR HP_OUTR_CON 41
CA32
PORTB_R 1 RA24 2 1 2
34 PORTB_R
100_0402_5%
10U_0603_6.3V6-M
A A
CA31, CA32 change to 4.7U for Quality requirement

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 HDA-HP/EXT MIC/SPK CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 35 of 65
5 4 3 2 1
 1 2 3 4 5

Only for Edge 15''

JRJ452
9
+3VALW_LAN YellowLED+
+3VALW by Shape or Trace W=30mils +3VALW_LAN RL10
LAN_ACTIVITY# 1 2 LANLED_ACT# 10
370mA YellowLED-
RL1 1 2 0_0805_5% 510_0402_1% RJ45_MDO3- 8
PR4-
@ 1 RJ45_MDO3+ 7
PR4+
CL24 RJ45_MDO1- 6
220P_0402_50V7-K PR2-
2 EMC_NS@ RJ45_MDO2- 5
PR3-
RJ45_MDO2+ 4
PR3+
A RJ45_MDO1+ 3 A
PR2+ 14
+LAN_VDD RJ45_MDO0- 2 GND2
+3VALW_LAN PR1- 13
UL1 RJ45_MDO0+ 1 GND1
PR1+
3 11 11
AVDD10_1 AVDD33_1 +3VALW_LAN GreenLED+
8 32 close to UL1 : Pin 17,18 RL11
30 AVDD10_2 AVDD33_2 LANLINK_STATUS# 1 2 LANLED_LINK# 12
+3VS 22 AVDD10_3 17 PCIE_CRX_C_DTX_P0 CL18 1 2 0.1U_0402_10V7-K PCIE_CRX_DTX_P0 GreenLED- GND45A
DVDD10 HSOP PCIE_CRX_DTX_P0 4
18 PCIE_CRX_C_DTX_N0 CL19 1 2 0.1U_0402_10V7-K PCIE_CRX_DTX_N0 510_0402_1% FOX_JM3611-RS800013-7H
1 HSON PCIE_CRX_DTX_N0 4
LAN_MDI0+ 1 ME@
MDIP0
1

LAN_MDI0- 2 19 PLT_RST#
MDIN0 PERSTB PLT_RST# 12,14,17,33,37
RL2 CL25
10K_0402_5%
@
LAN_MDI1+
LAN_MDI1-
4
5 MDIP1 20 ISOLATEB RL7 1 @ 2 1K_0402_1%
+3VS
2
220P_0402_50V7-K
EMC_NS@
RJ-45 Connector
+3VALW_LAN

1
MDIN1 ISOLATEB 21 LAN_WAKE# LAN_WAKE# 14,38
2

LAN_CLKREQ# LAN_MDI2+ 6 LANWAKEB RL8

LAN_MDI2- 7 MDIP2 23 +LAN_VDDREG 1K_0402_1%
MDIN2 VDDREG 24 +LAN_SROUT1.05
LAN_MDI3+ 9 REGOUT

2
LAN_MDI3- 10 MDIP3 25 LANLINK_STATUS#
MDIN3 LED2 26 LED1 RL23 1 @ 2 LANMODE_STATUS ISOLATEB
LED1/GPO LANMODE_STATUS 13
PCIE_CTX_C_DRX_P0 13 27 LAN_ACTIVITY# 0_0402_5%
4 PCIE_CTX_C_DRX_P0 HSIP LED0
PCIE_CTX_C_DRX_N0 14
4 PCIE_CTX_C_DRX_N0 HSIN

1
LAN_CLKREQ# 12 28 XTLO RL9 TL1
14 LAN_CLKREQ# CLKREQB CKXTAL1 15K_0402_1%
PCIE_LAN_CLK_P0 15 29 XTLI LAN_MDI0- 1 1:1
12 PCIE_LAN_CLK_P0 16 REFCLK_P CKXTAL2 TD1+ T1/B 24
PCIE_LAN_CLK_N0 RJ45_MDO0-

2
12 PCIE_LAN_CLK_N0 REFCLK_N TX1+
31 33
RSET GND LAN_MDI0+ 2

1
TD1-
RL20 RTL8111GUS-CG_QFN32_4X4 23 RJ45_MDO0+
2.49K_0402_1% TX1-
+V_DAC 3 22 MCT1 RL16 1 2 75_0402_5% RJ45_GND
2 TDCT1 T1/A TXCT1

20130314 change to 7V25000014 and 12P cap 4 21 MCT2 RL17 1 2 75_0402_5%

TDCT2 1:1 TXCT2
LAN_MDI1- 5
TD2+ T1/B
20 RJ45_MDO1-
TX2+
For External Clock Source

+3VALW_LAN Rising time (10%~90%) >1mS and <100mS CL20

LAN_MDI1+ 6
TD2-
TX2-
19 RJ45_MDO1+

1 2 XTLI_R RL22 1 2 0_0402_5% @ XTLI

T1/A
B B
+3VALW_LAN +LAN_VDD +LAN_VDD 10P_0402_50V8-J YL1 LAN_MDI2- 7 1:1
0.1A TD3+ T1/B 18 RJ45_MDO2-
1 4 TX3+
CL6 CL7 CL8 CL11 CL12 OSC1 GND2
CL1 CL2 CL3 CL4 CL5 2 3 LAN_MDI2+ 8
GND1 OSC2 TD3-
4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1U_0402_10V6-K

0.1U_0402_10V7-K 17 RJ45_MDO2+
1 1 1 1 1 1 1 1 1 1 TX3-
@

25MHZ_10PF_7V25000014 9 16 MCT3 RL18 1 2 75_0402_5%

TDCT3 TXCT3
@

T1/A
2 2 2 2 2 2 2 2 2 2
CL21
10 15 MCT4 RL19 1 2 75_0402_5%
1 2 11 TDCT4 1:1 TXCT4
XTLO LAN_MDI3-
TD4+ T1/B
14 RJ45_MDO3-
TX4+
10P_0402_50V8-J
1
LAN_MDI3+ 12 CL27
TD4- 13 RJ45_MDO3+ 1000P_1206_2KV7-K
TX4- 2
These caps close to UL1 : Pin 11, 32 These caps close to UL1 : Pin 3, 8, 30 These caps close to UL1 : Pin 22 2
CL26 T1/A
.01U_0402_16V7-K
1 NA69RLF LAN
+3VALW_LAN

RL5 1 @ 2 0_0603_5%
RL4 1 2 CL13 CL14 +LAN_VDDREG CL22 1 2 .01U_0402_16V7-K
+LAN_VDD
4.7U_0603_6.3V6-K

0.1U_0402_10V7-K

@ 0_0603_5% 1 1 Test Point EMC@

LL1 CL23 1 2 0.1U_0402_10V7-K GND45A
+LAN_SROUT1.05 CL15 1 2 CL16 CL17 Test_Point_12MIL 1 TPL1 @ LANLINK_STATUS#
W=60mils 2.2UH_NLC252018T-2R2J-N_5% W=60mils EMC@
2 2
0.1U_0402_10V7-K

4.7U_0603_6.3V6-K

1 1
0.1U_0402_10V7-K

1
Test_Point_12MIL 1 TPL3 @ LAN_ACTIVITY#
These components close to U1 : Pin 24
@

GND45A
2 2
( Should be place within 200 mils )
2 EMI
DL1 DL3 EMC_NS@
LAN_MDI0- 6 1 LAN_MDI1- MCT1 2 1
V_I/O4 V_I/O1
5 2
+3VALW_LAN +3VALW_LAN VBUS Ground LSE-200NX3216TRLF_1206-2
LAN_MDI0+ 4 3 LAN_MDI1+
V_I/O3 V_I/O2
DL4 EMC_NS@
CL18 & RL2 resever to RTL8111G (LDO mode) RFC21 RFC22 CM1293A_SC-74 MCT2 2 1
C SC300003N00 C

2200P_0402_50V7-K
EMC@

47P_0402_50V8-J
2 1 LSE-200NX3216TRLF_1206-2

DL2 DL5 EMC_NS@

RF@
RF_NS@ LAN_MDI2- 6 1 LAN_MDI3- MCT3 2 1
1 2 V_I/O4 V_I/O1
5 2
+3VALW_LAN VBUS Ground LSE-200NX3216TRLF_1206-2
LAN_MDI2+ 4 3 LAN_MDI3+
V_I/O3 V_I/O2
DL6 EMC_NS@
For RF CM1293A_SC-74 MCT4 2 1
SC300003N00
EMC@
LSE-200NX3216TRLF_1206-2

GND45A
Reserve for Surge

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 LAN/RJ45 CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 36 of 65
1 2 3 4 5
 5 4 3 2 1

DV12 +DV33_18 AV12

20 mils 20 mils 20 mils
40 mils
CW1 CW2 CW3 CW4
+3VS RW1 1 2 +3VS_CARD

4.7U_0603_6.3V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
1 1 1 1

1U_0402_10V6-K
@ 0_0603_5%

2 2 2 2

D D

UW1

+3VS_CARD 11 30 SD_CD#
3V3_IN SD_CD#
All of cap. close to chip
+DV33_18 18 31
DV33_18 MS_INS#
AV12 10 32 RW20 2 1 10K_0402_5% +3VS_CARD
@ AV12 WAKE#
+3VS_CARD +3V3_AUX RW3 1 2 0_0603_5% DV12 14
DV12S
40 mils 40 mils
DV12 connects with AV12, due
CW5 CW6 CW7 CW8 to DV12 need a external input. 15 SD_DATA1
SP1
For EMI, please close to the chip
10U_0603_6.3V6-M

0.1U_0402_10V7-K

0.1U_0402_10V7-K

4.7U_0603_6.3V6-K
1 1 1 1 12 16 SD_DATA0_MS_DATA1
+CRD_POWER Card_3V3 SP2 EMC_NS@ EMC_NS@
17 SD_CLK_MS_DATA0_R RW6 1 2 0_0402_5% SD_CLK_MS_DATA0 CW11 1 2 5P_0402_50V9-C
RW18 1 2 @ +3V3_AUX 27 SP3
2 2 2 2 +3VS_CARD 3V3aux 19 SD_CMD_MS_DATA2 Close to chip
0_0402_5%
375mA SP4
RW8 1 2 6.2K_0402_1% 9 20 SD_MS_DATA3
Close to chip 12mils, lengths < 200milsRREF SP5
21 SD_DATA2_MS_CLK
SP6
PCIE_CTX_C_DRX_P1 3 29 SD_WP
4 PCIE_CTX_C_DRX_P1 HSIP SP7
Close to pin 11 Close to pin 27
PCIE_CTX_C_DRX_N1 4
4 PCIE_CTX_C_DRX_N1 HSIN
CW9 1 2 0.1U_0402_10V7-K PCIE_CRX_C_DTX_P1 7
4 PCIE_CRX_DTX_P1 HSOP
CW10 1 2 0.1U_0402_10V7-K PCIE_CRX_C_DTX_N1 8 13
4 PCIE_CRX_DTX_N1 HSON NC_1
22
NC_2
C C
PCIE_CARDREAD_CLK_P1 5 23
12 PCIE_CARDREAD_CLK_P1 REFCLKP NC_3
PCIE_CARDREAD_CLK_N1 6 24
12 PCIE_CARDREAD_CLK_N1 REFCLKN NC_4
25
NC_5
PLT_RST# 1 26
12,14,17,33,36 PLT_RST# PERST# NC_6

CARD_CLKREQ# 2
14 CARD_CLKREQ# CLK_REQ#

+3VS_CARD RW11 1 2 10K_0402_5% 28 33 GND

GPIO GND

RTS5227E-GR_QFN32_4X4

Only for Edge 15''

+CRD_POWER
+3VS
40 mils JREAD2 +3VS

SD_CMD_MS_DATA2 2
CMD

1
3 @
VSS1

1
4 @ RW12
SD_CLK_MS_DATA0 5 VDD RW13 100K_0402_5%
6 CLK 100K_0402_5%
VSS2
10U_0603_6.3V6-M
0.1U_0402_10V7-K

2
1 1 SD_DATA0_MS_DATA1 7

2
SD_DATA1 8 DAT0
CW13

SD_DATA2_MS_CLK 9 DAT1 SD_CD#_R RW14 1 2 SD_CD# @ SD_WP_R RW15 1 2 SD_WP @

CW12

SD_MS_DATA3 1 DAT2
B B
2 2 CD/DAT3 0_0402_5% 0_0402_5%

SD_WP_R 10
SD_CD#_R 11 W/P
12 C/D
13 GND1
GND2
Close to JREAD1.
SUYIN_250312HB011M106ZL
ME@

EMC_NS@
SD_CLK_MS_DATA0 RW16 1 EMC_NS@
2 10_0402_5% CW14 1 2 10P_0402_50V8-J

RW16 and CW14reserved for EMI.

Please close to conn.

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Card Reader
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 37 of 65
5 4 3 2 1
 5 4 3 2 1

+3VS +3VL +3VL Vcc 3.3V +/- 5%

+3VL +3VL_AVCC All capacitors close to EC RE33 100K +/- 1%
LE1
1 2 +3VL_AVCC +3VL CE3 CE4 CE5 CE6 CE7 CE8 Board ID RE34 VAD_BID min V AD_BID typ VAD_BID max Phase

1
0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
BLM18PG121SN1D_2P RE33
100K_0402_5%
0 0K +/- 5% 0 V 0 V 0 V SDV
1 1 2 2 2 2 2 2
CE9 CE10 Close to EC 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V

2
1000P_0402_50V7-K CE2 +3VL_AVCC
2
0.1U_0402_10V7-K
2 2 1 +VCOREVCC 1 1 1 1 @1 @1 Board_ID
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
LE2
3 33K +/- 5% 0.712 V 0.819 V 0.875 V

1
EC_AGND 1 2 0.1U_0402_10V7-K
RE34
BLM18PG121SN1D_2P 18K_0402_1%
4 4.7K +/- 5% 0.141 V 0.148 V 0.155 V

114
121
127
5 24K +/- 5% 0.612 V 0.638 V 0.664 V

12

11

26
50
92

74
D
minimum trace width 12 mil D

3
UE1

2
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC
VBAT

VSTBY(PLL)
VCORE
+3VALW
KBRST# 4 24 LOGO_LED# S5_1.1_EN
14 KBRST# 5 KBRST#/GPB6 PWM0/GPA0 25 LOGO_LED# 26,41
SERIRQ AOU_DET#
12 SERIRQ 6 SERIRQ/GPM6 PWM1/GPA1 28 AOU_DET# 30
LPC_FRAME# CP_RESET#
12 LPC_FRAME# LFRAME#/GPM5 PWM2/GPA2 CP_RESET# 42

1
RE32 1 2 100K_0402_5% HDD_DETECT# LPC_AD3 7 29 VGA_AC_BATT
12 LPC_AD3 8 LAD3/GPM3 PWM3/GPA3 30 VGA_AC_BATT 18 +5VS
LPC_AD2 PWM GS_SELFTEST RE15
12 LPC_AD2 9 LAD2/GPM2 PWM4/GPA4 31 GS_SELFTEST 40
LPC_AD1 EC_FAN_PWM 100K_0402_5%
12 LPC_AD1 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM 42 1 2
LPC_AD0 BEEP# @ CP_CLK RE16 4.7K_0402_5%
+3VL 12 LPC_AD0 13 LAD0/GPM0 PWM6/SSCK/GPA6 34 BEEP# 35 1 2
CLK_PCI_EC LPC S5_1.1_EN CP_DATA RE17 4.7K_0402_5%
12 CLK_PCI_EC S5_1.1_EN 54

2
WRST# 14 LPCCLK/GPM4 PWM7/RIG1#/GPA7 120
GPU_VR_HOT# 15 WRST# TMRI0/GPC4 124 SUSP#
1 RE1 2 18,59 GPU_VR_HOT# 16 ECSMI#/GPD4 TMRI1/GPC6 SUSP# 43,52,56,59
WRST# EC_RX
33 EC_RX 17 PWUREQ#/BBO/SMCLK2ALT/GPC7 66
1 EC_TX +3VALW
100K_0402_5% 33 EC_TX 22 LPCPD#/GPE6 ADC0/GPI0 67
EC_A_RST# GS_VOUTY GS_VOUTY 40
12 EC_A_RST# 23 LPCRST#/GPD2 ADC1/GPI1 68
CE1 EC_SCI# BATT_TEMP BATT_TEMP 49,50 RE19 @ RP1
14 EC_SCI# 126 ECSCI#/GPD3 ADC2/GPI2 69 1 2 1 8
1U_0402_10V6-K GATEA20 ADC Board_ID EC_ON S5_1.1_EN FAN_ID +3VS
2 14 GATEA20 GA20/GPB5 ADC3/GPI3 70 2 7
FAN_ID AOU_DET#
IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
ADP_I
GS_VOUTX
FAN_ID
ADP_I
GS_VOUTX
50
42

40
0_0402_5%
EC_FAN_SPEED
3
4
6
5

39 KSI[0..7]
KSI[0..7] KSI0 58
KSI0/STB#
LQFP-128L ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 ADP_ID ADP_ID 48
10K_0804_8P4R_5%
KSI1 59 78 IMVPPOK IMVPPOK 57
KSO[0..17] KSI2 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 MAINPWON +3VS
39 KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 MAINPWON 48,49,51
KSI3 61 DAC 80 H_PROCHOT_EC
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 APU_ENBKL EC_FAN_PWM RE18 1 @ 2 10K_0402_5%
KSI4 DAC5/RIG0#/GPJ5 APU_ENBKL 7
KSI5 63
KSI6 64 KSI5 85 AOU_EN
65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 AOU_EN 30
KSI7 PBTN_OUT#
36 KSI7 PS2DAT0/TMB1/GPF1 87 PBTN_OUT# 14
KSO0 HDD_DETECT# HDD_DETECT# 31
KSO1 37 KSO0/PD0 GPF2 88 TP4RST
+3VALW KSO1/PD1 Int. K/B PS2 GPF3 TP4RST 42
KSO2 38 89 CP_CLK
C
KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 CP_DATA
CP_CLK 42 C

40 KSO3/PD3 PS2DAT2/GPF5 CP_DATA 42

KSO4
KSO5 41 KSO4/PD4 96 BYPASS_PAD_R
KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3 BYPASS_PAD_R 42
KSO6 42 97 APUPWR_EN
1 2 43 KSO6/PD6 GPH4/ID4 98 APUPWR_EN 53,57 +3VL
RE6 10K_0402_5% KB_FN KSO7 ACOFF ACOFF 50
KSO8 44 KSO7/PD7 GPH5/ID5 99 FCH_PWROK
45 KSO8/ACK# GPH6/ID6 FCH_PWROK 14 1 2
KSO9 LID_SW# RE20 10K_0402_5%
KSO10 46 KSO9/BUSY 101 EC_SPI_FSCE#
51 KSO10/PE NC1 102 EC_SPI_FSCE# 13
KSO11 EC_SPI_FMOSI
52 KSO11/ERR# NC2 103 EC_SPI_FMOSI 13 +3VALW
KSO12 SPI Flash ROM EC_SPI_FMISO
+3VS 53 KSO12/SLCT NC3 105 EC_SPI_FMISO 13
KSO13 EC_SPI_FSCK
54 KSO13 NC4 EC_SPI_FSCK 13
KSO14
RE7 1 @ 2 2.2K_0402_5% EC_SMB_CK3 KSO15 55 KSO14 LAN_WAKE# RE21 1 2 10K_0402_5%
RE8 1 @ 2 2.2K_0402_5% EC_SMB_DA3 KSO16 56 KSO15 108 ACPRN
RE9 1 2 10K_0402_5% LPC_FRAME# KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW# LAN_WAKE# RE38 1 @ 2 10K_0402_5%
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 32
AOAC_ON# RE22 1 2 100K_0402_5%

ON/OFFBTN# 110 82 EC_GS_ON#

32 ON/OFFBTN# PWRSW# EGAD/GPE1 EC_GS_ON# 40
111 SM Bus 83 EC_ON EC_ON 51
EC_RSMRST# EC_SMB_CK1 115 XLP_OUT EGCS#/GPE2 84 AOU_CTL1
49,50 EC_SMB_CK1 SMCLK1/GPC1 EGCLK/GPE3 AOU_CTL1 30
EC_SMB_DA1 116
49,50 EC_SMB_DA1 117 SMDAT1/GPC2 77
VDDAPWROK GPIO PM_SLP_S5# PM_SLP_S5# 14
56,57 VDDAPWROK SMCLK2/PECI/GPF6 GPJ1
1

ADAPTER_ID_ON# 118 100

48 ADAPTER_ID_ON# SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2
RE11 EC_SMB_CK3 94 106 EC_MUTE# SCS00006S00 D6 1 2 RB751V-40_SOD323-2
7,18,29 EC_SMB_CK3 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 EC_MUTE#_R 34
@ 100K_0402_5% EC_SMB_DA3 95 104
7,18,29 EC_SMB_DA3 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 +3VL
SYSON
DTR1#/SBUSY/GPG1/ID7 119 SYSON 52
EC_BKOFF#
EC_BKOFF# 26
2

CRX0/GPC0 123 AOAC_ON#

112 CTX0/TMA0/GPB2 18 AOAC_ON# 33 1 2
+3VL PM_SLP_S3# PM_SLP_S3# 14 EC_MUTE# RE23 10K_0402_5%
LAN_WAKE# 125 VSTBY0 RI1#/GPD0 21
14,36 LAN_WAKE# GPE4 RI2#/GPD1 76 1 2
WAKE UP RE24 @ 100K_0402_5%
+3VALW TACH2/GPJ0 48 AOU_CTL3
TACH1A/TMA1/GPD7 AOU_CTL3 30
47 EC_FAN_SPEED
TACH0A/GPD6 EC_FAN_SPEED 42
RP2 USB_ON# 33 19 WLAN_WAKE#
+5VALW 1 8 KSO1
30,32
12
USB_ON#
FCH_S5 FCH_S5 35 GINT/CTS0#/GPD5
GPIO
L80HLAT/BAO/GPE0 20 KB_FN
WLAN_WAKE#
KB_FN 39
33 1. Version CX : Don't Support Mirror Code
RTS1#/GPE5 L80LLAT/GPE7
2
3
7
6
KSO2
14 EC_RSMRST#
EC_RSMRST# 93
CLKRUN#/GPH0/ID0 Version DX/EX : Support Mirror Code
B
4 5 USB_ON# Please don't place any PU Resistor on GPG[7:2] 2. For Mirror Code B

2
10K_0804_8P4R_5%
14,18 EC_WAKE#
EC_WAKE#
AC_PRESENT 128 CK32KE/GPJ7 (Reserve hardware strapping) "H" --> Enable
Clock
14 AC_PRESENT CK32K/GPJ6 "L" --> Disable (Default)
+3VL
+3VS *
+3VL RP3

2
AVSS

1 8 EC_SMB_CK3
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

2 7 EC_SMB_DA3 RE12 AC IN
3 6 EC_SMB_DA1 10K_0402_5%
4 5 EC_SMB_CK1 IT8586E-AX_LQFP128_14X14 +3VL
1

27
49
91
113
122

75

SA00005W940

1
2.2K_0804_8P4R_5% ACPRN RE25 1 2 10K_0402_5%
EC_ON RE26 1 2 0_0402_5% @ PACIN 50
EC_AGND SCS00006S00
DE1 @ 2 1 RB751V-40_SOD323-2

2
RE14
10K_0402_5% CE14 1 2 100P_0402_50V8-J
@
PROCHOT#

1
(EC asserts PROCHOT# signal by driving high,
the level shifter must invert it and drive the processor side PROCHOT# low.)
SYSON, SUSP#

RE27 1 2 0_0402_5% @ H_PROCHOT# H_PROCHOT# 7 @

50,57 VR_HOT# SUSP# RE29 1 2 100K_0402_5%

要要要EC的ADC pin
1

D
1
H_PROCHOT_EC 2
BATT_TEMP G CE15
QE1 S 47P_0402_50V8-J @
3

2N7002KW_SOT323-3 2 SYSON RE30 1 2 100K_0402_5%

A
@
For ESD SB00000YY00
A

CE11 1 2 220P_0402_50V7-K EC_A_RST# CE16 2 1 0.1U_0402_10V7-K

For EMI For EMC @

@ RE31
CE12 1 2 10P_0402_50V8-J 1 @ 2 CLK_PCI_EC

10_0402_5%

CE13 2 1 100P_0402_50V8-J BATT_TEMP Title

Security Classification LC Future Center Secret Data
Issued Date 2012/12/05 Deciphered Date 2014/12/05 EC_IT8586E/FX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
NM-A241 0.2

Date: Friday, June 13, 2014 Sheet 38 of 65

5 4 3 2 1
 A B C D E

KeyBoard CONN.(14")
1 1

KSI[0..7] KSI[0..7] 38
KSO[0..17]
KSO[0..17] 38

JKB
KSI1 32 34
KSI7 31 32 GND2 33
KSI6 30 31 GND1
KSO9 29 30
KSI4 28 29
KSI5 27 28
KSO0 26 27
KSI2 25 26
KSI3 24 25
KSO5 23 24
KSO1 22 23
KSI0 21 22
KSO2 20 21
KSO4 19 20
KSO7 18 19
KSO8 17 18
KSO6 16 17
KSO3 15 16
KSO12 14 15
KSO13 13 14
KSO14 12 13
KSO11 11 12
KSO10 10 11
2
KSO15 9 10 2
R39 1 2 300_0402_5% 8 9
+3VS 8
FN_LED# 7
14 FN_LED# 7
F1_LED# 6
14 F1_LED# 6
F4_LED# 5
13 F4_LED# 5
KB_FN 4
38 KB_FN 4
3
KSO16 2 3
KSO17 1 2
1
JAE_FL10S032HA1
ME@

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 KB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 39 of 65
A B C D E
 5 4 3 2 1

D D

APS G-Sensor

+3VALW +3VS_GS

W=40 mils RG6 1 @ 2 0_0402_5%

QG1
AO3413_SOT23-3

D
3 1

1 2
CG3

G
2
CG1 .01U_0402_16V7-K
0.1U_0402_10V7-K @
2@ 1

RG5
1 2
38 EC_GS_ON#
1
100K_0402_5%
CG2
.01U_0402_16V7-K
2

C C

RG7 1 2 100K_0402_5% UGSEN1

GS_SELFTEST 2 12 VOUTX RG8 1 2 56K_0402_5% GS_VOUTX

+3VS_GS 38 GS_SELFTEST ST VoutX GS_VOUTX 38
10 VOUTY RG9 1 2 56K_0402_5% GS_VOUTY
VoutY GS_VOUTY 38
8
VoutZ
1 1 1 1
14
15 VDD_1 CG7 CG8 CG9 CG10
VDD_2 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K
1 1 2 2 2 2
1
CG5 CG6 NC1 4
10U_0603_6.3V6-M 0.1U_0402_10V7-K 3 NC2 9
2 2 5 GND1 NC3 11
6 GND2 NC4 13
7 GND3 NC5 16 APS_GND
GND4 NC6

LIS34ALTR_LGA16_4X4
APS_GND SA000037F0J

JAPS @
1 2
1 2
JUMP_43X39

B APS_GND B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 APS G-SENSOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 40 of 65
5 4 3 2 1
 A B C D E F G H

1 1

2 2

+3VALW

2
R130
1K_0402_1%
Only for Edge 15"

1
JAUF
C_COVER_LOGO 12 14
LOGO_LED# 11 12 GND2 13
26,38 LOGO_LED# 11 GND1
10
JSENSE_CON 9 10
35 JSENSE_CON 9
HP_OUTR_CON 8
35 HP_OUTR_CON 8
3 HP_OUTL_CON 7 3
35 HP_OUTL_CON 7
HGNDA 6
34,35 HGNDA 6
5
4 5
HGNDB 3 4
34,35 HGNDB 3
2
1 2
1
ACES_50506-01201-001
ME@
GNDA
FFC

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 Sub-board/Power Button
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 41 of 65
A B C D E F G H
 1 2 3 4 5

+3VS

R43 1 2 2.2K_0402_5% FCH_SMB1CLK_R

Click Pad R44 1 2 2.2K_0402_5% FCH_SMB1DATA_R

Track point
+5VS

R100 1 2 0_0603_5% Only for Edge 15''

@ JTP
A TP_DATA2 1 A
JCP TP_RESET 2 1
1 3 2
FCH_SMB1CLK_R 2 1 4 3
14 FCH_SMB1CLK_R 2 4
3 +5VS 5
TP_DATA2 4 3 TP_CLK2 6 5
TP_CLK2 5 4 7 6
FCH_SMB1DATA_R 6 5 8 7
14 FCH_SMB1DATA_R 6 8
7 1 9
CP_RESET# 8 7 10 9
38 CP_RESET# 8 10
CP_CLK 9 C131 11 13
38 CP_CLK 9 11 GND1
CP_DATA 10 0.1U_0402_10V7-K 12 14
38 CP_DATA 10 2 EMC_NS@ 12 GND2
TP4RST 11 13
38 TP4RST 11 GND1
BYPASS_PAD 12 14
12 GND2 JAE_FL10S012HA1
1 1
C129 C130 ACES_51522-01201-001 ME@
100P_0402_50V8-J 100P_0402_50V8-J ME@
EMC_NS@ EMC_NS@
2 2
FFC
+5VS TP4RST R106 1 2 0_0402_5% @ TP_RESET

2
R11
R101 1 2 4.7K_0402_5% TP_CLK2 0_0402_5%
@
R102 1 2 4.7K_0402_5% TP_DATA2

1
R103 1 2 4.7K_0402_5% TP_RESET R107 1 2 0_0402_5% @ BYPASS_PAD
38 BYPASS_PAD_R

B B
R104 1 2 100K_0402_5% CP_RESET# CP_CLK TP_CLK2
CP_DATA TP_DATA2

2
D23 D24
PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3
R105 1 @ 2 4.7K_0402_5% BYPASS_PAD EMC_NS@ EMC_NS@

1
+VCC_FAN

RFC23 RFC24

FAN FingerPrint
2200P_0402_50V7-K

C C
47P_0402_50V8-J

2 1

+VCC_FAN
Only for Edge 15''
RF@

RF_NS@
1 2

1 2 0_0603_5%
40mil
+5VS R110
1
@ For RF
C134
1U_0402_10V6-K
Only for Edge 15''
2@

JFAN
1
38 EC_FAN_PWM 1
2
3 2
38 EC_FAN_SPEED 3
4 6
5 4 G1 7
38 FAN_ID 5 G2
1
C135
ACES_85205-05001
ME@
FFC
1000P_0402_50V7-K
EMC_NS@
2

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 CP/TP/FAN/FP CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 42 of 65
1 2 3 4 5
 1 2 3 4 5

+VDDIO to +VDDIO_RUN For DisCharge

+5VS +1.35V_APU_VDDIO +1.35V_APU_VDDIO_RUN +5VALW +0.675VS

Q13

1
A AO4354 1N A
8 1 R116 R117
7 2 J6 @ 100K_0402_5% 22_0805_5%

1
+5VALW 6 3 1 2 @
R112 5 1 2

2
100K_0402_5% JUMP_43X79
1

4
C138 SUSP

2
1 0.1U_0402_10V7-K

1
R119 2 D D
100K_0402_5% R113 SUSP# 2 2 SUSP
38,43,52,56,59 SUSP#
0_0402_5% G G
Q11 S S Q14
2

3
2N7002KW_SOT323-3 2N7002KW_SOT323-3

1
+1.35V_IORUN_GATE SB00000YY00 SB00000YY00
@

1
D
1
2 Q15 C137
G 2N7002KW_SOT323-3 .01U_0402_16V7-K
S SB00000YY00

3
2
1

D
SUSP# 2 Q16
G 2N7002KW_SOT323-3
S SB00000YY00
3

B +5VALW To +5VS B

+3VALW To +3VS +1.1VALW to +1.1VS

+3VALW +3VS +1.1VALW
VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm VIN 1.1V (VBIAS=5V), IMAX=6A, Rds=15mohm
U13 J7 @ U14
1 14 +3VS_LS 1 2 1 5
2 VIN1_1 VOUT1_2 13 1 2 VIN1 GND +1.1VS
VIN1_2 VOUT1_1 C142 220P_0402_50V7-K JUMP_43X118 2 6 C149 1 2 1000P_0402_50V7-K
1 1 1 VIN2 CT
3VSON 3 12 1 2 +5VALW J13 @
C140 ON1 CT1 C144 C148 11PWRON_R 3 7 +11VS_LS 1 2
1U_0402_6.3V6-K 4 11 0.1U_0402_10V7-K 1U_0402_6.3V6-K ON VOUT1 1 2
2@ +5VALW VBIAS GND 2@ 2@
C143 100P_0402_50V8-J 4 8 JUMP_43X118 1
+5VALW 5VSON 5 10 1 2 +5VS VBIAS VOUT2
ON2 CT2 9 C150
1 THERMALPAD
6 9 J8 @ 0.1U_0402_10V7-K
7 VIN2_1 VOUT2_2 8 +5VS_LS 1 2 C151 2@
VIN2_2 VOUT2_1 1 2 0.1U_0402_10V7-K
15 JUMP_43X118 2
1 GPAD 1 TPS22965DSGR_WSON8_2X2
C141 TPS22966DPUR_WSON14_2X3 C145
1U_0402_6.3V6-K 0.1U_0402_10V7-K
2@ 2@
SCS00006S00
+5VS, C143 --> 1.5ms D5
RB751V-40_SOD323-2
1 2
+3VS, C142 --> 2.5ms
R118
SUSP# 2 1 11PWRON_R
38,43,52,56,59 SUSP#
C C
47K_0402_5% 1
+0.95VS +0.95VS_VDDP C152
R114 J9 @ 0.1U_0402_10V7-K
1 2 3VSON 1 2 2
1 2
100_0402_5% JUMP_43X118
+1.35V_DDR_VDDIOSUS +1.35V_APU_VDDIO
+3VS
1
C146 +0.95VS +0.95VS_VDDR
1U_0402_6.3V6-K J10 @ C35 1 2 0.1U_0402_10V7-K

1
1 2
2 1 2 R120
JUMP_43X118 C36 1 2 0.1U_0402_10V7-K 220_0402_5%

2
R115 +1.8VS +1.8VS_VDDA C37 1 2 0.1U_0402_10V7-K
SUSP# 1 2 5VSON J11 @
1 2
33_0402_5% 1 2 C38 1 2 0.1U_0402_10V7-K
JUMP_43X118

1
D
1
C147 C39 1 2 0.1U_0402_10V7-K 2 SUSP
1U_0402_6.3V6-K +1.35V_DDR_VDDIOSUS +1.35V_APU_VDDIO G
J12 @ S Q17

3
2 1 2 C40 1 2 0.1U_0402_10V7-K 2N7002KW_SOT323-3
1 2 SB00000YY00
JUMP_43X118

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 3VS/5VS/1.1VS/VDDIO_RUN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 43 of 65
1 2 3 4 5
 1 2 3 4 5

SMBus block diagram

+3VS +3VS
A A

FCH SMB0 QH3

DDR3L DDR3L Click Security
SO-DIMM1 SO-DIMM2 Pad ROM
1001 000Xb 1001 010Xb
+3VL
+3VALW +3VS
EC SMB1
SMB1 QH1
Smart Power
Thermal EC Battery Controller
sensor
1001_101xb
B
SMB2 B
+3VALW +3VS

SMB2 QH2
+3VS +3VALW

SMB3 QH1
Thermal FCH
sensor
+1.35VS_APU_VDDIO +3VS

SCL3_LV QC6
SDA3_LV QC7 +3VS_VGA
reserve APU EC
SIC QV2
SID

C GPU C

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 SMBUS Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 44 of 65
1 2 3 4 5
 1 2 3 4 5

RTC
B+
+3VL/VL
A A

ACPRN
EC_ON
+5VALW
+3VALW
+1.1VALW
EC_RSMRST# 10ms
PBTN_OUT#
PM_SLP_S5#
B PM_SLP_S3# B

SYSON
SUSP#
+1.35V
+5VS
+3VS
VDDA
+1.5VS
VDDAPGOOD
C C

IMVP_IMON
+0.95VS
+VDDNB_CORE
+VCC_CORE
IMVPPOK
FCH_PWROK
APU_PWROK 98ms
PLT_RST#

D
APU_RESET# D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Power Sequence
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 45 of 65
1 2 3 4 5
 1 2 3 4 5

Only for Edge 15" SCREW LOCATION

A A

H20
PAD_C6P0D2P3 H8
PAD_C6P0D2P3

1
@

1
H6
H19 PAD_C6P0D3P3
PAD_shapeT6P0X8P5CB6P0D2P3

1
@ H18
1

PAD_C6P0D3P3

H5 H7
@ PAD_C6P0D3P3 PAD_C6P0D3P3
1

H21 @ @

1
PAD_C6P0D3P3
H9
PAD_C6P0D2P3
@ H22

1
PAD_shapeT6P0X8P5CB6P0D2P3
@

1
@ H1 H2

1
PAD_C6P0D3P3 PAD_C6P0D3P3

H17 @ @

1
PAD_C6P0D2P3
B B

@ H3 H4
1

PAD_C6P0D3P3 PAD_C6P0D3P3

@ @ H10

1
PAD_C6P0D2P3

H23
PAD_C6P0D2P3 @

1
H16
PAD_C6P0D2P3 @

1
@
1

H11
PAD_C6P0D2P3
H24
H15 PAD_C6P0D2P3
PAD_C6P0D2P3 @

1
@
1

@
1

H25
PAD_C6P0D2P3 H14 H13 H12
PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3

@
1

C @ @ @ C
1

1
H26
PAD_O2P3X2P8D2P3X2P8N

@
1

H27
PAD_shapeT6P0X8P5CB6P0D2P3

@
1

PCB Fedical Mark PAD

FD1 FD2 FD3 FD4 FD5 FD6

H29

1
PAD_C6P0D2P3

@
1

H30
PAD_C2P3D2P3N
D D
@
1

H31
PAD_C3P5D2P3

@ Title
Security Classification LC Future Center Secret Data
1

Issued Date 2012/07/01 Deciphered Date 2014/07/01 SCREW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 46 of 65
1 2 3 4 5
 5 4 3 2 1

POWER MAP

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Power MAP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 47 of 65
5 4 3 2 1
 5 4 3 2 1

0528@bob PD1
RB751V-40
PR2 PR3 1 2
PD2
100K_0402_1% 10K_0402_1% VIN
2 1 1 2 1 2
@ 38,49,51 MAINPWON
+3VALW 1 2
B+

RB751V-40
1SS355
VIN
PD3

1
D RB751V-40 D

3
E
PD21
PR296 2
B MMBT3906_SOT23-3

2
750_0402_1% PQ1
C
0102@Bob PR271 PR4

1
1M_0402_5% 750K_0402_5%

1
1
2N7002KDWH_SOT363-6
C
2 PQ2 2

6
D MMBT3904_SOT23-3 B +VDD_CORE +VDDNB_CORE 1.35VS

PQ47A
@ PR270 2 ADAPTER_ID_ON E

3
0_0402_5% G
1 2 2 1 2 1 2 1

2N7002KDWH_SOT363-6
S

1
PR7
1

3
10K_0402_1% PR272 D PRT1 PRT2 PRT3

PQ47B
1 2 1M_0402_5% 5 PC7 540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30%
ADP_ID 38 ADAPTER_ID_ON# 38

1
G 1U_0603_25V7K
A/D S PRT4

4
1
3VALW 540_0402NEW_30%

1
1

2
PC1 PC2
0.1U_0402_6.3V7-K PD19 DIS@
2

680P_0402_50V7-K

AZ5425-01F_DFN1006P2E2

2
2 1 2 1 2 1

2
PRT7 PRT6 PRT5
540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30%

VGA Charger 5VALW

C C

PRT7A

PL1
BLM18KG300TN1D
For 15 inch APDIN EMC@ 0_0402_5%
1 2
JDCIN
VIN UMA@

PL16
1 EMC@ BLM18KG300TN1D
1 2 APDIN 1 PF1 2 APDIN1 1 2
2 3
3 4 7A_32V_0437007.WR
4 5
8 5 6 EMC@
9 GND1 6 7 EMC@ EMC@ PC6
GND2 7 EMC@
1

1
PC3 PC4 1000P_0402_50V7-K
@ ACES_50271-00701-001 1000P_0402_50V7-K 100P_0402_50V8-J PC5
100P_0402_50V8J Thermal protect
2

2
PRT1 place to closed PQ21 with PU8
PRT2 place to closed PQ20 with PU8
PRT3 place to closed PQ18 with PU7
PRT4 place to closed PQ42 with PU15
B B
PRT5 place to closed PQ26 with PU14
PRT6 place to closed PQ29 with PU14
PRT7 place to closed PQ24 with PU9

RTCVREF
+RTCVCC +CHGRTC
PR14 PR15
PD8
@ 560_0603_5% @ 560_0603_5% 3.3V
1 2 1 2 1 2

@ RB751V-40
1

PC13
PD9
@ 10U_0603_6.3V6M
2

1 2
+3VLP
RB751V-40

A
RTC Battery A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/01 Deciphered Date 2014/08/01 DCIN / Vin Detector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 48 of 65
5 4 3 2 1
 5 4 3 2 1

PL2 EMC@
BLM18KG300TN1D PRT9 under CPU botten side :
VMB2 VMB
PF2 1 2 CPU thermal protection at 104 +-3 degree C
JBATT2 12A_32V_0501012.WRS
1 2 1 1 2 Recovery at 78 +-3 degree C
1 2 BATT+
2 3 EC_SMCA PL17
3
4
4
5
EC_SMDA BLM18KG300TN1D +3VLP +3VALW
5 EMC@ EMC@ EMC@

2
D 6 D
6 7 PC14 PC15 VL
7 8 1000P_0402_50V7-K 0.01U_0402_25V7-K

1
G1

3
9
G2

1
10 PD10
G3 1

1
11 PR19 PR20 PR29
G4 @ PC16 21K_0402_1% @ 12.7K_0402_1% @ 47K_0402_1%

PESD5V0U2BT_SOT23-3
PR22 0.1U_0603_16V7K

2
100_0402_1%

2
@ SUYIN_200082GR007M211ZR PR21
2

2
100_0402_1% PU2
1 8 NTC_V_1
VCC TMSNS1
PR33 2 7 OTP_N_002 2 1
@ 0_0402_5% GND RHYST1
EC_SMB_CK1 38,50 1 2 3 6
OTP_N_003 PR23
OT1 TMSNS2

1
38,48,51 MAINPWON 20K_0402_1%
4 5
EC_SMB_DA1 38,50 OT2 RHYST2
PR34
100K_0402_1% G718TM1U_SOT23-8
1 2 PRT9
+3VALW

2
100K_0402_1%_NCP15WF104F03RC

PR35
10K_0402_1%
1 2
A/D
BATT_TEMP 38,50
2

PD11
@ PESD5V0U2BT_SOT23-3
C C
1

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/01 Deciphered Date 2014/08/01 BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 49 of 65
5 4 3 2 1
 5 4 3 2 1

D P3 D

P2 PQ15
VIN PQ14 SIS406DN-T1-GE3_PAK1212-8-5 EMC@ PR77
SIS406DN-T1-GE3_PAK1212-8-5 3 3 PL3 0.01_1206_1%
2 2 1UH_PCMB053T-1R0MS_7A_20%
5 1 1 5 1 2 1 4
B+
2 3
EMC@ EMC@

4
1
1 PC31 PC33

1
0.022U_0402_25V 10U_0805_25V6-K

2
PC30 PR78

2
470P_0402_50V7K 4.7_0603_5% PC32
2 10U_0805_25V6-K PC34 PQ32

5
0.1U_0402_25V7-K SIS406DN-T1-GE3_PAK1212-8-5

2
1 2
BQ24780_BATDRV 4
PQ17
2N7002WT1G

1
2
3
0.01U_0603_50V7K
2

2
S

D
3 1 2

499K_0402_1%
PR79
1

1
PD20

PC37
RB751V-40 PC35 PC36

G
2

1
1U_0603_25V7-K PR82 0.1U_0402_25V7-K 1
1

1
2 1 1 2 10_0402_1% 2
1226@Bob PR83
PR80 PR81 10_0402_1%
PR274 PQ33 1M_0402_5% 1M_0402_5%
VIN B+

2
1

@ 0_0402_5% 2N7002WT1G D PR84

1 2 2 10_0402_1%
38 ACOFF G 1 2
DOCK_CONSUMP 32 RF_NS@

2
RB751V-40
S
3

PD15 1 2
VIN B+
1

PD14 RB751V-40
PR104 PC38
C
@ 100P_0402_50V8-J RF@ C

EMC@

2200P_0402_25V7-K
10K_0402_1%

10U_0805_25V6-K

10U_0805_25V6-K
47P_0402_50V8-J
1

1
1 1

68P_0402_50V8-J
1

1
PC40

PC41
PC253
PC39
2

ACN
ACP
PR85 PR88

PC254
2
4.02K_0603_1% PR86 432K_0603_1%

2
4.02K_0603_1% PR87 2 2
BQ24780_VDD

5
10_1206_5%
2

1
PC44 PC43

ACN
ACP
1
1U_0603_25V6M 2.2U_0603_25V6M
PR89 2 1 28 24 1 2
64.9K_0603_1% VCC REGN 4
1 2 6 PC46
ACDET 0.047U_0603_25V7M BATT+
1 2 25 BST_CHG1 2 2 1
BTST PR91

3
2
1
PC45 0.1U_0402_25V7-K PR90 PQ18 PL4 0.01_1206_1%
3 26 DH_CHG 2.2_0603_5% SIS412DN-T1-GE3 4.7UH_PCMB104T-4R7MS_20%
CMSRC HIDRV 1 2 CHG 1 4
4
PR92 @ 10K_0402_5% ACDRV 2 3

5
2 1 27 LX_CHG
+3VALW PHASE EMC@

2
4.7_0603_5%
PR93 1 2 @ 0_0402_5% 5
38 PACIN ACOK
PR95 1 2 @ 0_0402_5% 11 PR94 PC47 PC48
38,49 EC_SMB_DA1 SDA 23 DL_CHG 4
PU7 LODRV

10U_0805_25V6-K

10U_0805_25V6-K
1

2
PR96 1 2 @ 0_0402_5% 12 BQ24780RUYRGND 22
38,49 EC_SMB_CK1 SCL PQ19
EMC@

1
SIS412DN-T1-GE3

3
2
1

1
680P_0402_50V7K
PR97 1 2 @ 0_0402_5% 7 29 PC49
38 ADP_I IADP PAD
1 1

2
PR98 1 2 @ 0_0402_5% 8 18 BQ24780_BATDRV
IDCHG BATDRV PC50 PC51
PR99 1 2 @ 0_0402_5% 9 0.1U_0402_25V7-K
@ PR100 10K_0402_5% PMON 17 2 2 0.1U_0402_25V7-K
B
2 1 BATSRC PR101 10_0603_5%
B
+3VALW 20 2 1 SRP
PC53 1 2 10 SRP
38,57 VR_HOT# PROCHOT# 1
2

PR102 13 PC55
100P_0402_50V8J

PC52 PC54 @ 0_0402_5% CMPIN 0.1U_0402_25V7-K

BATPRES#

2
TB_STAT#

100P_0402_50V8J 100P_0402_50V8J 14 PR103 10_0603_5%

1

CMPOUT 19 2 1 SRN
21 SRN
ILIM
2

PR364
16

15

@ 0_0402_5%

0528@bob
1

BATT_TEMP 38,49
PR358 PR359
316K_0402_1% 18.2K_0402_1%
1 2 1 2
+3VALW
1
1

PR357
PC252 100K_0402_1%
0.1U_0402_25V6
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/01 Deciphered Date 2014/08/01 CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 50 of 65
5 4 3 2 1
 5 4 3 2 1

PJ2
2 1
+3VALWP 2 1 +3VALW
@ JUMP_43X118

D D
PJ3
3V5V_VIN +5VALWP
2
2 1
1
+5VALW
@ JUMP_43X118
VL +3VL

4.7U_0603_10V6-M

4.7U_0603_10V6-M

0_0603_5%
0_0603_5%
1
3V5V_VIN

2
19.6K_0402_1%

17.8K_0402_1%

2
PC57 1 1
0.1U_0402_25V7-K @

1
PJ4 2 @
EMC@ 3V5V_VIN

PR113

1
2 2

PC59

PR111

PC58
2 1
B+ RF_NS@ EMC@ EMC@

1
2 1 +3VALW
@ JUMP_43X118
2200P_0402_25V7-K

47P_0402_50V8-J

10U_0805_25V6-K

10U_0805_25V6-K
0.1U_0402_25V6
EMC@ RF_NS@ 1

1
PC66

PC67

PC68

PC69

PC70
PR110

PR112

2200P_0402_25V7-K
10U_0805_25V6-K

10U_0805_25V6-K

EMC@ 1

CS1 2
1

1
PC62

PC63

PC64

47P_0402_50V8-J
+3VLP

CS2
PQ21
0.1U_0603_25V7K

0.1U_0402_25V6

2
2
PC61

PC65 SIS412DN-T1-GE3
2

5
2
PC60

PR139
+5VALWP

12

13
100K_0402_1%

3
PQ20

1
SIS412DN-T1-GE3
FSW=400KHz

VIN

CS2

CS1

LDO5

LDO3
21
GND
7
PGOOD
4
TDC:8A
C
4
UG_3V 10 UGATE1
16 UG_5V
PR114 PC72
OCP:11A C
PC71 PR115 UGATE2 2.2_0603_5% 0.1U_0603_25V7K
PU8

3
2
1
0.1U_0603_25V7K 2.2_0603_5% 17 BST_5V 1 2 1 2
1 2 1 2 BST_3V 9 BOOT1 PL6
+5VALWP
1
2
3

PL5 BOOT2 2.2UH_PCMB063T-2R2MS_20%

+3VALWP 2.2UH_PCMB063T-2R2MS_20%
PHASE1
18 LX_5V 1 2
1 2 LX_3V 8
PHASE2

5
RT6585BGQW_WQFN20_3x3 15 LG_5V PQ23
EMC@ EMC@ EMC_NS@ LGATE1 EMC_NS@ EMC@ EMC@
2

2
PQ22 LG_3V 11 SIS472DN-T1-GE3
LGATE2

2200P_0402_25V7-K
PR116 SIS472DN-T1-GE3 14 PR117

0.1U_0603_25V7K
BYP1
2200P_0402_25V7-K

4.7_0603_5% 4.7_0603_5% 1 PC77

VCLK
0.1U_0603_25V7K

EN2

EN1
FB2

FB1

PC76
PC73 1

1
+
PC74

PC79
4

220U_B2_6.3VM_R25M
1

1
1

+
PC75

4
220U_B2_6.3VM_R25M

20

19

2
2

2
PC78 PR118

2
2
2

PC81
13K_0402_1%
EMC_NS@
2

1
2
0.1U_0402_25V6

EMC_NS@
1

3
2
1
1

PC80
1

1
2
3

1
FB_5V
PC82 680P_0402_50V7K @

51.1_0402_1%

1
680P_0402_50V7K
2

0.1U_0402_25V6
PR119
30K_0402_1%

FB_3V
@

PR241
PR120
2.2K_0402_1%
+3VALWP
2

1 2
B 38 EC_ON B
FSW=475KHz

1
PR121
TDC:8A 20K_0402_1%
1 2 PR122
1

OCP:11A 38,48,49 MAINPWON 19.6K_0402_1%

2
1

PD13 PC83
RB751V-40 0.1U_0402_6.3V7-K
2

0110@EE request

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/01 Deciphered Date 2014/08/01 3VALWP/5VALWP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
NM-A241 0.2

Date: Friday, June 13, 2014 Sheet 51 of 65

5 4 3 2 1
 A B C D

PJ5
2 1
2 1
@ JUMP_43X118

PJ6 +1.35V_DDR_VDDIOSUS
+1.35VP 2 1
2 1
@ JUMP_43X118
1 1

PJ7
+1.35VP +0.675VSP
2
2 1
1
+0.675VS
PJ8 EMC@ EMC@

10U_0603_6.3V6M
B+ @ JUMP_43X39

1
2 1

PC84
B+_1.35V
2 1
@ JUMP_43X79
RF_NS@ RF@

0.1U_0402_25V6

2
2200P_0402_25V7-K

10U_0805_25V6-K

10U_0805_25V6-K
1

1
PC87

PC89

PC90
PR125
196K_0402_1%

PC85
PR123

68P_0402_50V8J
47P_0402_50V8-J

PC88
@ 100K_0402_1%

2
2

PC86
2 1
+3VALW

+0.675VSP
PR124
100K_0402_1% +0.675VSP

+1.35VP
1 2

10U_0603_6.3V6M

0.1U_0402_6.3V7-K
2

1
PC91

PC92
+0.675VSP

5
TDC:1.5A

14

11

13

19

20

2
PQ24

PGND

VID

CS

VLDOIN

VTT
SIS412DN-T1-GE3 PR126 21
+1.35VP PC93 2.2_0603_5% PAD
4 1 2 1 2 18 1
FSW=285KHz BOOT VTTGND

TDC:8A 0.22U_0603_25V7K
DH_1.35V 17 2 +0.675VSP
UGATE VTTSNS
OCP:10A PL7

1
2
3
2
1UH_PCMC063T-1R0MN_+-20% 2

PU9 3
1 2 LX_1.35V 16 GND VTTREF_0.675V
+1.35VP PHASE
4 VTTREF_0.675V
EMC@ EMC@ VTTREF
2

PQ25 RT8231AGQW_WQFN20_3X3 PR129

EMC_NS@

5
2200P_0402_25V7-K

SIS472DN-T1-GE3 DL_1.35V 15 5.1_0603_5%

0.1U_0402_25V6

LGATE
1

PR127 12 2 1
470P_0402_50V7K
330U_D2_2V_R9M

1 VDD +5VALW

1
PGOOD
PC98

1 4.7_0603_5%
1

+
PC95

PC94

PC99

5 1 PC96

TON
1

VDDQ 0.033U_0402_16V7K

FB

S5

S3

2
PR128 4 PC97
2

2 2 8.06K_0402_1% 1U_0402_10VA-K
EMC_NS@

10
1

2
PC100
@ 680P_0402_50V7K

2 TON_1.35V

S5_1.35V

S3_1.35V
2

1
2
3

PR131
1

100K_0402_1%
PR130 1 2
10K_0402_1% +3VALW

887K_0402_1%
2

PR132
FB_1.35V

1
B+_1.35V

3 3

PR133
@ 0_0402_5%
38,43,56,59 SUSP# 1 2

1 2 S3_1.35V

PR134
@ 0_0402_5%

1
PC101
2 0.1U_0402_6.3V7-K

PR135
@ 0_0402_5%
1 2 S5_1.35V
38 SYSON
1

PC102
0.1U_0402_6.3V7-K
2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/01 Deciphered Date 2014/08/01 +1.35VP/+0.675VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
NM-A241 0.2

Date: Friday, June 13, 2014 Sheet 52 of 65

A B C D
 5 4 3 2 1

PR136
@ 0_0402_5%
1 2
38,57 APUPWR_EN
PC104

0.1U_0402_16V7-K
1

2
0.1U_0402_6.3V7-K
+3VALW

2
PR138

PC103
210K_0402_1%

1
D D

2
PR137

2
100K_0402_5%
PR238

24

25

26

27

28

29
191K_0402_1%

1
REFIN2

GND2
REFIN

EN
RA
VREF
+0.95VS_VCCPP

1
+5VALW 23 1
GSNS PGOOD
PGOOD 0.95VS
FSW=800KHz
PC105
22
VSNS LP#
2 PR142
@ 0_0402_5%
TDC:9A
PR140
@ 0_0402_5%
2 1 21
SLEW MODE
3 1 2 OCP:12A
1 2 0.01U_0402_25V7-K20 4 PR141 PC106
TRIP NC @ 0_0603_5% 0.1U_0603_25V7K
19 PU10 5 2
BST_0.95VS 1 1 2 PL8
GND1 BST 1UH_PCMC063T-1R0MN_+-20% +0.95VS_VCCPP
1 2 PC107 18 TPS51367RVER SW1 6 SW 0.95VS 1 2
PJ9 2.2U_0603_10V6-K V5
2 1

2200P_0402_25V7-K
VIN 0.95VS 17 7
EMC_NS@

10U_0805_25V6-K

10U_0805_25V6-K
2 1 VIN3 SW2
B+

2
68P_0402_50V8J

0.1U_0402_25V6
16 8

2200P_0402_25V7-K
@ JUMP_43X79 PR143

47P_0402_50V8-J
VIN2 SW3
1

1
PC109
bob@0609 4.7_0603_5%

PC110

PC111

PC112
1

0.1U_0402_25V6
15 9

PC113

PC117

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M
VIN1 SW4

1
PC118
PGND5

PGND4

PGND3

PGND2

PGND1

22U_0805_6.3V6-M
1 1 1 1
2

PC119
2

PC114

PC115

PC116

PC221

2
C C
2 2 2 2
RF@ EMC@ EMC@ RF_NS@ EMC_NS@

14

13

12

11

10

1
PC120
680P_0402_50V7K @

2
PJ10
Mode Frequency +0.95VS_VCCPP 2 1
+0.95VS
2 1
@ JUMP_43X118
GND 400KHz

Float 800KHz
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/01 Deciphered Date 2014/08/01 +0.95VS_VCCPP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 53 of 65
5 4 3 2 1
 5 4 3 2 1

D D
PR233

@ 0_0402_5%
2 1
38 S5_1.1_EN

0.1U_0402_16V7-K
1
PR146

PC121
1M_0402_5%

2
+1.1VALWP

1
FSW=800KHz
PJ11
TDC:5A

10U_0805_25V6-K
2 1 8 1 PR147 PC123
B+ 2 1
EMC@
IN EN @ 0_0603_5%
0.1U_0603_25V7K OCP:8A
@ JUMP_43X79 6 BS_1.1VS 2 1 1 2 PL9
1 BS

1
PC122

0.1U_0402_25V6
0.68UH_PCMB063T-R68MS_+-20%
+1.1VALWP

PC124
9 10 SW_1.1VS 1 2
+3VALW GND LX
2

2
PU11 4 FB_1.1VS
3 FB EMC@ EMC@
C ILMT +3VALW EMC_NS@ C

2
7

2200P_0402_25V7-K
BYP

0.1U_0402_25V6
PR148
PR149 SYX198DQNC 4.7_0603_5%

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M
@ 0_0402_5% 2 1 1 1 1
PG

1
PC126

PC131
1 2 5

1
LDO

PC128

PC129

PC130

PC125
4.7U_0402_6.3V6-M
PR150

2
1
2 2 2 2

PC127
4.7U_0402_6.3V6-M
2 1

2
EMC_NS@

1
PC132
100K_0402_5%

2
2

PC133
PR151 680P_0402_50V7K

2
@ 0_0402_5%

330P_0402_50V7-K
1

2
PC134
PR153
100K_0402_1%

1
2
PR152
B 1K_0402_1% B

1
+1.1VALWP PJ12 +1.1VALW
PR154 2 1
115K_0402_1% 2 1
@ JUMP_43X79

2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/01 Deciphered Date 2014/08/01 +1.1VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
NM-A241 0.2

Date: Friday, June 13, 2014 Sheet 54 of 65

5 4 3 2 1
 5 4 3 2 1

D D
PR155

@ 0_0402_5%
2 1
24 1.5VS_VGA_EN

0.1U_0402_16V7-K
1
PR156

PC135
DIS@ 1M_0402_5%

2
+1.5VSP

1
FSW=800KHz
PJ13 DIS@ DIS@
TDC:5A

10U_0805_25V6-K
2 1 8 1 PR157 PC136
B+ 2 1
DIS_EMC@
IN EN @ 0_0603_5%
0.1U_0603_25V7K OCP:8A
@ JUMP_43X79 6 BS_1.5VSP 2 1 1 2 PL10
1 BS

1
PC138
PC137 DIS@ 0.68UH_PCMB063T-R68MS_+-20%
0.1U_0402_25V6 9 10 SW_1.5VSP 1 2 +1.5VSP
+3VALW GND LX
2

2
PU12 4 FB_1.5VSP
3 FB DIS_EMC@
C ILMT DIS@ +3VALW DIS_EMC_NS@ C

2
DIS@ 7
BYP PR158 DIS@ DIS@ DIS@ DIS@ DIS_EMC@
PR159 SYX198DQNC 4.7_0603_5%

2200P_0402_25V7-K
22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

0.1U_0402_25V6
@ 0_0402_5% 2 1 1 1 1
PG

1
PC142

PC141
1 2 5

1
LDO

PC145

PC139

PC140

PC146
4.7U_0402_6.3V6-M
PR160

2
1
2 2 2 2

PC144
4.7U_0402_6.3V6-M
2 1

2
DIS_EMC_NS@

1
PC143
DIS@ 100K_0402_5%

2
1

PC147
PR161 680P_0402_50V7K

330P_0402_50V7-K
@ 0_0402_5%

DIS@
2

PC148

1
DIS@ DIS@
PR163

2
DIS@ 30.9K_0402_1%

2
2
DIS@ PR162
B 1K_0402_1% B

1
+1.5VSP PJ14 +1.5VS_VGA
2 1
2 1

2
@ JUMP_43X79
PR164
DIS@ 20K_0402_1%

1
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/01 Deciphered Date 2014/08/01 +1.5VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
NM-A241 0.2

Date: Friday, June 13, 2014 Sheet 55 of 65

5 4 3 2 1
 5 4 3 2 1

D D

+3VS

1
PR170
100K_0402_5%
+1.8VSP
PR172
FSW=1MHz

2
@ 0_0402_5%
38,57 VDDAPWROK
1 2
TDC:0.83A
PL11
1UH_PH041H-1R0MS_20%

4
C
PJ15 C
2 1 10 1 +1.8VS_LX 1 2
+5VALW

PG
2 1 PVIN2 LX1 +1.8VSP

2
@ JUMP_43X79 9 2
PVIN1 LX2
1

2
@ PR168

1
PC150 PC151 8 3 4.7_0603_5%
10U_0603_10V 10U_0603_10V SVIN1 LX3 PR173 PC162
EMC@
2

PU13 20K_0402_1%

2 1

2
RT8068AZQW PC154 PC155 PC156

1
5 6 22P_0402_50V

GND
EN FB

22U_0805_6.3VAM

22U_0805_6.3VAM

0.1U_0402_25V6
PR165 @ PC161

NC
10K_0402_1% 680P_0402_50V

2
1 2 EN_+1.8VS
38,43,52,59 SUSP#

11

7
PD5
2

RB751V-40
1

1 2
@ PR166 PC149

1
1M_0402_5% 0.1U_0402_10V
2
1

PR174
10K_0402_1%

2
1226@EE request
B B

+1.8VSP PJ16 +1.8VS

2 1
2 1
@ JUMP_43X79

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/01 Deciphered Date 2014/08/01 +1.8VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
NM-A241 0.2

Date: Friday, June 13, 2014 Sheet 56 of 65

5 4 3 2 1
 5 4 3 2 1

EMC@
PC163 PR175 PL15
680P_0402_50V 2K_0402_1% BLM18KG300TN1D
1 2 1 2
1 2
PL23
BLM18KG300TN1D

PR176 PR177 PC164 VIN_+VDDNB_CORE 1 2

PR181
PR178 1.4K_0402_1% 82K_0402_1% 390P_0402_50V B+
100_0402_1% 1 2 1 2 1 2 1 2
+VDDNB_CORE 1 2 RF_NS@ EMC@EMC@ EMC@
@ 32.4K_0402_1%

68U_25V_M

68U_25V_M

68U_25V_M
1 1 1 1

0.1U_0402_25V6
47P_0402_50V8-J

2200P_0402_25V7-K

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K
PR179 PR180 PC166

PC108

1
@ 0_0402_5% 301_0402_1% 150P_0402_50V + + +

PC193

PC194

PC195

PC196

PC255

PC256

PC197

PC198

PC199
5
1 2 1 2 1 2 1 2
D 7 VDDNB_SENSE 2 D

2
PC165 2 2 2
1000P_0402_50V7-K
PC167
1 2 UGATE_NB 4

@ +VDDNB_CORE
330P_0402_50V
VSUMP_NB
PQ26 FSW=300KHz
TDC=27A

3
2
1
TPCA8065-H PL12

2
PR182
0.36UH_PCMC104T-R36MN1R105_20%
OCP=45A

COMP_NB
VSEN_NB
2.61K_0402_1% PHASE_NB 1 4 +VDDNB_CORE
+VDDNB_CORE

FB_NB
2
2 3
EMC_NS@ 1 1 EMC@

2 1

2
2 PR221 PC200 1

2
PC169 BOOT_NB 1 2 1 2 PR222 PC257 PC201 + PC202 + PC203 PC204
PRT10 0.068U_0402_25V PGOOD_NB 4.7_0603_5% +

330U_D2_2VM_R9M

330U_D2_2VM_R9M

330U_D2_2VM_R9M

0.1U_0402_10V6K
CLOSE PL12 10K_0402_NTC PR245 2.2_0603_5% 0.22U_0603_25V7K

1
1 2 2

10U_0603_6.3V6M
11K_0402_1% LGATE_NB

1
1 PC168 PR185 LGATE_NB 4 4 2
0.1U_0402_25V7-K 715_0402_1% PHASE_NB PQ27 PQ28
VSUMN_NB 1 2
UGATE_NB
2 EMC_NS@

3
2
1

3
2
1
1 2 BOOT_NB

1
PC171 PC205
PR188 0.1U_0402_25V7-K PR186 PC170 680P_0402_50V7-K
1
CLOSE PQ26 27.4K_0402_1% @ 100_0402_1% @ 820P_0402_50V

40

39

38

37

36

35

34

33

32

31

2
1 2
TPCA8057-H TPCA8057-H

ISUMP_NB

ISUMN_NB

VSEN_NB

FB_NB

COMP_NB

PGOOD_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT_NB
PR192
10.7K_0402_1% PRT11
470K_0402_3% PR224
1 2 2 1 APU_NTC_NB 1 30 3.65K_0402_1%
NTC_NB BOOT2 VSUMP_NB 1 2
APU_IMON_NB 2 29
IMON_NB UGATE2
PR189 1 2 200_0402_5% APU_SVC_1 3 28 PR225
C
7 APU_SVC SVC PHASE2 1_0402_1% C
PR191 1 2 @ 0_0402_5% APU_VRHOT_A 4 27 PR196 VSUMN_NB 1 2
38,50 VR_HOT# VR_HOT_L LGATE2 @ 0_0603_5%
1

PR194 1 2 200_0402_5% APU_SVD_1 5 26 APU_VDDP PR198 2 1

7 APU_SVD SVD VDDP +5VS
1

1_0603_5%
PR193 PC175 PR195 1 2 @ 0_0402_5% 6 PU14 25 APU_VDD 2 1 PL20 EMC@
133K_0402_1% 1000P_0402_50V +1.35V_APU_VDDIO_RUN VDDIO VDD BLM18KG300TN1D
ISL62771HRTZ_TQFN40_5X5
2

1
PR197 1 2 200_0402_5% APU_SVT_1 7 24 LGATE1_APU
7 APU_SVT
2

SVT LGATE1 PC176 PC177 1 2

EN_APU PR199 1 2 @ 0_0402_5% 8 23 PHASE1_APU 1U_0402_10V 1U_0402_10V PL13

2
ENABLE PHASE1 BLM18KG300TN1D
1218@Bob
APU_PWROK_1 9 22 UGATE1_APU
PWROK UGATE1 VIN_+VDD_CORE 1 2
PC178 1 2 0.1U_0402_16V7-K 10
IMON BOOT1
21 BOOT1_APU B+
RF_NS@ EMC@EMC@ EMC@

PGOOD
ISUMN
ISUMP

COMP
ISEN2

ISEN1

VSEN
1

NTC

RTN

0.1U_0402_25V6
47P_0402_50V8-J

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K
1 2

PC152
FB

TP

2200P_0402_25V7-K
1

1
+1.35V_APU_VDDIO_RUN

PC206

PC207

PC208

PC209

PC259

PC260
5
PR202 133K_0402_1% +3VS

11

12

13

14

15

16

17

18

19

20

41
2

2
1

1
PR234 PR201 1 2 27.4K_0402_1%
@ 1.91K_0402_1% PR203 UGATE1_APU 4

APU_COMP
APU_VSEN
1.91K_0402_1%
+VDD_CORE

APU_FB
APU_RTN
2

2 1 PQ29

2
7,12 APU_PWROK
1 2 APU_PWROK_1
PRT12
PR237 FSW=300KHz
CLOSE PQ29 @ 0_0402_5% TPCA8065-H
TDC=25A

3
2
1
1

PR200 +5VS 470K_0402_3% PGOOD_APU 1 2 PL14

IMVPPOK 38
@ 0_0402_5%
PR204 PR236
0.36UH_PCMC104T-R36MN1R105_20%
OCP=43A
10.7K_0402_1% @ 0_0402_5% PHASE1_APU 1 4
+VDD_CORE
2

PGOOD_NB 1 2
2

PR205 2 3
EMC_NS@ 1 1 1 EMC@

2
@ 0_0402_5% PR227 PC210

2
+1.35V_APU_VDDIO_RUN BOOT1_APU 1 2 1 2 PR228 PC258 + PC211 + PC212 + PC213 PC214
4.7_0603_5%
1

330U_D2_2VM_R9M

330U_D2_2VM_R9M

330U_D2_2VM_R9M

0.1U_0402_10V6K
2.2_0603_5% 0.22U_0603_25V7K

1
2 2 2

10U_0603_6.3V6M
APU_ISEN2

1
B B
LGATE1_APU 4 PQ30 4 PQ31

APU_ISEN1
1

PR223 PR226 PR244

@ 1K_0402_1% @ @ 1K_0402_1%
EMC_NS@

3
2
1

3
2
1
1

1
1K_0402_1%

PC215
PR240 680P_0402_50V7-K
2

10K_0402_1%

2
PC182 PR206 PC183 PR208
330P_0402_50V
2

1000P_0402_50V7-K 301_0402_1% 68P_0402_50V @ 32.4K_0402_1% TPCA8057-H TPCA8057-H

APU_SVC_1 1 2 1 2 1 2 2 1

APU_SVD_1 VSUM+_VDD
2

PR211 PR213 PC184

APU_SVT_1 PR210 1.4K_0402_1% 110K_0402_1% 390P_0402_50V
0.068U_0402_25V

2.61K_0402_1% 1 2 1 2 1 2
2

PR230
PC187
2

3.65K_0402_1%
PC185
11K_0402_1%
1
1

PC186 PR214 PC189 VSUM+_VDD 1 2

PR212

PR1 PR6 PR5 CLOSE PL14 0.1U_0402_25V6 @ 2K_0402_1% 680P_0402_50V

2

2
2

@ 220_0402_5% @ @ 220_0402_5% 1 2 2 1
PRT13 PR231
1
220_0402_5%

10K_0402_NTC PR215 1_0402_1%

2

PR216 10_0402_1% VSUM-_VDD 1 2

665_0402_1% 1 2
+VDD_CORE
1

1 2APU_ISUMN
VSUM-_VDD PR217
2 @ 0_0402_5%
1 2
PC190 VDD_SENSE 7
PRE-PWROK METAL VID CODES 1
0.1U_0402_25V7-K
1 2 PR219
@ 0_0402_5%
SVC SVD Boot Voltage PR218 PC191 1 2
@ 100_0402_1% @ 820P_0402_50V VSS_SENSE 7
PR220
0 0 1.1V
1

PC192 10_0402_1%
0.01U_0402_25V 1 2
A
0 1 1.0V(Default) PR207 A
2

@ 0_0402_5%
1 0 0.9V 1 2
38,53 APUPWR_EN
1 1 0.8V
1 2 EN_APU
38,56 VDDAPWROK
PR209
@ 10K_0402_1%
1

PC188 Title
0.1U_0402_10V7-K Security Classification LC Future Center Secret Data
2

Issued Date 2013/08/15 Deciphered Date 2013/08/15 VCORE/VDDNB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 57 of 64

5 4 3 2 1
 5 4 3 2 1

D D
+VDDNB_CORE

1 1 1 1 1
PC216 PC217 PC218 PC219 PC220
22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M
2 2 2 2 2

1 1 1 1 1 1 1
PC225 PC226 PC227 PC228 PC229 PC230 PC231
22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M @ 22U_0805_6.3V6-M @ 22U_0805_6.3V6-M
2 2 2 2 2 2 2

C C

+VDD_CORE

1 1 1 1 1
PC233 PC234 PC235 PC236 PC237
22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M
2 2 2 2 2

1 1 1 1 1
PC238 PC239 PC240 PC241 PC242
22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M
2 2 2 2 2

B B

1 1 1
PC243 PC232 PC244
22U_0805_6.3V6-M @ 22U_0805_6.3V6-M @ 22U_0805_6.3V6-M
2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/01 Deciphered Date 2014/08/01 VCCCPUCORE DECOUPLING
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
NM-A241 0.2

Date: Friday, June 13, 2014 Sheet 58 of 65

5 4 3 2 1
 5 4 3 2 1

ISL62771 Schematic for FT3 solution PR355

@ 0_0402_5%
1 2
38,43,52,56 SUSP# +5VS +5VS
PD4 DIS_EMC@ B+
DIS@ RB751V-40 +VGA_B+ PL21

1
1 2 BLM18KG300TN1D
1226@EE request PR300 PR301 DIS_EMC@ DIS_EMC@ 1 2
PR352 @ 0_0603_5% @ 0_0603_5%
DIS@ 2.2K_0402_5% DIS@ DIS@

5
1 2

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
2

2
12,17,24 DGPU_PWREN PC321 PC323

2200P_0402_50V7K
VDD_62771 DIS_RF_NS@ 1

1
PC324

PC322
PC335 PC153

1
+3VS DIS@ 0.1U_0402_25V6 PC289 PC290
DIS@ 1U_0402_10V DIS@ 1U_0402_10V 4 47P_0402_50V8-J

2
D 2 D

2
PQ42
+VGA_CORE

2
DIS@ TPCA8065-H PL18 +VGA_CORE

25

26
PR351 FSW=300KHz

3
2
1
DIS@ 10K_0402_1% DIS@ 0.36UH 20% PDME064T-R36MS1R405

VDDP
VDD
TDC=31A
1 4
MAX=46.5

1
PR333 8
ENABLE
@ 0_0402_5% 2 3 OCP=48A

5
1 2 PG_VDD 20 PR331 DIS@
12 DGPU_PWROK PGOOD
35 @ 0_0603_5% PC312 DIS@ DIS@ DIS@
DIS_EMC_NS@

2
PGOOD_NB

4.7_0603_5%
21 2 1 1 2
PR299 1 2 @ 0_0402_5% 9 BOOT1 VSUM+ 1 2 PC331 1 PC332 1 PC333
17,18 PLT_RST_VGA# PWROK
PR302 1 2 @ 0_0402_5% 3 0.22U_0603_25V7-K PR353 DIS@ 3.65K_0402_1% PR343
18 SVI2_SVC SVC

1
PR303 1 2 @ 0_0402_5% 5 22 4 + +

0.1U_0402_25V6
330U_D2_2VM_R9M

330U_D2_2VM_R9M
18 SVI2_SVD SVD UGATE1
PR306 PR304 1 2 @ 0_0402_5% 7 ISEN1 1 2
18 SVI2_SVT

1
@ 0_0402_5% PR305 1 2 @ 0_0402_5% 4 SVT PQ43 PR344 DIS@ 10K_0402_1%
18,38 GPU_VR_HOT#

2
VR_HOT_L

2
2 1 6 23 DIS@ TPCA8057-H 2 2
+1.8VS_VGA VDDIO PHASE1

1
PC319 DIS@ PC318

3
2
1

680P_0402_50V7K
DIS@ PC304 1 2 100P_0402_50V 0.22U_0603_25V7-K DIS@

1
PR313 1 2 @ 0_0402_5% 24 VSUM- PR345 1 2 1_0402_1%
+3VS_VGA

2
DIS@ DIS@ LGATE1
DIS@ 1 2 PC292 1 2 150P_0402_50V 19 PR332 DIS_EMC_NS@
DIS@ PR312 499_0402_1% PR308 39K_0402_1% COMP @ 0_0603_5% PC313
+VGA_CORE 1 2 1 2 30 2 1 1 2
PC298 470P_0402_50V7-K PR309 1 2 BOOT2
19 VDDC_SEN PR316 DIS@ @ 32.4K_0402_1% 0.22U_0603_25V7-K
2

1 2 18 29
10_0402_1%

PR307 PR356 910_0402_1% FB UGATE2

DIS@
1

@ 0_0402_5% 1 2 PC293 1 2 @ 680P_0402_50V7-K

PC295
DIS@
PR311 @ 2.7K_0402_1% 28 DIS_EMC@ B+
330P_0402_50V7-K PHASE2 +VGA_B+ PL1205
1

16 BLM18KG300TN1D
VSEN DIS_EMC@ DIS_EMC@
1

DIS@ 27 1 2
DIS@ PC294 LGATE2
DIS@ 330P_0402_50V7-K 17 PU15
2
2

PR317 RTN DIS@ DIS@

1

5
PR310 PC297 PC328 PC326
10_0402_1%

ISL62771HRTZ_TQFN40_5X5 DIS_RF_NS@
@ 0_0402_5% 1000P_0402_25V7-K PC325 PC327

10U_0805_25V6K
1
2

1
PC157

10U_0805_25V6K
0.1U_0402_25V6

2200P_0402_50V7K
1

DIS@ 36 31 VDD_62771 47P_0402_50V8-J

2

2
C 19 VDDC_RTN COMP_NB BOOT_NB 4 2 C
DIS@
PR229 32 PR268 PQ44
DIS@ @ 10K_0402_1% UGATE_NB 10K_0402_1% DIS@ TPCA8065-H
1 2 37 PL19 +VGA_CORE

3
2
1
FB_NB 33 1 2
PHASE_NB DIS@ 0.36UH 20% PDME064T-R36MS1R405
DIS@
34 1 2 1 4
38 LGATE_NB
VSEN_NB PR269 2 3

5
10K_0402_1%
DIS_EMC_NS@

2
4.7_0603_5%
VSUM+ 1 2
VSUM+ 14 13 ISEN1 PR354 DIS@ 3.65K_0402_1% PR347 DIS@ DIS@ DIS@
ISUMP ISEN1 PC314 1 PC329 1 PC334
12 ISEN2 4 ISEN2 1 2

1
ISEN2

1
15 DIS@ PR348 DIS@ 10K_0402_1% + +

0.1U_0402_25V6
330U_D2_2VM_R9M

330U_D2_2VM_R9M
ISUMN

2
PQ45

1
TPCA8057-H PC320 DIS@ PC336

2
1

2 2

680P_0402_50V7K
DIS@ 0.22U_0603_25V7-K

3
2
1

1
40 VSUM- PR349 1 DIS@ 2 1_0402_1%
DIS_EMC_NS@

2
ISUMP_NB
PC291

PR323 PC306
DIS@ 2.61K_0402_1% DIS@ @
1
330P_0402_50V7-K

DIS@ 1 1 39
2

ISUMN_NB
1

PC307 DIS@ PR266

PR326 100K_0402_1%
2

2
11K_0402_1%

0.1U_0402_25V7-K

82N_0402_50V

1 1 2
2 2 PR232 NTC_NB 11
2

DIS@ @ 0_0402_5% NTC

2

PRT14 PR324 10
DIS@ 10K_0402_NTC 604_0402_1% IMON 2
1

IMON_NB
TP

CLOSE PL18
1

2
2

41

27.4K_0402_1%
PR325

1
100K_0402_1%

DIS@ DIS@ PRT15 DIS@

PR265

VSUM- PR337
470K_0402_3%_NCP15WM474E03RC
2

@ 100_0402_1%

2
PC308 CLOSE PQ42
2

B DIS@ 0.1U_0402_25V6 B
1

BOTTOM PAD
CONNECT TO GND
Through 8 VIAs
2

DIS@ PC317 DIS@

0.1U_0402_25V6 PR336 DIS@
1

PR340
130K_0402 10.7K_0402_1%
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/01 Deciphered Date 2014/08/01 +VGA_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A241
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, June 13, 2014 Sheet 59 of 65
5 4 3 2 1
 5 4 3 2 1

Item Reason for change PG# Modify List Date Phase

1 GPU power sequence tuning 24 1.RV132 from 20K ohm change to 3.3K ohm 2013.12.26 FVT
12 2.CV165 from 1000PF change to 820PF
3.RV129 from 51K ohm change to 180K ohm
D 4.RV133 from 47K ohm change to 240K ohm D

5.Add DV5
6.RH145 pull down to 1K ohm
7.change RH35 to @
8.reserver GPU core discharge circiut(RV144, RV143,QV13)

2 APU_RESET signal noise 7 1.reserve CC169 2013.12.26 FVT

3 EMI request 36 1.CL27 change to 2000V 2013.12.26 FVT

4 Common design 14 1.add RH92 to separate 2013.12.26 FVT
5 System power sequence 43 1.add +3VS discharge circuit Q17,R120
2.change D5 to mount form @ 2013.12.26 FVT

C 6 Common design 43 1.RA2 change to @ , Add RA3 connect to 3VL 2013.12.26 FVT C

7 ECSL request 40 1.SB000007H1J change to AOS AO3413 SB93413000J(QG1, QV5) 2013.12.26 FVT
24 2.SB000002R0J change to LRC LMBT3904WT1G SB00000ZJ00
(Q1,Q8,Q9,QC1,QC2,QV3,,QC4,QC5)
3.SE000000KMT change to SE00000X30T(C1,C3,C70,C140,C141,C146,C147,C148,
CA9,CA13,CA14,CA15,CA17,CD22,CV163)

8 del double component 38 1.Del RE2, RE3 2013.12.26 FVT

9 modify SMBus issue 7 1.QC7, QC6 gate G connect to 1.35V run del RC71,RC72 2013.12.26 FVT
10 SMBus issue 7 1.add RC21 2013.12.30 FVT

11 Cost down component count 38 1.RE30, RE29, RE11 change to @ 2013.12.30 FVT
B B

12 Cost down component count 14 1.RH87 change to @ 2013.12.30 FVT

13 Cost down 15 1.RH62 change to mount, LH2 change to @ 2013.12.30 FVT

14 Cost down component count 18 1.RV75 change to @ 2013.12.30 FVT
15 Cost down component count 18 1.RV82, RV83 change to @ 2013.12.30 FVT
16 Cost down component count 18 1.RV150, RV151 change to JET@ from @ 2013.12.30 FVT
2.RV125, RV122 change to @ form DIS@
3.CV149,CV150,RV96, RV97,RV95,CV152,CV151,UV9 change to @ form JET@

17 Cost down component count 26 1.R4, RC73, RC74 change to@ 2013.12.30 FVT
7
18 Cost down component count 7 1.RC17,18,13, 19 del add RP4 2013.12.30 FVT
A A

19 Cost down component count 7 1.RC47,48,49 del add RP5 2013.12.30 FVT

20 Cost down component count 7 1.RC37,38,39,40 del add RP6 2013.12.30 FVT
Title
<Title>

21 EC_MUTE# leakage issue 38 1.add D6 Size Document Number Rev 2013.1.3 FVT
C <Doc> 0.2

Date: Friday, June 13, 2014 Sheet 60 of 60

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 5 4 3 2 1

Item Reason for change PG# Modify List Date Phase

22 for EC mirro function 38 add D6,RA29 and RE12 change to mount 2013.01.06 FVT

23 BIOS request 14 change GPIO ipin to G-event 5 2013.01.06 FVT

24 PEG signal EA request 7/17 change PEG capacitor to 0.22u 2013.01.06 FVT
D
25 reduce component count 7/17 DEL RC45,R66, RH70,RH71,RH72,RH73,RH77,RV136,RW4,RW5,RW7,RW8,RW9,RW10 2013.01.06 FVT D

26 Pin define modify 35 JSPK 2013.02.27 SIV

27 modify BOM strcture 7 CC169 2013.02.27 SIV

28 modify BOM strcture 43 QV13 change to Q13 2013.02.27 SIV

29 modify BOM strcture 24 UV11 change to DIS@ form always mount 2013.02.27 SIV
30 remove FP function 18 DEL R111,D25,C136, JFPB 2014.02.24 SIV

31 reduce component count del 0402 2014.02.24 SIV

R10 R106 R107 R134 RA28 RC43 RE26
RH6 RH7 RH8 RH9 RH10 RH11 RH12
RH13 RH14 RH15 RH16 RH17 RH44
RH22 RH57 RH58 RH76 RH91 RH98
RH90 RH122 RH125 RH126 RH127 RH128
C
RH129 RH130 RL22 RV150 RV151 C

0603
R5 R100 R110 RH78 RH79 RH80
RH81 RL4
0805
R8 R37 RA1 RA3 RA4 RA6 RH62 RH61 RH142
RH143
RL1
32 CP SMB issue 14/42 add R43,R44 for SMB pull up 2014.02.24 SIV

33 separate HDT connector 7 add R137@ 2014.02.24 SIV

APU_RESET# signal
34 remove GPU CTF function 18 DEL QV3,CV148,RV87,DV1,RV86,RV88,RV74 2014.02.24 SIV

35 change BOM Structure 4 change CC1~CC8, CC106~CC113 to DIS@ 2014.05.14 SVT

B
36 Audio test request 35 CA 31, CA 32 change to 10u form 4.7u 2014.05.28 SVT B

37 Power sequence modify 43 C142 change to 220p form 2200p 2014.05.28 SVT
C143 change to 100p form 1000p

A A

Title
<Title>

Size Document Number Rev

C <Doc> 0.2

Date: Friday, June 13, 2014 Sheet 61 of 61

5 4 3 2 1