DFT Embedded Memory

10/20/2010

for

Sangmin, Sangmin Bae DFX Group IDC, System LSI, Samsung Electronics Co, Ltd Co Samsung Property

Contents
Introduction
Environments and Scopes

Technical Items
Integration complexity MBIST design consideration Design flow consideration Repair and ECC

More Technical Items Summary

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Introduction
Status on eMemory Testing Driver
Complex advanced design flow with limited TAT Complex,

Design capacity : Mega SOC, near NoC product

Hierarchical, modular design flow

Advanced lo po e Ad anced low-power design techniq e technique Design reuse : Heterogeneous IP integration

R id process migration i Rapid i i into nano-technology h l

Performance gain and yield goal is more challenging than before Reliability, test escape reduction Bit-cell engineering requires efficient channel for si. analysis

Well tuned DFx technique

Typically, DFT resources are re-purposed for DFx

Productivity, Reliability, Debug, etc.

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Introduction
Scope and limitation on eMemory Testing Typically, memory is not fully controllable and we have fewer knobs than logic dft (scan) technique technique.
Memory BIST y

MBIST is classical and well-defined technique, but most of eMemory design and test issues are tightly coupled with DFT logic ( g (MBIST). So, re-visiting of MBIST is still occurred ) , g Not easy to maintain current through-put within the previous DFT resource (test cost, H/W area) cost

Providing flexible MBIST automation tool is not sufficient

SiP, TSV testing is still challenging area in the real action

Evolution of existing technique is not sufficient

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Integration Complexity
Difficulty on SRAM Tests

Layout is more crucial compare with logic std. cell Each 6 tr. has very strong relationship : y g p Trade-off exists between area, performance, yield Bit-cell array and peri. circuit is controlled by self-timed logic SRAM configuration widely varies on their usages Most SRAM are deeply embedded in a chip MBIST just do functional test on SRAMs

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Row-Decoder o Column mux + Sense Amp

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Integration Complexity
Who is DFT player?
Example : test lvcc problem
Vector and screening condition

Test engr IP or package engr SoC DFT designr FE/BE eng r engr

IO + package spec. full-chip full chip level DFT planning power-clock network
Design methodology + Sign-off rules

MBIST engr

SRAM core 6T bit-cell w/ SNM, SNM DNM + peri. design w/ self-timing margin

Process eng r engr SRAM designer

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Integration Complexity
Memory BIST Limitation

Typically, MBIST is implemented on ASIC flow Test is based on functional test Without memory changes, very difficult to obtain useful knobs on test Example : Controlling clock skew between multi-port memories Each type could requires extra implementation overhead Sacrifice parallelism for area reduction Poor resolution Pattern development difficulties p p / p ROI perspective : Trade-off b/w implementation efforts and TAT

BIST A

BIST B

BIST

BIST
direct control clock

mem. mem.
Port A Port B 0 1 1 0 0 1

mem.
1 0

A Type

B Type

C Type

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Integration Complexity
MBIST complexity Increased memory counts
Hierarchical/multi-step generation and insertion capacity Redundancy strategy

Multiple power-domain and various power-gating scheme

Repair-information distribution T Test condition control i multiple voltage l di i l in li l l level l

Light-weight clock-domain crossing control is required

JTAG is just simple std. Programmability control Redundancy information handling
SoC JTAG
IP i/f mbist

Top controller w/ repair function block

IP i/f mbist mbist

mbist

Solution approaches
JTAG + IEEE1500 interface with tricky interface blocks MBIST insertion variation GL vs. RTL insertion Hierarchical test-bus

mbist

Block A
IP i/f mbist

mbist

mbist

Block C

mbist

IP i/f

Block B

Big hard-macro IP inc. memories Typical SoC MBIST Architecture

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Memory BIST Design

Memory BIST Design MBIST using HDL based ASIC flow Common features : Programmable, at-speed fail-bit map High-speed option : PLL, data-path pipelining, FSM design

MBIST generator : easily adapted and deployed in industry Script or GUI based input form : memory and MBIST lib. format Based on configurable and parameterized template ased o co gu ab e a d pa a e e ed e p a e IDE fasten DK iteration : planning, insertion, verification Several consideration : mainly automation and flow issues Customization can not be avoidable Different DFT budgets and targets by different customer Clock scheme, and scan mode isolation scheme Seamless automation flow requires continuous efforts Hard to be properly hidden during implementation flow Timing closure, STA, Verification closure STA Samsung Property

Design Flow Consideration

RTL vs. GL MBIST Flow TAT is a main driving factor : IP and tools status Selection could different depends on design-flow and tool-chain It mainly depends on other constraints, not by MBIST HDL interface capability is mandatory No leading/full standards exists g/

JTAG + IEEE1500 style is very popular but, loose standards

RTL Logic- synthesis Scan Synthesis Boundary Scan

Simple Concept

design planning Top-level integration l l IP integration

ECO & verification Timing closure flow automation

EDA tool integration Complex Execution

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Si. Diagnosis of SRAM

eMemory Si. Diagnosis
eMemory Si. diagnosis motivation

Low yield, poor device characteristics, test escape, etc.

Several approaches pp

Initial statistical analysis Extract exact fail bit-map Parametric analysis using memory operation mode MBIST logic fails Typically, detected by design verification review and work around work-around can be exists

Test escape

Re producing Re-producing fail on DFT@ATE test is technical goal Main barrier : lacks of fail modeling and MBIST flexibilities Diagnosis time is most important

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Programmable MBIST
Programmable MBIST Flexibility depends on structures
FSM-based FSM based ALPG like (micro-code based) Extension of general micro-controller ISA w/ custom module
Needs of programmable MBIST

Control of complex memory IP : eDRAM, KGD(SiP, TSV) Si diagnosis repair analysis : diagnostic pattern, repair analysis Si. diagnosis, pattern
Pattern level programmability seems to be not sufficient

ALPG ( i i memory ATE) approaches i popular (mini. h is l Pattern development costs Well defined flexible ISA
ATE or on-chip control interface is one of issues

JTAG or AMBA-bus based Vector and simulation flow is required Samsung Property
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Repair and ECC

General Memory Redundancy Scheme
1D Redundancy 2D (Row/Column) Redundancy Hier. Redundancy Redundancy

1D Redundancy Red. Type # of Red. BIRA Single (Row / Column / IO) N Simple

2D Redundancy Row + Column 2N Medium

2.5D Redundancy (Row + Column) * M 2N * M Complex

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Repair and ECC

Typical MBIST structure on SOC Top DFT controller inc. JTAG interface Local Memory BISTs Fuse related logic for repair Features on MBIST design Memory isolation and clocking scheme Interface between Top DFT controller and Local BIST logics Repair policy and repair-bus structure repair bus

JTAG

IEEE 1500 or custom control

Wrapper

Wrapper

Wrapper

JTAG

Top DFT Controller Repair Analysis

BIST
Fuse Related Controller

SRAM

...

SRAM

SRAM

Serial or Parallel Bus

Repair Address

Repair Address

General MBIST Structure

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Repair and ECC

ECC Typically, SRAM ECC regarded as having big-overhead technique
Area, timing overhead Increase complexities of test condition and repair flow
Popular ECC code : SEC-DED, SEC-SED Architectural approaches are trends for eMemory ECC

Combined with redundancy and other design constraints/techniques

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Memory Test Bus

Memory Test Bus Motivation i i Traditional memory isolation and MBIST insertion are can be performance, implementation TAT intrusive W ll d fi d and fi d Well-defined d find-grain t t b i test-bus protocol will catch both performance t l ill t h b th f and DFT productivity goals Current MBIST solution is not suitable for this kind of approaches Early stage of its adaption on several IPs
Pre-designed Re-configurable IP Re epairBu us
repair interconnection

Serial F/F Memory Instance

Me emory Ins stance

Me emory Ins stance

Configurable BIST or BIRA w/o Memory Memory Te est-Bus

Memory Instance

Memory Instance

F/F
normal memory bus

Memory Instance e

Memory Instance

normal memory bus

normal memory bus F/F

F/F
BIST vs. Memory Interconnection

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MBIST Planning and Test Scheduling

Backgrounds
For multiple MBISTs in a chip, how to merge/split MBIST(s)? Trades-off is exists (accuracy or q&d solution) ( y q ) Approaches Candidates Memory BIST grouping/scheduling automation

Both, spec. and run-time level required , p q Should consider BIST generation, pattern, repair

Run-time scheduling flow should reflect other constraints

ATE interface overhead Diagnosis

Flow Considerations Accuracies

Average vs. peak power based Clock skew and timing dependency P&R floor-planning back-annotation Memory operations

Peak Power Run #1

Run #2

Run u #3

Run #4

Capacities
MILP or graph-based solver Graph-based : bin-packing problem Graph based bin packing

Test Time

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More Technical Items

Several topics on eMemory DFT

Bit-cell related Reliability and manufacturability issues NBTI, Hot-carrier, TDDB Memory related Multi port memory related Multi-port Parametric diagnosis structure Memory test-assist function support g g / Design-assist function using BIST/BIRA resource BIST-BIRA related BISR(self-repair) Repair analysis algorithm fuse-compress and repair-bus structure BIST/BIRA planning and scheduling Shared BIST or hierarchical BIST architecture BIST/BIRA planning w/ design constraints TSV, SiP memory test support

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Summary
DFT for Memories Memory BIST for eSRAM
On-product diagnostic features in mass volume On product Fluent and flexible design flow
Memory BIST for SiP, TSV

KGD test is still challenging on real execution

Memory BIST for DFx

Basic infra structure for eSRAM DFT

Technical requirements on current MBIST Well-designed memory test-bus g y Matured programmable MBIST for SiP, TSV Latest full-chip DFT architecture compliance

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