Unit – 6

Pipeline And Vector

Processing

HITESH RAVANI
9978139389
[email protected]

Computer Organization & Architecture (3140707) Shree Swami Atmanand Saraswati Institute of Technology
PIPELINING AND VECTOR PROCESSING

• Parallel Processing

• Pipelining

• Arithmetic Pipeline

• Instruction Pipeline

• RISC Pipeline

• Vector Processing

• Array Processors
 Parallel Processing

PARALLEL PROCESSING

Execution of Concurrent Events in the computing process to achieve

faster Computational Speed

Levels of Parallel Processing

- Job or Program level

- Task or Procedure level

- Inter-Instruction level

- Intra-Instruction level
 Parallel Processing

PARALLEL COMPUTERS

Architectural Classification

* Flynn's classification
- Based on the multiplicity of Instruction Streams and Data Streams
- Instruction Stream
Sequence of Instructions read from memory
- Data Stream
Operations performed on the data in the processor

Number of Data Streams

Single Multiple

Number of Single SISD SIMD

Instruction
Streams Multiple MISD MIMD
 Parallel Processing

SISD COMPUTER SYSTEMS

Control Processor Data stream Memory

Unit Unit

Instruction stream

Characteristics
it is a limitation on
- Standard von Neumann machine
throughput caused
- Instructions and data are stored in memory
- One operation at a time by the standard personal
computer architecture.
Limitations

Von Neumann bottleneck

Maximum speed of the system is limited by the

Memory Bandwidth (bits/sec or bytes/sec)

- Limitation on Memory Bandwidth

- Memory is shared by CPU and I/O
 Parallel Processing

PERFORMANCE IMPROVEMENTS

• Multiprogramming
• Spooling
• Multifunction processor
• Pipelining
• Exploiting instruction-level parallelism
- Superscalar
- Superpipelining
- VLIW (Very Long Instruction Word)
 Parallel Processing

MISD COMPUTER SYSTEMS

M CU P

M CU P Memory
• •
• •
• •

M CU P Data stream

Instruction stream

Characteristics

- There is no computer at present that can be

classified as MISD
 Parallel Processing

SIMD COMPUTER SYSTEMS

Memory
Data bus

Control Unit
Instruction stream

P P ••• P Processor units

Data stream

Alignment network

M M ••• M Memory modules

Characteristics

- Only one copy of the program exists

- A single controller executes one instruction at a time
 Parallel Processing

TYPES OF SIMD COMPUTERS

Array Processors

- The control unit broadcasts instructions to all PE(processing

elements) and all active PEs execute the same instructions

- ILLIAC IV (the first massively parallel computer.),

GF-11(parallel computer currently under construction at the IBM Yorktown
Research Center ,Supercomputer),
Connection Machine, DAP (Distributed Array Processor),
MPP (massively parallel processing)

Systolic Arrays

- Regular arrangement of a large number of very simple processors

constructed on VLSI (Very-large-scale integration ) circuits
- CMU Warp, Purdue Chip

Associative Processors

- Content addressing
- Data transformation operations over many sets of arguments with
a single instruction
- STARAN, PEPE
 Parallel Processing

MIMD COMPUTER SYSTEMS

P M P M ••• P M

Interconnection Network

Shared Memory

Characteristics

- Multiple processing units

- Execution of multiple instructions on multiple data

Types of MIMD computer systems

- Shared memory multiprocessors

- Message-passing multicomputers
 Parallel Processing

SHARED MEMORY MULTIPROCESSORS

M M ••• M

Buses,
Interconnection Network(IN) Multistage IN,
Crossbar Switch

P P ••• P

Characteristics
All processors have equally direct access to one large memory
address space
Example systems
Bus and cache-based systems
- Sequent Balance, Encore Multimax
Multistage IN-based systems
- Ultracomputer, Butterfly, RP3, HEP
Crossbar switch-based systems
- C.mmp, Alliant FX/8
Limitations
Memory access latency
Hot spot problem
 Parallel Processing

MESSAGE-PASSING MULTICOMPUTER
Message-Passing Network Point-to-point connections

P P ••• P

M M ••• M

Characteristics

- Interconnected computers
- Each processor has its own memory, and communicate
via message-passing

Example systems

- Tree structure: Teradata, DADO

- Mesh-connected: Rediflow, Series 2010, J-Machine
- Hypercube: Cosmic Cube, iPSC, NCUBE, FPS T Series, Mark III

Limitations

- Communication overhead
- Hard to programming
 Parallel Processing

COMPUTER ARCHITECTURES FOR PARALLEL PROCESSING

Von-Neuman SISD Superscalar processors

based
Superpipelined processors

VLIW

MISD Nonexistence

SIMD Array processors

Systolic arrays
Dataflow
Associative processors

MIMD Shared-memory multiprocessors

Reduction
Bus based
Crossbar switch based
Multistage IN based

Message-passing multicomputers

Hypercube
Mesh
Reconfigurable
 Pipelining

PIPELINING
A technique of decomposing a sequential process
into suboperations, with each subprocess being
executed in a partial dedicated segment that
operates concurrently with all other segments.
Ai * Bi + Ci for i = 1, 2, 3, ... , 7
Ai Bi Memory Ci
Segment 1
R1 R2

Multiplier
Segment 2

R3 R4

Adder
Segment 3

R5

R1  Ai, R2  Bi Load Ai and Bi

R3  R1 * R2, R4  Ci Multiply and load Ci
R5  R3 + R4 Add
 Pipelining

OPERATIONS IN EACH PIPELINE STAGE

Clock Segment 1 Segment 2 Segment 3

Pulse
Number R1 R2 R3 R4 R5
1 A1 B1
2 A2 B2 A1 * B1 C1
3 A3 B3 A2 * B2 C2 A1 * B1 + C1
4 A4 B4 A3 * B3 C3 A2 * B2 + C2
5 A5 B5 A4 * B4 C4 A3 * B3 + C3
6 A6 B6 A5 * B5 C5 A4 * B4 + C4
7 A7 B7 A6 * B6 C6 A5 * B5 + C5
8 A7 * B7 C7 A6 * B6 + C6
9 A7 * B7 + C7
 Pipelining

GENERAL PIPELINE

General Structure of a 4-Segment Pipeline

Clock

Input S1 R1 S2 R2 S3 R3
3 S4 R4

Space-Time Diagram

1 2 3 4 5 6 7 8 9 Clock cycles
Segment 1 T1 T2 T3 T4 T5 T6
2 T1 T2 T3 T4 T5 T6
3 T1 T2 T3 T4 T5 T6
4 T1 T2 T3 T4 T5 T6

To complete n tasks using k-segment pipeline no.of clock cycles required =k+(n-1)
 Pipelining

PIPELINE SPEEDUP

n: Number of tasks to be performed

Conventional Machine (Non-Pipelined)

tn: Clock cycle
t1: Time required to complete the n tasks
t1 = n * tn

Pipelined Machine (k stages)

tp: Clock cycle (time to complete each suboperation)
tk: Time required to complete the n tasks
tk = (k + n - 1) * tp

Speedup
Sk: Speedup=(Non-Pipelined/ Pipelined Machine )

Sk = n*tn / (k + n - 1)*tp
If n is much larger then,
tn
Sk = ( = k, if tn = k * tp )
tp
 Pipelining

PIPELINE AND MULTIPLE FUNCTION UNITS

Example Ii I i+1 I i+2 I i+3
- 4-stage pipeline; k=4
- subopertion in each stage;
tp = 20nS
- 100 tasks to be executed
- 1 task in non-pipelined system;
20*4 = 80nS P1 P2 P3 P4

Pipelined System
(k + n - 1)*tp
= (4 + 99) * 20 = 2060nS

Non-Pipelined System
n*k*tp = 100 * 80 = 8000nS Multiple Functional Units in parallel
Speedup
Sk = 8000 / 2060 = 3.88

4-Stage Pipeline is basically identical

to the system with 4 identical
function units
 Arithmetic Pipeline

ARITHMETIC PIPELINE
Floating-point adder Exponents Mantissas
a b A B

X = A x 2a
R R
Y = B x 2b
Compare Difference
Segment 1: exponents
by subtraction

Segment 2: Choose exponent Align mantissa

Add or subtract
X = 0.9504 x 103 Segment 3:
mantissas
Y = 0.8200 x 102
R R
[1] Compare the exponents
[2] Align the mantissa
[3] Add/sub the mantissa Segment 4: Adjust Normalize
exponent result
[4] Normalize the result

X = 0.9504 x 103 Z =X+Y R R

Y = 0.0820 x 103 = 1.0324 x 103

= 0.10324 x 104
 Arithmetic Pipeline

4-STAGE FLOATING POINT ADDER

A = a x 2p B = b x 2q
p a q b

Stages: Other
Exponent fraction Fraction
S1 subtractor selector
Fraction with min(p,q)
r = max(p,q)
Right shifter
t = |p - q|

S2 Fraction
adder Overflow then mantissa shifted right
r c and exponent incremented by one

Leading zero
S3 counter
c
Underflow then mantissa shifted left
Left shifter
r and exponent decremented
(determined by leading zeros)
d
Exponent
S4 adder

s d
C = A + B = c x 2r = d x 2s
(r = max (p,q), 0.5  d < 1)
 Instruction Pipeline

INSTRUCTION CYCLE

Six Phases* in an Instruction Cycle

[1] Fetch an instruction from memory
[2] Decode the instruction
[3] Calculate the effective address of the operand
[4] Fetch the operands from memory
[5] Execute the operation
[6] Store the result in the proper place

* Some instructions skip some phases

* Effective address calculation can be done in the part of the decoding phase

* Storage of the operation result into a register is done automatically in the

execution phase

==> 4-Stage Pipeline

[1] FI: Fetch an instruction from memory

[2] DA: Decode the instruction and calculate the effective address of the
operand
[3] FO: Fetch the operand
[4] EX: Execute the operation
 Instruction Pipeline

INSTRUCTION PIPELINE

Execution of Three Instructions in a 4-Stage Pipeline

Conventional

i FI DA FO EX

i+1 FI DA FO EX

i+2 FI DA FO EX

Pipelined

i FI DA FO EX
i+1 FI DA FO EX
i+2 FI DA FO EX
 Instruction Pipeline

MAJOR HAZARDS IN PIPELINED EXECUTION

Structural hazards(Resource Conflicts)
Hardware Resources required by the instructions in simultaneous
overlapped execution cannot be met
Data hazards (Data Dependency Conflicts)
An instruction scheduled to be executed in the pipeline requires the
result of a previous instruction, which is not yet available

Control hazards
Branches and other instructions that change the PC make the fetch of
the next instruction to be delayed

Hazards in pipelines may make it Pipeline Interlock:

necessary to stall the pipeline Detect Hazards Stall until it is cleared
 STRUCTURAL HAZARDS
• Structural Hazards

• Occur when some resource has not been duplicated enough to allow all
combinations of instructions in the pipeline to execute

Example: With one memory-port, a data and an instruction fetch cannot be

initiated in the same clock

The Pipeline is stalled for a structural hazard

<- Two Loads with one port memory
-> Two-port memory will serve without stall
 Instruction Pipeline

DATA HAZARDS
Data Hazards

Occurs when the execution of an instruction depends on the results of

a previous instructions
ADD R1, R2, R3
SUB R4, R1, R5
Data hazard can be dealt with either hardware techniques or software
technique
Hardware Technique

Interlock
- hardware detects the data dependencies and delays the scheduling
of the dependent instruction by stalling enough clock cycles
Forwarding (bypassing, short-circuiting)
- Accomplished by a data path that routes a value from a source
(usually an ALU) to a user, bypassing a designated register. This
allows the value to be produced to be used at an earlier stage in the
pipeline than would otherwise be possible
Software Technique
Instruction Scheduling(compiler) for delayed load
 FORWARDING HARDWARE
• Example:

• ADD R1, R2, R3

• SUB R4, R1, R5

• 3-stage Pipeline

I: Instruction Fetch
A: Decode, Read Registers, ALU Operations
E: Write the result to the destination register
 Instruction Pipeline

CONTROL HAZARDS
Branch Instructions

- Branch target address is not known until the branch instruction is

completed

- Stall -> waste of cycle times

Dealing with Control Hazards

* Prefetch Target Instruction

* Branch Target Buffer
* Loop Buffer
* Branch Prediction
* Delayed Branch
 Instruction Pipeline

CONTROL HAZARDS
Prefetch Target Instruction
– Fetch instructions in both streams, branch not taken and branch taken
– Both are saved until branch is executed. Then, select the right
instruction stream and discard the wrong stream
Branch Target Buffer(BTB; Associative Memory)
– Entry: Addr of previously executed branches; Target instruction
and the next few instructions
– When fetching an instruction, search BTB.
– If found, fetch the instruction stream in BTB;
– If not, new stream is fetched and update BTB
Loop Buffer(High Speed Register file)
– Storage of entire loop that allows to execute a loop without accessing memory
Branch Prediction
– Guessing the branch condition, and fetch an instruction stream based on
the guess. Correct guess eliminates the branch penalty
Delayed Branch
– Compiler detects the branch and rearranges the instruction sequence
by inserting useful instructions that keep the pipeline busy
in the presence of a branch instruction
 RISC Pipeline

RISC PIPELINE
RISC
- Machine with a very fast clock cycle that
executes at the rate of one instruction per cycle
<- Simple Instruction Set
Fixed Length Instruction Format
Register-to-Register Operations

Instruction Cycles of Three-Stage Instruction Pipeline

Data Manipulation Instructions
I: Instruction Fetch
A: Decode, Read Registers, ALU Operations
E: Write a Register

Load and Store Instructions

I: Instruction Fetch
A: Decode, Evaluate Effective Address
E: Register-to-Memory or Memory-to-Register

Program Control Instructions

I: Instruction Fetch
A: Decode, Evaluate Branch Address
E: Write Register(PC)
 RISC Pipeline

DELAYED LOAD
LOAD: R1  M[address 1]
LOAD: R2  M[address 2]
ADD: R3  R1 + R2
STORE: M[address 3]  R3
Three-segment pipeline timing
Pipeline timing with data conflict

clock cycle 1 2 3 4 5 6
Load R1 I A E
Load R2 I A E
Add R1+R2 I A E
Store R3 I A E

Pipeline timing with delayed load

clock cycle 1 2 3 4 5 6 7
Load R1 I A E
The data dependency is taken
Load R2 I A E care by the compiler rather
NOP I A E than the hardware
Add R1+R2 I A E
Store R3 I A E
 RISC Pipeline

DELAYED BRANCH
Compiler analyzes the instructions before and after the branch and
rearranges the program sequence by inserting useful instructions in the
delay steps

Using no-operation instructions Program Consist of 5 instruction

1. Load from memory into R1
Clock cycles: 1 2 3 4 5 6 7 8 9 10
2. Increment R2
1. Load I A E
3. Add R3 to R4
2. Increment I A E
4. Subtract R5 from R6
3. Add I A E 5. Branch to address X
4. Subtract I A E
5. Branch to X I A E
6. NOP I A E
7. NOP I A E
8. Instr. in X I A E

Rearranging the instructions

Clock cycles: 1 2 3 4 5 6 7 8
1. Load I A E
2. Increment I A E
3. Branch to X I A E
4. Add I A E
5. Subtract I A E
6. Instr. in X I A E
 Vector Processing

VECTOR PROCESSING

Vector Processing Applications

• Problems that can be efficiently formulated in terms of vectors
– Long-range weather forecasting
– Petroleum explorations
– Seismic data analysis
– Medical diagnosis
– Aerodynamics and space flight simulations
– Artificial intelligence and expert systems
– Mapping the human genome
– Image processing

Vector Processor (computer)

Ability to process vectors, and related data structures such as matrices
and multi-dimensional arrays, much faster than conventional computers

Vector Processors may also be pipelined

 Vector Processing

VECTOR PROGRAMMING

Fortran DO loop DO 20 I = 1, 100

20 C(I) = B(I) + A(I)

Conventional computer

Initialize I = 0
20 Read A(I)
Read B(I)
Store C(I) = A(I) + B(I)
Increment I = i + 1
If I  100 goto 20

Vector computer

C(1:100) = A(1:100) + B(1:100)

 Vector Processing

VECTOR INSTRUCTION FORMAT

Vector Instruction Format

Operation Base address Base address Base address Vector
code source 1 source 2 destination length

Pipeline for Inner Product

Source
A

Source Multiplier Adder

B pipeline pipeline
 Vector Processing

MULTIPLE MEMORY MODULE AND INTERLEAVING

Multiple Module Memory

Address bus
M0 M1 M2 M3

AR AR AR AR

Memory Memory Memory Memory

array array array array

DR DR DR DR

Data bus

Address Interleaving

Different sets of addresses are assigned to different memory modules

 Vector Processing

Array Processor and its Types

• Array processors are also known as multiprocessors or vector processors. They
perform computations on large arrays of data. Thus, they are used to improve the
performance of the computer.

• There are basically two types of array processors:

1. Attached Array Processors
2. SIMD Array Processors

• An attached array processors is an auxiliary processor attached to

general-purpose computer.

• The main purpose of Attached Array Processors is enhance the

performance of the computer by providing vector processing for complex
scientific applications.

• An SIMD array processors manipulates vector instructions by means of

multiple functional units responding to a common instruction.
 Vector Processing

Attached Array Processors

• An attached array processor is a processor which is attached to a
general purpose computer and its purpose is to enhance and improve
the performance of that computer in numerical computational tasks.

• It achieves high performance by means of parallel processing with

multiple functional units.
 Vector Processing

SIMD Array Processors

Scalar and program control instruction are directly executed within the master control unit
 Vector Processing

SIMD Array Processors

• SIMD is the organization of a single computer containing multiple
processors operating in parallel. The processing units are made to
operate under the control of a common control unit, thus providing a
single instruction stream and multiple data streams.

• The master control unit controls all the operations of the processor
elements. It also decodes the instructions and determines how the
instruction is to be executed.

• The main memory is used for storing the program. The control unit is
responsible for fetching the instructions. Vector instructions are send to
all PE's simultaneously and results are returned to the memory.

• SIMD processors are highly specialized computers. They are only

suitable for numerical problems that can be expressed in vector or
matrix form and they are not suitable for other types of computations.

• The best known SIMD array processor is the ILLIAC IV computer

developed by the Burroughs corps.