82C82

March 1997 CMOS Octal Latching Bus Driver

Features Description
• Full Eight-Bit Parallel Latching Buffer The Intersil 82C82 is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon
• Bipolar 8282 Compatible
gate CMOS process (Scaled SAJI IV). The 82C82 provides
• Three-State Noninverting Outputs an eight-bit parallel latch/buffer in a 20 pin package. The
active high strobe (STB) input allows transparent transfer of
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max. data and latches data on the negative transition of this sig-
• Gated Inputs: nal. The active low output enable (OE) permits simple inter-
- Reduce Operating Power face to state-of-the-art microprocessor systems.
- Eliminate the Need for Pull-Up Resistors Ordering Information
• Single 5V Power Supply
PART NUMBER TEMP. RANGE PACKAGE PKG. NO.
• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA CP82C82 0oC to +70oC 20 Ld PDIP E20.3
• Operating Temperature Ranges IP82C82 -40oC to +85oC
- C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC CS82C82 0oC to +70oC 20 Ld PLCC N20.35

- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC IS82C82 -40oC to +85oC

CD82C82 0oC to +70oC 20 Ld CERDIP F20.3
- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
ID82C82 -40oC to +85oC
MD82C82/B -55oC to +125oC
8406701RA SMD #
MR82C82/B -55oC to +125oC 20 Pad CLCC J20.A
84067012A SMD #

Pinouts
82C82 (PDIP, CERDIP) 82C82 (PLCC, CLCC)
TOP VIEW TOP VIEW
TRUTH TABLE

STB OE DI DO
DO0
VCC
DI2

DI1

DI0

X H X Hi-Z
3 2 1 20 19
DI0 1 20 VCC H L L L

DI1 H L H H
2 19 DO0
DI3 4 18 DO1 ↓ L X †
DI2 3 18 DO1
DI4 5 17 DO2 H = Logic One
DI3 4 17 DO2
L = Logic Zero
DI4 5 16 DO3 DI5 6 16 DO3 X = Don’t Care
† = Latched to Value of Last
DI5 6 15 DO4 DI6 7 15 DO4 Data
DI6 7 14 DO5 Hi-Z = High Impedance
DI7 8 14 DO5
↓ = Neg. Transition
DI7 8 13 DO6
PIN NAMES
OE 9 12 DO7
9 10 11 12 13
GND 10 11 STB PIN DESCRIPTION
GND

STB

DO7

DO6
OE

DI0-DI7 Data Input Pins

DO0-DO7 Data Output Pins
STB Active High Strobe
OE Active Low Output
Enable

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 2975.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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 82C82

Functional Diagram

DIO D Q DO0
CLK

DI1 DO1

DI2 DO2

DI3 DO3

DI4 DO4

DI5 DO5

DI6 DO6

DI7 DO7

STB OE

Gated Inputs
During normal system operation of a latch, signals on the bus DC input voltage levels can also cause an increase in ICC if
at the device inputs will become high impedance or make these input levels approach the minimum VIH or maximum
transitions unrelated to the operation of the latch. These unre- VIL conditions. This is due to the operation of the input cir-
lated input transitions switch the input circuitry and typically cuitry in its linear operating region (partially conducting
cause an increase in power dissipation in CMOS devices by state). The 82C8X series gated inputs mean that this condi-
creating a low resistance path between VCC and GND when tion will occur only during the time the device is in the trans
the signal is at or near the input switching threshold. Addition- parent mode (STB = logic one). ICC remains below the max-
ally, if the driving signal becomes high impedance (“float” con- imum ICC standby specification of l0mA during the time
dition), it could create an indeterminate logic state at the input inputs are disabled, thereby, greatly reducing the average
and cause a disruption in device operation. power dissipation of the 82C8X series devices
The Intersil 82C8X Series of bus drivers eliminates these con-
Typical 82C82 System Example
ditions by turning off data inputs when data is latched (STB =
logic zero for the 82C82/83H) and when the device is disabled In a typical 80C86/88 system, the 82C82 is used to latch
(OE = logic one for 82C86H/87H). These gated inputs dis- multiplexed addresses and the STB input is driven by ALE
connect the input circuitry from the VCC and ground power (Address Latch Enable) (see Figure 3). The high pulse width
supply pins by turning off the upper P-channel and lower N- of ALE is approximately 100ns with a bus cycle time of
channel (see Figures 1, 2). No new current flow from VCC to 800ns (80C86/88 at 5MHz). The 82C82 inputs are active
GND occurs during input transitions and invalid logic states only 12.5% of the bus cycle time. Average power dissipation
from floating inputs are not transmitted. The next stage is held related to input transitioning is reduced by this factor also.
to a valid logic level internal to the device.

VCC

VCC VCC

P P

P
OE P

STB N INTERNAL
P DATA IN DATA
VCC
INTERNAL
DATA IN DATA N
P
N
N

N N

FIGURE 16. 82C82/83H FIGURE 17. 82C86H/87H GATED INPUTS

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Application Information
Decoupling Capacitors
The transient current required to charge and discharge the where tR = 20ns, VCC = 5.0V, CL = 300pF on each of eight
300pF load capacitance specified in the 82C82 data sheet is outputs.
determined by: -12 –9
I = ( 8 x 300 x 10 )x (5.0V x 0.8)/ ( 20 x 10 ) = 480mA (EQ. 4)
I = C L (dv/dt) (EQ. 1)
This current spike may cause a large negative voltage spike
Assuming that all outputs change state at the same time and
on VCC, which could cause improper operation of the device.
that dv/dt is constant;
To filter out this noise, it is recommended that a 0.1µF
I = CL (EQ. 2) ceramic disc decoupling capacitor be placed between VCC
and GND at each device, with placement being as near to
( V CC x 80% ) (EQ. 3)
----------------------------------- the device as possible.
tR/tF

VCC VCC

ALE N
STB P
MULTIPLEXED
BUS ADDRESS ADDRESS INTERNAL
DATA IN DATA

ICC N

FIGURE 18. SYSTEM EFFECTS OF GATED INPUTS

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 82C82

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Thermal Resistance (Typical) θJA θJC
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to VCC +0.5V CERDIP . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W 18oC/W
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 CLCC. . . . . . . . . . . . . . . . . . . . . . . . . . 85oC/W 22oC/W
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . 75 N/A
Operating Conditions PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . 75 N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65oC to +150oC
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Maximum Junction Temperature
Operating Temperature Range
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
C82C82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC
I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Minimum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
M82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
(PLCC Lead Tips Only)

Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

DC Electrical Specifications VCC = 5.0V ±10%; TA = 0oC to +70oC (C82C82);

TA = -40oC to +85oC (I82C82);
TA = -55oC to +125oC (M82C82)

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH Logical One Input Voltage 2.0 - V C82C82, I82C82 (Note 1)

2.2 - V M82C82 (Note 1)

VIL Logical Zero Input Voltage - 0.8 V

VOH Logical One Output Voltage 2.9 - V IOH = -8mA, OE = GND

VCC -0.4V - V IOH = -100µA, OE = GND

VOL Logical Zero Output Voltage - 0.4 V IOL = 8mA, OE = GND

II Input Leakage Current -1.0 1.0 µA VIN = GND or VCC, DIP Pins 1-9, 11

IO Output Leakage Current -10.0 10.0 µA VO = GND or VCC, OE ≥ VCC -0.5V

DIP Pins 12-19

ICCSB Standby Power Supply Cur- - 10 µA VIN = VCC or GND, VCC = 5.5V, Outputs Open
rent

ICCOP Operating Power Supply - 1 mA/MHz TA = +25oC, VCC = 5V, Typical (See Note 2)
Current

NOTES:
1. VIH is measured by applying a pulse of magnitude = VIH min to one data input at a time and checking the corresponding device output
for a valid logical “1” during valid input high time. Control pins (STB, OE) are tested separately with all device data input pins at VCC -0.4.
2. Typical ICCOP = 1mA/MHz of STB cycle time. (Example: 5MHz µP, ALE = 1.25MHz, ICCOP = 1.25mA).

Capacitance TA = +25oC

SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS

CIN Input Capacitance 13 pF Freq = 1MHz, all measurements are

referenced to device GND
COUT Output Capacitance 20 pF

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 82C82

AC Electrical Specifications VCC = 5.0V ±10%; TA = 0oC to +70oC (C82C82);

CL = 300pF (Note 1), Freq = 1MHz TA = -40oC to +85oC (I82C82);
TA = -55oC to +125oC (M82C82)

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

(1) TIVOV Propagation Delay Input to Output - 35 ns Notes 2, 3

(2) TSHOV Propagation Delay STB to Output - 55 ns Notes 2, 3

(3) TEHOZ Output Disable Time - 35 ns Notes 2, 3

(4) TELOV Output Enable Time - 50 ns Notes 2, 3

(5) TIVSL Input to STB Setup Time 0 - ns Notes 2, 3

(6) TSLIX Input to STB Hold Time 25 - ns Notes 2, 3

(7) TSHSL STB High Time 25 - ns Notes 2, 3

(8) TR, TF Input Rise/Fall Times - 20 ns Notes 2, 3

NOTES:
1. Output load capacitance is rated at 300pF for ceramic and plastic packages.
2. All AC parameters tested as per test circuits and definitions below. Input rise and fall times are driven at 1ns/V.
3. Input test signals must switch between VIL - 0.4V and VIH +0.4V.

Timing Waveforms
TR, TF (8)

2.0V
INPUTS
0.8V
TIVSL (5) TSLIX
(6)

STB

TSHSL (7)

OE

TIVOV
(1) TEHOZ (3) TELOV (4)
VOH -0.1V 2.4V
OUTPUTS 0.8V
VOL +0.1V
TSHOV (2)

Test Load Circuits

1.7V 0.6V 3.3V

150Ω 300Ω 300Ω

TEST TEST TEST
OUTPUT POINT OUTPUT POINT OUTPUT POINT

300pF 50pF 50pF

(NOTE) (NOTE) (NOTE)

TIVOV, TSHOV, TELOV TEHOZ OUTPUT HIGH DISABLE TEHOZ OUTPUT LOW DISABLE

NOTE: Includes stray and jig capacitance.

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 82C82

Burn-In Circuits
MD82C82 CERDIP
VCC
C1
R1
F2 1 20
R1
F2 2 19 A
R1
F2 3 18 A
R1
F2 4 17 A
R1
F2 5 16 A VCC
R1
F2 6 15 A
R1
F2 7 14 A R2
R1
F2 8 13 A
R1 A
F0 9 12 A
R1
F1 R2
10 11

MR82C82 CLCC
VCC C1

F2 F2 F2 VCC/2
R3 R3 R3 R3

3 2 1 20 19
R3 R3
F2 4 18 VCC/2
R3 R3
F2 5 17 VCC/2
R3 R3
F2 6 16 VCC/2
R3 R3
F2 7 15 VCC/2
R3 R3
F2 8 14 VCC/2

9 10 11 12 13
R3 R3 R3 R3

F0 F1 VCC/2 VCC/2

NOTES:
1. VCC = 5.5 ± 0.5V, GND = 0V.
2. VIH = 4.5V ±10%.
3. VIL = -0.2V to 0.4V.
4. R1 = 47kΩ ±5%.
5. R2 = 2.0kΩ ±5%.
6. R3 = 4.2kΩ ±5%.
7. R4 = 470kΩ ±5%.
8. C1 = 0.01µF minimum.
9. F0 = 100kHz ±10%.
10. F1 = F0/2, F2 = F1/2.

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 82C82

Die Characteristics
DIE DIMENSIONS: GLASSIVATION:
118.1 x 92.1 x 19 ±1mils Type: SiO2
Thickness: 8kÅ ±1kÅ
METALLIZATION:
Type: Si - Al WORST CASE CURRENT DENSITY:
Thickness: 11kÅ ±1kÅ 2.00 x 105 A/cm2

Metallization Mask Layout

82C82

D11 D10 VCC DO0 D01

2 1 20 19 18

D12 3

17 DO2

16 DO3
D13 4

D14 5
15 DO4

14 DO5

D15 6

13 DO6
D16 7

8 9 10 11 12

D17 OE GND STB DO7

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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