8

Precision Techniques

As data conversion interfaces are designed for higher precisions, the nonide-
alities that accompany monolithic devices become more problematic. Effects
such as mismatch, nonlinearity, and finite intrinsic gain limit the "raw" res-
olution to approximately 6 bits in CMOS technology and 10 bits in bipolar
technology. For higher resolutions, it is often necessary to correct for these
effects by means of circuit or algorithmic techniques. Such techniques are
applied to individual building blocks to improve their precision, as well as to
the overall architecture to make its input/output characteristic approach the
ideal. In addition to the regular mode of operation, circuits employing some of
these techniques typically require a dedicated period to carry out cancellation
or calibration, thereby complicating the system's timing scheme.
In this chapter, we describe a number of methods often used to enhance
the precision or "relax the speed-precision trade-offs of data acquisition sys-
tems. These include comparator and op amp offset cancellation, DAC and
ADC calibration, and range overlap with digital correction.

8.1 COMPARATOR OFFSET CANCELLATION

The resolution limitations discussed in Chapter 7 for comparators mandate
offset cancellation in high-precision systems. This is particularly crucial in
pure CMOS circuits because of the large mismatches of MOS devices and is
also important in bipolar and BiCMOS circuits if resolutions above 10 bits
are required.

198
Sec. 8.1 Comparator Offset Cancellation 199

Traditionally, laser wafer trimming and fuse techniques have been used
in bipolar circuits to cancel offsets [1]. However, these techniques suffer from
several drawbacks: substantial area and cost penalty, failure to maintain the
cancellation over temperature and time, and sensitivity to package stress. Fur-
thermore, these methods cannot be easily applied to CMOS circuits because
the large offsets of MOS transistors require a much wider correction range
than do their bipolar counterparts.
The need for reliable offset cancellation has led to autozeroing tech-
niques in CMOS and BiCMOS comparators, wherein the offset is periodically
sensed, stored, and added to the input in such a way as to cancel itself. Of
the variety of comparator offset cancellation techniques [2, 3, 4], we discuss
four here. The general architecture using any of these techniques is similar
to that of Figure 7.19, consisting of a preamplifier and a latch. Each circuit
has three modes of operation: offset cancellation, tracking, and latching. The
challenge is to minimize the input offset contributed by the preamp and the
latch without compromising other aspects of the performance.
8.1.1 Input Offset Storage
This technique (denoted by lOS) measures the input offset of the pream-
plifier by closing a unity-gain feedback loop around it and stores the resulting
offset on capacitors in series with the input. Figure 8.1 depicts a configura-
tion employing this technique. The circuit operates as follows. During offset
cancellation, SI-S4 are on, Ss and S6 are off, nodes A and B are grounded,
a unity-gain feedback loop is established around Ao, and the input offset is
stored on CI and C2. During tracking, SI-S4 are off, S5 and S6 are on, the feed-
back loop is open, and the preamplifier senses the analog input and amplifies
the difference. In the latching mode, the latch is strobed so as to regeneratively
amplify the difference produced at the preamplifier output, hence providing
logic levels at VOUl •
The residual offset (the offset after cancellation) of this topology can
be calculated as follows. For the feedback circuit in the offset cancellation
mode, we have

(8.1)

where VOSA is the input offset of the preamplifier. Thus,

Ao
VXY = VasA. (8.2)
1+ Ao
This voltage is stored on Cl and C2. When the feedback loop opens, the
preamplifier output remains the same if S3 and S4 exhibit perfect matching.
200 Precision Techniques Chap. 8

x Latch Vout
y

Fig. 8.1 Input offset storage.

Therefore, for a zero difference at the comparator input, the preamplifier

output is approximately equal to VasA. In contrast, if there were no offset
cancellation, the preamplifier output would be equal to AoVasA. Thus, lOS
reduces the effect of the preamplifier offset by approximately a factor of Ao.
In addition to VOSA, the latch offset, VOSL , and charge injection mismatch
between S3 and S4, Sq, contribute to the comparator input offset. Of these
two, VOSL is divided by Ao when referred to the input, whereas ~q appears
directly at the input, yielding a total offset of

VOSA ~q VOSL
VOS(IOI) = 1 + Ao + C + Ao ' (8.3)

where C is the value of Cl and C2 (assumed equal here).

The lOS topology has two important features. First, it allows a rail-to-
rail common-mode level at the comparator input (when using complementary
MOS switches for 85 and S6), thereby achieving a wide dynamic range. Sec-
ond, it performs the cancellation in a closed loop, thus driving the preamplifier
to its active region as well as augmenting its overdrive recovery,
Despite these features, lOS suffers from several drawbacks. The offset
contributed by the preamplifier can be reduced only by employing a high gain,
degrading the power-speed trade-off. Furthermore, since the value of input
coupling capacitors is dictated by charge injection mismatch, kT / C noise,
and attenuation considerations, Cl and C2 (and hence their parasitics) are
usually quite large. Note that a large input capacitance not only slows down
the preceding circuit (e.g., the front-end sample-and-hold amplifier) but also
introduces a substantial amount of noise at the input when the circuit enters
the tracking mode and nodes A and B must charge to proper voltages. This
issue is particularly important if many comparators are connected to a resistor
ladder.
Sec. 8.1 Comparator Offset Cancellation 201

8.1.2 Output Offset Storage

This technique (denoted by ODS) measures the output-referred offset of
the preamplifier by grounding its inputs and stores the result on capacitors in
series with the preamplifier output. Illustrated in Figure 8.2, OOS operates as
follows. During offset cancellation, nodes A, B, X, and Yare grounded and
the preamplifier offset is amplified and stored on CI and C2. In the tracking
mode, St-S4 tum off and Ss and S6 tum on. The circuit thus senses and
amplifies the input difference, generating a differential voltage at the input of
the latch. Next, in the latching mode, the latch is strobed to amplify its input
voltage and produce logic levels at Vout '

Latch Vout

Fig. 8.2 Output offset storage.

To calculate the residual offset of DOS, first note that in the cancellation
mode, the latch input voltage is zero; i.e., a zero difference at the comparator
input gives a zero difference at the latch input. Consequently, the offset of the
preamplifier is completely canceled, a feature in contrast with lOS. Thus, the
total offset results from only the charge injection mismatch between 53 and
54 and the latch offset:
~q VOS L
VOS(IOI) = AoC + Ao . (8.4)

Note that the effect of charge injection mismatch is divided by Ao, another
advantage of 005 over lOS.
In addition to a potentially lower offset, OOS usually exhibits less input
capacitance than 105 and is therefore more suitable for parallel ADC archi-
tectures. However, it suffers from two drawbacks that do not exist in IDS.
Since the preamplifiers used in 005 are open loop, they cannot employ high
gain. This is because, in the cancellation mode, the preamplifier may satu-
rate if the product of its input offset and its gain exceeds the maximum voltage
202 Precision Techniques Chap. 8

swing allowed at its output. As a consequence, OOS typically incorporates a

single-stage amplifier with a gain less than 20.
The other drawback of OOS stems from dc coupling at its input and
hence limited input common-mode range. This is in contrast with lOS, where
rail-to-rail inputs can be accommodated.
8.1.3 Multistage Offset Storage
From the discussion in the previous section it follows that for high res-
olutions a single stage of OOS is inadequate, while a single stage of lOS
with high gain suffers from a long delay. These considerations have led to
the use of multistage cancellation techniques in high-resolution comparators
[2,4].
Figure 8.3 illustrates a typical multistage cancellation scheme. The
circuit comprises a cascade of capacitively coupled amplifiers followed by a
latch. In this example, all amplifiers use OOS, but IDS or a combination of
both are also possible. Since the equivalent gain of the overall amplifier is the
product of the gains of individual stages, a high gain with fast response can
be achieved. The circuit operates as follows . In the offset cancellation mode,
the inputs of A I, ..... , An and the latch are grounded, and the offset of each
amplifier is stored on capacitors in series with its outputs. In the tracking
mode, the input difference is sensed and amplified by A I , ..... , An. In the
latching mode, the latch is strobed to produce logic levels at Vout -

Fig. 8.3 Multistage offset cancellation.

In the circuit of Figure 8.3, the input offset resulting from the latch is
equal to
VOSL
Vos = . (8.5)
AJ A 2 · .. An
The number of stages used in this approach depends on the overall gain re-
quired to suppress Vas below a certain value. For a given gain, n can be
calculated so as to achieve the maximum bandwidth [4], but in practice it is
between 2 and 4.
Sec. 8.1 Comparator Offset Cancellation 203

An important source of error was neglected in the above discussion:

channel charge injection mismatch of switches SII-S2n. Depending on their
exact tum-off timing, these switches may contribute to the input offset in the
transition from cancellation to tracking. For example, if SII and 521 turn
off slightly later than others, their channel charge mismatch introduces an
uncanceled offset at the input of A2. To minimize this type of error, the
comparator can utilize sequential clocking [2], wherein the gain stages leave
the offset cancellation mode sequentially, A I first and An last.
Figure 8.4 illustrates this timing arrangement. When C K I goes low,
AI leaves the cancellation mode, whereas A2, ... , An are still in that mode.
Consequently, the offset due to charge injection mismatch of Sit and S21 is
amplified by A2 and stored on the capacitors at its output. In other words,
during this interval A2 acts as an OOS stage and hence reduces its residual
offset to zero. Next, C K2 goes low while C K3' ... , C K; are still high,
allowing the offset due to charge injection mismatch of Sl2 and S22 to be
canceled by the following stage. This sequence continues until C K; goes
low. Thus, the error due to charge injection mismatch of all the switches
except SIn and S2n is canceled.

CK n
CKo

Fig. 8.4 Sequential clocking in multistage comparators.

In designing a multistage comparator, two issues should be considered.

First, the delay between the edges of C K I, ... , C K n should be long enough to
allow complete offset storage on the following capacitors. Figure 8.5 depicts
typical resistive paths for the offset storage capacitors. With 005, the total
resistance in series with Ci] is Roj + Ron,j, where Roj is the open-loop output
204 Precision Techniques Chap. 8

resistance of Aj and Ron,j is the on-resistance of switch Si]. With lOS, the
total resistance is Roj + Ron,j/Aj+1 + Ro(j+I), where Ro(i+l) is the closed-
loop output impedance of Aj+ 1 when configured as a unity-gain feedback
amplifier. The resulting time constant in each case imposes a lower bound on
the delay between C K j and C Kj+l.

(a) (b)

Fig. 8.5 Resistive paths associated with offset storage capacitors in a multi-
stage comparator. (a) DOS; (b) IDS.

The second issue relates to the error voltage introduced by charge in-
jection and clock feedthrough when each stage leaves the offset cancellation
mode. If the product of this voltage and the gain of a stage is excessively large,
the amplifier in that stage is driven out of its active region, hence exhibiting a
much lower gain.
Multistage comparators have been implemented in several forms [2, 4.,
5]. A simple approach is illustrated in Figure 8.6, where CMOS inverters
operate as amplifiers, with lOS applied to all the stages [5]. The simplicity of
this configuration has made it quite popular in the resolution range of 8 to 10
bits [6, 7]. An important feature of this topology is its scalability with lower
supply voltages, essentially the same as digital CMOS circuits. For example,
a 10-bit ADC [7] utilizes such stages extensively to allow operation from 2.5
V with a total power dissipation of 30 mW at 20 MHz.

"I>-.......- - - --1 Latch f--o Vout

Fig. 8.6 Multistage offset cancellation using CMOS inverters.

This approach nonetheless suffers from several drawbacks. The single-

ended operation raises serious concerns regarding charge injection error and
Sec.8.l Comparator Offset Cancellation 205

supply rejection ratio. In order to ensure that the inverters remain in their
high-gain region after the feedback switches turn off, the coupling capaci-
tors must be quite large. Furthermore, the output voltage of each inverter is
very sensitive to supply noise because the small-signal input/output gain of
inverters is on the same order as the gain from the supply line to their output.
In addition, the power dissipation of the circuit is strongly process- and
supply-dependent because it is given primarily by the bias current of inverters
when their feedback switches are on, i.e., the current drawn from the supply
by two diode-connected MOSFETs in series. Also, as mentioned for lOS, the
large capacitance and switching noise seen at the input of this topology give
rise to long settling times and are particularly detrimental in flash architectures.
Multistage comparators can also be implemented in fully differential
form through the use of differential amplifiers. In contrast with the topology
of Figure 8.6, differential circuits are much less sensitive to common-mode
effects such as charge injection and supply variation.
Figure 8.7(a) shows a simple CMOS differential pair used in differential
comparators. For square-law devices, the gain of this circuit has a square root
dependence on device size and is usually limited to less than 10 for reasonable
device dimensions. Thus, it is well-suited to OOS. To achieve a higher gain,
the load circuit can be modified as shown in Figure 8.7(b), where current
sources II and /2 provide a major portion of the current drawn by M 1 and M2
[4]. Since the bias current of M3 and M4 is less than that of MI and M2, the
gain can be made higher than that in Figure 8.7(a). In practice, II and /2 track
/55 within a few percent. As a safe choice, /1 = 12 = 0.75(0.5/ss). so that
M3 and M4 do not "starve" in the presence of tracking and mismatch errors.
Another approach to increasing the gain is to incorporate positive feed-
back with controlled loop gain [8]. Illustrated in Figure 8.7(c), this technique
configures the load devices such that they boost the gain without entering
latch-up. The overall gain of this circuit is equal to

_ gml2 I
A v- , (8.6)
gm34 1- gm56/ gm34

where the second fraction represents the gain resulting from positive feedback.
Since gm56/gm34 is defined only by the ratio of PMOS device dimensions, it
can be controlled quite tightly. For example, with WS6/ W34 = 3/4 and
L56 = L34, we have /D56/ID34 =3/4, and positive feedback boosts the gain
by a factor of 4.
While multistage comparator topologies achieve a small input offset,
they also pose several problems. First, they suffer from strong trade-off among
gain, bandwidth, and power dissipation, often trading the latter two for a
206 Precision Techniques Chap. 8

-.
(a)

,.....--.....- - - - - . - -......... VDD

(b) (c)
Fig.8.7 (a) CMOS differential pair; (b) gain boosting using current sources;
(c) gain boosting using positive feedback.

high gain to ensure adequate resolution. This is especially acute if the latch
exhibits large offsets. Second, the complexity of these comparators and their
clocking sequence make them difficult to use in flash or two-step ADCs. Third,
the sequential clocking required to suppress the effect of charge injection
mismatch both imposes a lower bound on the clock period and faces timing
skew issues when clocks must be distributed on a large chip.
8.1.4 Comparators Using Offset-Canceled Latches
The problems described for multistage comparators can be substantially
alleviated if the offset of the latch is reduced in a reliable way. With a lower
latch offset, the preamplifier need not have a high gain and can therefore be
optimized for speed and power dissipation. In this section, we describe a com-
parator architecture that applies offset cancellation to both the preamplifier
and the latch.
Sec. 8.1 Comparator Offset Cancellation 207

Figure 8.8 depicts a simplified block diagram of the comparator [3]. It

consists of transconductance amplifiers G m I and G m2, load resistors R L I and
R L2, and capacitors eland C2 placed in a positive feedback loop around G m'I»
In the offset-cancellation mode, the inputs of Gml and G m 2 are grounded and
their offsets are amplified and stored on CI and C2. In the comparison mode,
the inputs are released from ground and the input voltage is sensed. This
voltage is amplified by G m 1 to establish an imbalance at the output nodes and
hence at G m 2 inputs, initiating a fast regeneration around G m 2 .

Fig. 8.8 CMOS comparator with offset-canceled latch.

The calibration of this circuit can be viewed as OOS applied to both G m I

and G m 2 , resulting in complete cancelation of their offsets. The important
difference is that this topology utilizes the offset-canceled amplifier G m 2 for
regeneration, whereas DOS incorporates an explicit latch that can suffer from
a large input offset. Thus, neglecting second-order effects such as charge
injection mismatch of Ss and S6, this configuration accomplishes zero residual
offset while retaining all of the advantages of OOS.
Due to several complications, the configuration of Figure 8.8 is not quite
practical if implemented as such. First, the feedback capacitors and their par-
asitics load the output nodes, reducing the speed. Second, because of the
finite on-resistance of Ss and S6, the positive feedback loop around G m 2 is not
completely broken in the calibration mode, making the circuit prone to oscil-
lation. More importantly, when Ss and S6 turn off to end the calibration, any
mismatch in their charge feedthrough can trigger a false regeneration around
G m 2 . Since the feedback is designed for a fast response, this regeneration
cannot be overridden by small voltages at the input, hence causing a large
input-referred offset. Figure 8.9 illustrates a modified block diagram of the
comparator that circumvents these problems. In this circuit, buffers BI and
82 isolate nodes A and B from the feedback capacitors, while switches S7-S10
disable the feedback loop when required. Regeneration then begins only after
the input voltage has been sensed and amplified.
208 Precision Techniques Chap. 8

Fig. 8.9 Modified version of the circuit in Figure 8.8.

Since this configuration calibrates both the preamplifier and the latch,
its residual offset is primarily caused by charge feedthrough mismatch of
switches SS-SIO. The resulting errors are discussed in [3].

8.2 OP AMP OFFSET CANCELLATION

Pipelined NO converters often require precision op amps to perform inter-
stage sampling, subtraction, and amplification [9]. The input-referred offset of
these op amps gives rise to differential nonlinearity and must remain well be-
low 1 LSB, usually mandating offset cancellation in high-resolution systems.
The major concern in cancelling the offset of an op amp, unlike that of
an open-loop circuit such as a comparator, is the phase margin degradation
caused by the cancellation circuit, in particular the offset storage capacitors.
While some of the offset cancellation techniques described for comparators in
previous sections may be applied to op amps [10], they substantially degrade
the closed-loop settling behavior by introducing capacitors in the signal path,
Le., by adding more nondominant poles to the circuit. Since the minimum size
of these capacitors (and their parasitics) is dictated by charge injection mis-
match and kT/ C noise, the magnitude of these poles may not be sufficiently
large, thus increasing the settling time markedly.
A more efficient approach is to use an auxiliary amplifier that isolates
the signal path from offset storage capacitors while canceling the offset of the
main amplifier [11].
A possible implementation of this concept is illustrated in Figure 8.10,
where a transconductance amplifier Gml and a transresistance amplifier R
constitute the main amplifier and another transconductance amplifier G m 2
performs offset cancellation. The circuit operates as follows. During offset
cancellation, SJ -S4 are on while 55 and 56 are off, inputs of GmJ are grounded,
Sec. 8.2 Op Amp Offset Cancellation 209

and the G m2 R loop is closed. The op amp offset is thus stored on C) and
C2. During amplification, only Ss and S6 are on and G m 2 simply adds a de
component at the output so as to cancel the op amp offset.

Vout

Fig.8.10 Op amp offset cancellation using an auxiliary amplifier.

To calculate the residual offset of the circuit, we first consider a hypo-

thetical case where the inputs of both Gml and G m 2 are grounded and the
Gm2R loop is open. In that case, the input offsets of Gml and G m2 , denoted
by VOS , I and VOS ,2 , respectively, would be amplified by their respective gains
and appear at the output as GmJ RVos,1 + Gm2RVOS,2. Now, if the Gm2R loop
is closed, negative feedback reduces Vout by a factor of approximately Gm2R:

11 _ GmlRVOs,) + G m 2 R VOS,2 (8.7)

yo~- G 2R ·
m

This is the overall offset voltage of the circuit referred to the output (and is
stored on CI and C2). To find the offset referred to the input of Gmt, (8.7)
should be divided by the gain of the main amplifier G m I R:

Vos = VOS• 1 + VOS,2. (8.8)

Gm 2 R c:»
At the end of offset cancellation, when S3 and S4 turn off, their charge
injection mismatch results in a differential error voltage, ~ V, on CI and C2.
This error appears in series with the input of G m 2 , but it is not corrected
because the Gm2R feedback loop is now open. Thus, ~ V is multiplied by
210 Precision Techniques Chap. 8

G m2 R and divided by G m I R when referred to the main input. The total input
offset voltage is then equal to

V. - VOS.1 + VOS.2 + G m2 ~ V (8.9)

osuoi) - G R G R G .
m2 ml Inl

The three terms in (8.9) impose different constraints on the design of the
op amp. To suppress the first two terms, G,n I, G fnZ, and R must be maximized,
whereas to reduce the last term, GmZ/Gml or ~ V must be minimized. In a
typical design, G m2/ G m 1 ~ 0.1 and ~ V is reduced using large offset storage
capacitors [12].
The topology of Figure 8.10 is easily realized in a folded cascade op
amp, with the G m I and G m2 output current summation occurring at the folding
point. Such an implementation is shown in Figure 8.11, where differential
pairs M 1-M2 and M3-M4 comprise the Gml and G m 2 amplifiers, respectively,
and common-gate transistors M« and M6 along with their loads form the R
amplifier. The ratio of G m I and G m 2 is set by the sizing and biasing of Mt-M4 .

..................................

~ Gm1 •
....................... R

Fig. 8.11 Circuit implementation of topology of Figure 8.10 (common-mode

feedback not shown).
Sec. 8.3 Calibration Techniques 211

Equation (8.9) illustrates the direct dependence of the residual offset

upon the loop gains GmJ Rand Gm2R, predicting design issues in scaled
technologies. For typical short-channel devices, loop gains are smaller, while
offsets tend to be larger. Thus, the residual offset of this topology increases
for small-geometry devices. Since the supply voltage of such circuits must
also scale with technology, the input dynamic range of the op amp is more
limited.

8.3 CALIBRATION TECHNIQUES

Integral linearity of data converters usually depends on the matching and lin-
earity of integrated resistors, capacitors, or current sources, and it is typically
limited to approximately 10 bits with no calibration. For higher resolutions,
means must be sought that can reliably correct nonlinearity errors. This is
often accomplished by either improving the effective matching of individual
devices or correcting the overall transfer characteristics.
8.3.1 DAC Calibration Techniques
Capacitor DACs. As mentioned in Chapter 3, capacitor DACs achieve
both a wide dynamic range and a relatively fast settling and are often utilized
in multistep AID converters. These DACs have been especially popular in
successive approximation architectures, where they are normally configured
as binary-weighted arrays.
We first describe a technique for measuring the mismatch between two
capacitors. Consider the circuit of Figure 8.12. First, S I, S2, and Ss are on,
and hence CI is charged to VREF and C2 is discharged to ground. Next, 51,
S2, and S5 turn off and S3 and S4 tum on so that nodes X and Yexperience
voltage swings equal to - VREF and + VREP , respectively. The change in the
voltage at node P, here called the "residual voltage," can be written as

~V=- VREF C1 + VREF C2 (8.10)

CI +C2 C. +C2

- ~~ ~ ~~ V REF
,
(8.11)

where the charge injected by S5 is neglected. Thus, L\ V is a measure of the

mismatch between CI and C2.
A calibration technique described by Lee [13, 14] is based on measuring
and digitizing the residual voltages obtained for a binary capacitor array and
storing and combining the results digitally. Illustrated in Figure 8.13 in sim-
plified form, this approach employs a main DAC, a calibration DAC (CDAC),
212 Precision Techniques Chap. 8

Fig. 8.12 Measurement of mismatch between two capacitors.

Main DAC
Successive
Approximation
Logic

: VREF
.........................................................
Fig. 8.13 Calibration of a binary-weighted capacitor array.

a precision comparator, and digital logic required for storage and correction.
In the main DAC, Cj = 2 j -I C 1 for j > 1, and capacitor Co, equal to C 1, is
used only during calibration.
Before describing the algorithm utilized in this approach, we should
mention two points regarding the circuit of Figure 8.13. First, for perfectly
matched devices,
k-I
c, = Lej , for 1 < k ~ m, (8.12)
j=O
an important result used to measure capacitor mismatches. Second, it can be
easily proved that the accuracy of the following algorithm is not influenced
by Cca1, input capacitance of the comparator, or top plate parasitics of the
array.
Calibration begins with em and proceeds as follows. Using (8.11)
and (8.12), the mismatch between em and Cm - 1 + ... + Co is represented
as a residual voltage (Vres,m) at node P. Subsequently, the comparator and
CDAC perform a successive approximation routine to digitize Vres,m. This pro-
Sec. 8.3 Calibration Techniques 213

cedure is repeated for the mismatch between Cj and Cj-J + ... + Co for j =
m - 1, ... , 1, thus producing the digital representation of Vres,m-l, • • ., Vres , I.
For a digital input D m Dm-I . · · D], it can be shown [14] that the output
error voltage in the presence of capacitor mismatch is

VREF ~ j-I tiC

Verror = --;;;- £..J 2 ( - )j D j (8.13)
2 j=l C
m
= L v.io; (8.14)
j=1

where (l:1C / C)j denotes the relative mismatch of Cj and

V. .
f)
= VREF2j-l(tlC
2m C )
).. (8.15)

Thus, to find Verror for each input code, all V f j must be calculated. It can also
be shown that
1 m
Vf j = -(Vres,j -
2
L VEk)·
k=j+1
(8.16)

Thus, after every Vtes.] is digitized, a corresponding Vfj is calculated from

(8.16) and stored in the data register. The precise error voltage at the output
for any digital input can then be determined using (8.14).
The primary feature of this algorithm is that it performs calibration using
only adders and simple logic gates, with no need for digital multipliers. In a
typical design, the digital circuitry amounts to approximately 400 gates and
120 bits of RAM [13]. The precision achievable through this technique has
made possible resolutions as high as 18 bits [15].
Another approach to calibrating capacitor DACs measures the mismatch
between each unit capacitor and a "reference" capacitor and corrects the mis-
match by adding small, trimmable capacitors to each unit [17]. This approach
is better described in the context of ADC calibration and is treated in Sec-
tion 8.4.
The above calibration techniques fail to fully correct one type of error:
capacitor nonlinearity. For example, the mismatch measurement illustrated
in Figure 8.12 corrects capacitor nonlinearity only for a capacitor voltage of
VREF because the residual voltage also includes the mismatch between the
value of CI with a voltage of VREF and the value of C2 with a voltage of
zero. However, the nonlinearity corresponding to other voltages across the
capacitors remains.
If the capacitor nonlinearity is reproducible and well-characterized, it is
possible to employ nonlinear function generators that introduce an opposite
214 Precision Techniques Chap. 8

nonlinearity in the input/output characteristic, hence canceling the effect of

the capacitor voltage coefficient [8]. However, it is desirable to avoid the
complexity associated with this technique through the use of fully differential
architectures and highly linear capacitors.
Current-Steering DACs. In order to achieve integrallinearities above
10 bits, it is often necessary to calibrate the current sources of a DAC. Factory
calibration techniques such as laser wafer trimming and fusing are exten-
sively used in industry, but they increase the cost and their precision degrades
with package stress and temperature variation. In contrast, self-calibration
techniques are free from these errors but result in more circuit complexity.
The equivalent matching of current sources can be substantially im-
proved using the concept of "dynamic element matching" [16]. Depicted in
Figure 8.14, this method performs time averaging on nominally equal current
sources /RI and IR2 so as to produce precisely matched currents lout,l and
[out,2. We note that if C K has a duty cycle of exactly 50%, then [out, 1 = I Rl
and lout,2 = I R2 for half of the time and lout, 1 = I R2 and lout,2 = I Rl for the
other half. Thus, both lout, I and lout,2 have an average value of (I R 1 + I R2)/ 2
and are therefore exactly equal. In reality, the clock dutycycle may deviate
from 50% by some amount, ~c K, thereby yielding a total output mismatch of
Illout ~ IRI - IR2
- - = 0CK (8.17)
lout IR

where IRis the mean value of I R 1 and I R2 [16]. Since ~c K can be less than 1%,
this approach improves the matching by more than two orders of magnitude.
As dynamic element matching is based on time averaging, it requires
low-pass filtering of the output currents, e.g., by means of capacitors con-
nected from nodes X and Y in Figure 8.14 to ground. However, unless clock
frequencies of several hundred megahertz are used, these capacitors tend to be
excessively large for on-chip fabrication, an issue that becomes more severe
as the number of averaged outputs increases.
A self-calibration technique for segmented current-steering arrays has
been introduced by Groenveld et a1. [18]. Illustrated in Figure 8.15, this
technique makes each unit current source equal to a reference current source,
thus canceling errors due to mismatches. Each unit in the array consists
of a fixed current source, MI, an adjustable current source, M2, and a hold
capacitor, C H. During calibration, Sl and S2 are on and the gate-source
voltage of M2 is adjusted so that II + /2 = I REF • When SI and S2 turn off,
this voltage is stored on C H , retaining the same 12.
The key point in this circuit is that typical device matching allows M I to
provide approximately 99% of the total current, thereby relaxing the precision
Sec. 8.3 Calibration Techniques 215

x lout,1

y
lout,2
CK···· .
CK .

-. -.
CK
'out,1 I R1 + I R2
...... ~----

'out,2 2

t
Fig. 8.14 Dynamic element matching.

-. -.
Current Cell

Fig. 8.15 Calibration of a current source.

required of /2 by two orders of magnitude. For example, in a 16-bit system,

calibration must trim /2 to only 10 or 11 bits of precision, making the circuit
quite tolerant of errors due to charge injection and feedthrough. Furthermore,
216 Precision Techniques Chap. 8

since /2 is quite small, M2 can be a long device to attain better matching and
lower sensitivity to charge injection at its gate.
In order to make the calibration transparent to the user, a proxy current
cell can be added to the DAC array such that it replaces the cell undergoing
calibration [18].
The circuit of Figure 8.15 nonetheless has two drawbacks. First, since
the adjustable current source has single-ended control (i.e., the gate of M2), it
requires a large value for C H to suppress the effect offeedthrough due to S2. If
this effect were identical for all the cells in the array, then it would simply yield
a constant offset in each source and deviate the full-scale current from its ideal
value, an error that could be corrected by adjusting I REF • However, if random
mismatches and gradients across the chip are significant, feedthrough effects
are not identical, thereby causing nonlinearity. To mitigate this problem, the
adjustable current source can incorporate differential control.
The second drawback is that if II > I REF , calibration fails, implying
that lREF must be skewed to guarantee II ~ I REF • However, since II and [REF
are generated using nonidentical devices (e.g., NMOS and PMOS devices,
respectively), it is difficult to ensure that II is less than [REF by only 1%. A
more practical approach is to employ a bidirectional current source for 12 so
that it can contribute either negative or positive components to II + 12-
Figure 8.16 shows a calibration circuit that satisfies both of the above
requirements. Here, the transconductance amplifier comprising M2-MS and
[55 operates as a bidirectional current source to generate 12. In the calibration
mode, SI-S3 are on and lDt + [D3 - IDS = [REF- When S2 and S3 tum off,
only their charge injection mismatch introduces a small error.
Groenveld describes another implementation of the calibration circuit
[18].
Another approach described by Miller et al. [19] stores the errors digi-
tall y to achieve stable operation over time and temperature without the need for
frequent calibration. Depicted in Figure 8.17, this technique employs a main
DAC (MDAC), a calibration DAC (CDAC), and a sampling DAC (SDAC)
along with control logic and a small memory. In the calibration mode, the
output corresponding to each code is examined and the error is detected and
stored. This operation occurs in two steps. In the first step, an input code D is
applied to the MDAC and the corresponding current cells are switched to node
X. In the ideal case, the output corresponding to the next code D + 1 would
result simply from drawing an additional LSB current from node X _Thus, an
extrapolated value for D + 1 is established at the output by switching an extra
LSB current source, I LSD , to X. Subsequently, the SDAC and the comparator
operate as a successive approximation ADC and reduce the voltage at node
Sec. 8.3 Calibration Techniques 217

...----__---------4t---.. VDD
'REF

-.
-.
Fig. 8.16 Differential bidirectional calibration of a current source.

Main
DAC
Cal.
Logic Cal. lc R
and DAC
Storage
Samplingl-- ~--_ __e y
DAC

-.
Fig. 8.17 Calibration of a current-steering DAC using extrapolation.

Y to zero. In other words, the SDAC samples the (extrapolated) output of the
main DAC.
In the second step, I LSs turns off, and the digital input of the MDAC is
incremented by 1 LSB to generate the actual output corresponding to D + 1.
Next, the CDAC and the comparator successively reduce the voltage of node
218 Precision Techniques Chap. 8

Y to zero, making Vout equal to the value stored in SDAC. As a result, the
difference between the actual output and the extrapolated output is detected
by CDAC and stored digitally. This difference is then used to correct the
output during actual digital-to-analog conversion.
Since the calibration and sampling DACs only measure or correct errors,
their resolution and dynamic range can be quite low. For example, in a 16-bit
system, these DACs require a resolution of approximately 6 bits [19].
8.3.2 ADC Calibration Techniques
Since high-resolution AID converters typically employ multistep archi-
tectures, they often impose two stringent requirements: small INL in their
interstage DACs and precise gain (usually a power of 2) in their interstage
subtractors/amplifiers. These constraints in turn demand correction for device
mismatches if resolutions above 10 bits are required.
In this section, we describe three calibration techniques suited to mul-
tistage ADC architectures. For simplicity, we consider single-ended imple-
mentations, but the actual circuits are fully differential.

Capacitor Error Averaging. In the I-bit-per-stage architecture of Sec-

tion 6.6, rather than subdividing the reference, each stage amplifies the residue
by a precise factor of2. The accuracy of this gain depends on capacitor match-
ing (and op amp gain). In order to suppress the effect of capacitor mismatch,
capacitor error averaging can be used [9, 20].
Figure 8.18 depicts a multiply-by-2 circuit in two modes. In the sampling
mode CI and C2 are charged to \.'in. In the amplification mode, C. is placed
around the amplifier while node X is grounded. For an ideal op amp,

(8.18)

If Cl = C and C2 = C + 6.C, then

(8.19)

thus exhibiting a gain error of ~C / C, typically on the order of 0.1 %.

Now suppose the multiply-by-2 function is repeated but with CI and C2
interchanged. This case is illustrated in Figure 8.19. Then, the output is

(8.20)
Sec. 8.3 Cal i bration Techniques 219

Vout

-.
(a)

Vout

(b)
Fig. 8.18 A multiply-by-2 stage in (a) the sampling mode and (b) the am-
plification mode.

(a)

-. -. (b)
Fig.8.19 Multiply-by-2 stage of Figure 8.18 with C, and C2 interchanged.
220 Precision Techniques Chap. 8

In the capacitor error-averaging technique, the outputs represented by

(8.18) and (8.20) are sampled and averaged to generate

1 Cl C2
Vout,av = 2~n(2 + C2 + C\) (8.21)

1 C2 + C2
~ - V (2 + 1 2). (8.22)
2 an C1C2

We can show that this approach reduces the gain error to a term proportional
to the square of the relative capacitor mismatch. Substituting C I = C and
C2 = C + ~C in (8.22), we have

V. - ~ V; 2 2C 2 + 2C ~C + ~C2
out.av - 2 IO[ + C(C + ~C) ] (8.23)

~C2
~ \lin(2 + 2C2 ). (8.24)

Thus, the gain error can be expressed as

~C2
~Av ~ 2C2' (8.25)

which is typically only a few parts per million.

Figure 8.20 illustrates the amplifier along with an averaging circuit con-
sisting of A2, C3, and C4. Capacitor C3 is nominally half of C4 so as to provide
an overall gain of 0.5 for the averaging circuit [9]. During the first amplifica-
tion mode [Figure 8.20(a)], the output of A) is equal to Vin (1 + C 1/C2) and is
stored on C3 and C4. In the second amplification mode [Figure 8.20(b)], C4 is
placed in a negative feedback loop around A2, and C, and C2 are interchanged
so that the output of A I is equal to \lin(I + C2/ C I ). Thus, Vout.av is equal to
the initial voltage across C4 plus half of the change in the output of A I :

Vout.av
Cl
= - ~n(1 + -) - -1 Vin ( -C2 - CI
-) (8.26)
C2 2 Cl C2
1 C2 C1
= -\lin - 2(C\ + C2)Vin, (8.27)

The negative sign in the output can be taken into account by the following
stage.
Capacitor Trimming. Figure 8.21 (a) shows a 2-bit stage of a pipelined
ADC [17] comprising nominally equal capacitors C l-C4 and C F, and op amp
Sec. 8.3 Calibration Techniques 221

~ oO Vout,av

-. -.
(a)

>-.--0 Vout,av

-.
(b)

Fig. 8.20 Capacitor error-averaging circuit.

A I. During sampling, St-S4 are switched to ~n and SF is on, providing a

virtual ground at the inverting input of AI. Subsequently, DI A conversion,
subtraction, and amplification take place when SF turns off and SI-54 switch
to either VREF or ground according to the thermometer code generated by the
previous stage. The output voltage VOUl is then equal to 4 times the difference
between ~n and the output of the previous stage.
In the circuit ofFigure 8.21(a), mismatch among C I-C4 results in integral
nonlinearity, while mismatch between each of C l-C4 and C F causes gain
error. In order to reduce these errors, each of C I-C4 can be compared with
C F and trimmed so that the effective matching is improved. Illustrated in
Figure 8.21(b), the calibration scheme utilizes the (offset-canceled) op amp
A 1 as a precision comparator and proceeds as follows. First, the mismatch
between C] (j = 1, ... , 4) and C F is represented as a voltage at node X in
the same fashion as illustrated in Figure 8.12. Next, the comparator detects
the polarity of this voltage and adjusts the value of Cj in the proper direction.
This sequence is repeated until the difference between Cj and C F is reduced
to very small values.
In practice, it is difficult to implement small, trimmable capacitors be-
cause, on the one hand, they must be approximately 500 to 1000 times less
222 Precision Techniques Chap. 8

Calibration Logic

(b)

Fig. 8.21 (a) A multibit stage in a pipelined ADC; (b) calibration of the stage
using trimmable capacitors.

than Cj and, on the other hand, they must offer sufficient trimming range. For
example, for Cj = 1 pF, a mismatch of 0.1 %, and an overall resolution of 12
bits, the trimmable capacitors will be on the order of a few femtofarads and,
more importantly, they must be adjustable in steps of a few tenths of a femto-
farad. In current technology, such small capacitors are difficult to fabricate
and typically exhibit fringe parasitics that introduce significant errors in their
values.
This problem can be overcome through the use of structures consisting
of larger capacitors that have a small equivalent capacitance. For example,
Lin et a1. [17] use capacitor ladders for this purpose.
Digital Calibration. The ADC calibration techniques described above
are based on analog processing and correction of nonidealities. Alternatively,
calibration can be performed in the digital domain to simplify the measurement
and storage of errors.
A digital calibration technique has been proposed for two-step ADCs
that employ switched-capacitor interstage 01A conversion and subtraction
Sec. 8.3 Calibration Techniques 223

[21]. This method computes the additional charge that must be pumped onto
the DAC output to correct the reconstructed analog signal and digitally stores
the voltage corresponding to that charge.
We consider the 3-bit topology shown in Figure 8.22 to illustrate this
approach. This configuration comprises the interstage DAC and subtrac-
tor/amplifier of a two-step ADC along with a calibration DAC (CDAC) and
a calibration capacitor (ecal ) . In this circuit, C3 = 2C2 = 4CI = 4CF.
During sampling, SF is on, establishing a virtual groundat X, and SI-S4 are
switched to Vin. During D/A conversion/subtraction, SF is off, CF is placed
in a negative feedback loop around AI, and 81-83 switch to either VREF or
ground according to the binary output of the first flash stage. As a result, if
all the devices are ideal, the amplifier output is

\t: - (1 C3 + C2 + CI)\I: _ D3C3 + D2C2 + DICI v:

out - + CF to CF REF.
(8.28)

where D = D3D2DI is the binary output of the previous stage. [Note that
the analog equivalent of D is given by (22 D3 + 2 1 D2 + 2° D I) VREF /2 3 ] .

Cal.
DAC
~_ _... Ccal

Fig. 8.22 ADC calibration by pumping charge onto interstage DAC output
node.

For perfectly matched capacitors, (8.28) reduces to 23 ( \tin- 2- 3 DVREF ) ,

indicating an output equal to 23 times the residue. The technique to be de-
scribed corrects the coefficient of VREF in (8.28) such that it approaches the
ideal value of 2- 3 (2 2 D3 + 2 1 D2 + 2° Dl) and hence improves the linearity of
interstage D/A conversion. For simplicity, we assume the open-loop gain of
A 1 is sufficiently high.
The calibration is performed for each digital input code and proceeds as
follows. First, SF is on, CF is charged to VREF , and C3-Cl are discharged to
224 Precision Techniques Chap. 8

ground (D3D2Dl = 000). Next, CF is placed around Al so as to generate an

output of VREF , and the digital input is incremented to D3D2DI = 001, i.e., S3
switches from ground to VREF • If Cl and CF match perfectly, then the output
goes from VREF to O. In reality, the mismatch between these capacitors results
in a small voltage at the output. To null this voltage, a comparator repeatedly
senses the output and drives the CDAC in proper direction so that the charge
pumped by Ccal onto X balances the extra charge due to mismatch between
C F and C 1, thus reducing VOUl to zero. The code thus produced by the CDAC
is stored in a RAM and applied to CDAC and Ccal whenever the digital input
from the previous stage switches 83 to VREF •
In summary, this technique is based on the fact that if the digital input of
the DAC increments by 1, the amplifier output should change by exactly VREF
and any deviations from this value can be nulled using a calibration DAC and
a capacitor.
The calibration technique depicted in Figure 8.22 suffers from accumu-
lation of errors during calibration. This problem can be alleviated using other
circuit techniques [21].
In addition to the ADC calibration techniques described in this section,
the capacitor DAC calibration of Section 8.3.1 can be employed in succes-
sive approximation converters to achieve high linearity [15]. Other digital
calibration techniques have been proposed by Karanicolas [22] and Lee [23].

8.4 RANGE OVERLAP AND DIGITAL CORRECTION

A powerful technique to relax the speed-resolution trade-off of multistep AID
converters is to provide overlap between the quantization range of successive
stages and digitally correct the binary data produced by each stage. We use a
two-step half-flash architecture to illustrate this approach.
Consider the simple two-step 10-bit ADC depicted in Figure 8.23, where
each stage resolves 5 bits. Let us first assume an ideal system where compara-
tor offsets are zero, the reference voltages generated by the first-stage ladder
are precisely 32 LSB apart, and the quantization range of the second stage is
32LSB wide. If the input voltage lies between, for example, Vj and Vj + I,
then the DAC generates a voltage equal to Vj and the subtractor produces a
residue of Vin - Vj • Since this residue is always less than 32 LSB, it never
exceeds the input range of the second stage and hence no gross errors result.
This is shown graphically in Figure 8.24(a).
Now consider a nonideal system where, for example, the first-stage
comparators exhibit finite offset. In particular, suppose that in Figure 8.23
comparators Aj and A j + 1 have offsets ~ Vj < 0 and ~ Vj+l > 0, respectively.
Sec. 8.4 Range Overlap and Digital Correction 225

..
I)
To
32 Lsa! Vj+1
"ou
I)
DAC Second
Stage
VJ - - - t - -.... C

Fig. 8.23 Residue generation in a IO-bit two-step AID converter.

Consequently, for Vj + ~ Vj < ~n < Vj+ 1 + ~ Vj + l , Aj generates a ONE

output and Aj+1 a ZERO output; hence the DAC output remains equal to Vj.
Thus, as shown in Figure 8.24(b), for ~ + ~ ~ < \tin < ~ the difference
between Vin and VDAC is negative, and for Vj+1 < Vin < Vj+1 + l:!. Vj + l ,
this difference exceeds the input range of the second stage. In the first case,
the second stage interprets the residue as zero, and in the second as 32 LSB,
regardless of its actual value. The resulting input/output characteristic of the
overall ADC is shown in Figure 8.24(c), where the dead bands Vj + t1 Vj <
Vin < Vj and Vj + 1 < "in < ~+I + 6. Vj+1 give rise to maximum differential
nonlinearities of D. ~ and D. ~+I, respectively.
In addition to offset of the first-stage comparators, several other non-
idealities can lead to the overrange problem described above. The reader can
prove that the following are among them: nonunifonnity in the references
generated by the first-stage ladder (if the DAC does not use the same lad-
der); DAC and subtractor gain error; and long hold-mode settling time of the
front-end SHA. This list indicates that, for the ADC of Figure 8.23 to attain
IO-bit resolution, the first-stage ladder and comparators, the interstage DAC
and subtractor, and the second stage must all achieve a precision of at least 10
bits. Furthermore, the first stage may be strobed only after the SHA output
226 Precision Techniques Chap. 8

Residue Residue

32 LSB + L1VJ+1
32 LSB . 32LSB

(b)

Digital
Output

~~16VJ+11
VJ ~+1 Vin

(c)
Fig.8.24 Residue plot for ADC of Figure 8.23. (a) Ideal system; (b) fi-
nite offsets in comparators Aj and A j + l ; (c) ADC input/output
characteristic in the presence of offsets.

has settled to IO-bit accuracy. In summary, almost all parts of the system
require high precision.
The above constraints all originate from the fact that the second-stage
in Figure 8.23 digitizes residues only between 0 and 32 LSB. Now, as an
example, suppose that the second stage accommodates inputs from -16 LSB
to +48 LSB, i.e., it employs 64 comparators with references ranging from -16
LSB to +48 LSB. Then, these constraints are significantly relaxed because
the total error can be as large as ± 16 LSB without introducing overrange, and
only the second-stage comparators require IO-bit resolution. This addition of
redundancy to the second stage is called "overlap," and since the second stage
has one additional bit of resolution, we say the overlap is I bit.
For the ADC of Figure 8.23, the overlap between the two stages can be
implemented in one of two forms: (I) if reference voltages from -16 LSB
to +48 LSB are available, the second-stage comparators can simply compare
the residue with these references. This is particularly easy in fully differential
architectures because a reference of + 16 LSB can be interpreted as -16 LSB
by exchanging its two terminals; (2) the DAC output can be shifted down by
16 LSB so that the residue is always positive (for errors less than 16 LSB).
These cases are depicted in Figure 8.25.
Sec. 8.4 Range Overlap and Digital Correction 227

Re.ldue

32 LSB ;~i~ :::::::::: 1

Input Range of
Second Stage

J1.V
J
VJ ~+1 Vln ~
-16 LSB j
(a)
Residue

48 LS~::~~ :::::::::::::::::::::::::::: ···········1

. . --!. ~1~VJ+11 Input Range of

Second Stage
16LSB ...... : 1"".
16 LSB + l\Vj

~+1
(b)

Fig. 8.25 Residue plot with overlap between two stages.

To gain more insight, we discuss an example using the technique shown

in Figure 8.25(b). For simplicity, we assume a resistor-ladder DAC, but the
technique can be applied to other DAC configurations as well [24]. Figure
8.26 shows a lO-bit ADC using a resistor-ladder DAC. Note that the parallel
resistors at the two ends of the DAC ladder shift its tap voltages by 16 LSB,
thereby generating the midpoints of the voltage segments produced by the
first-stage ladder. If comparators A j and Aj+1 interpret Vin to lie between Vj
and V)+l, then three possibilities exist: Vin is slightly less than V), but A j has
a negative offset; ~n is indeed between V) and V)+I; or \tin is slightly greater
than Vj + l , but Aj+l has a positive offset. We explain how corrections are
made in the first and third cases.
If the input is interpreted to be between Vj and Vj+l, the AND gate N,
generates an output of ONE, turning on Sj and providing a DAC output equal
to V) - 16 LSB. Thus, so long as various errors in the first stage, the DAC,
and the subtractor add up to less than 16 LSB, the residue remains positive,
and hence no overrange occurs.
228 Precision Techniques Chap. 8

VJ+1

32LSB
I VJ . -- ............

Fig.8.26 JO-bit ADC using a resistor-ladder DAC.

In order for the third case explained above not to introduce overrange
errors, the second stage is designed for 6-bit resolution; i.e., it quantizes
residues ranging from 1 LSB to 64 LSB. As a consequence, for the typical
situation depicted in Figure 8.26, the second stage digitizes the difference
between ~n and Vj - (16 LSB) and has no overrange errors if \t'in < Vj+1 + 16
LSB.
In order to produce the final binary output, the data generated by the
two stages must be digitally corrected. If the digital output of the first stage is
represented by a binary number X I = D l o •.. D6, then its value normalized to
the LSB of the 10-bit system is X I = DI 0 29 + D928 + ··.+ D62s. Similarly,
the digital output of the second stage, X2 = D s ... Do, can be expressed as
X2 Ds2 s + D424 + · · · + Do2°. Because the DAC output is shifted down
=
by 16 LSB, the final output is
4
Y = (DI02 9 + D928 + · · . + D62s ) - 2
(8.29)
+(Ds2 5 + D424 + ... + Do20).
This equation indicates that the digital correction procedure consists of three
steps: (1) shift Dlo ... D6 to the left by 5 bits, (2) subtract the binary number
Chap. 8 References 229

10000 from the result of step 1, and (3) add Ds ... Do to the difference obtained
in step 2.
We should mention two important points. First, the overlap and digital
correction techniques described above cannot correct for subtractor gain error.
Second, the total amount of overlap between consecutive stages can be more
or less than 1 bit, depending on the overall anticipated error.
In the ADC of Figure 8.26, the overlap is implemented by expanding the
quantization range of the second stage, resulting in a 5-bit first stage and a 6-bit
second stage. Alternatively, the first stage can be designed to have a higher
resolution, allowing fewer comparators in the second stage. For example,
the ADC can resolve 6 bits in the first stage and 5 bits in the second. The
exact allocation of resolution to the stages depends on various issues pertinent
to each particular design. For example, in CMOS technology, comparators
typically suffer from severe trade-offs among their speed, resolution, power
dissipation, and input capacitance. Thus, it is desirable to use fewer high-
resolution comparators in the second stage and hence more low-resolution
comparators in the first stage. This also relaxes the gain accuracy required of
the subtractor. On the other hand, as the resolution of the first stage and hence
that of the interstage DAC increases, the DAC may exhibit a longer settling
time.

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